10b57cec5SDimitry Andric//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the RISC-V instructions from the standard 'F', 100b57cec5SDimitry Andric// Single-Precision Floating-Point instruction set extension. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 150b57cec5SDimitry Andric// RISC-V specific DAG Nodes. 160b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 170b57cec5SDimitry Andric 180b57cec5SDimitry Andricdef SDT_RISCVFMV_W_X_RV64 190b57cec5SDimitry Andric : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 200b57cec5SDimitry Andricdef SDT_RISCVFMV_X_ANYEXTW_RV64 210b57cec5SDimitry Andric : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 22fe6060f1SDimitry Andricdef STD_RISCVFCVT_W_RV64 23fe6060f1SDimitry Andric : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisFP<1>]>; 24349cc55cSDimitry Andricdef STD_RISCVFCVT_X 25349cc55cSDimitry Andric : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>; 260b57cec5SDimitry Andric 270b57cec5SDimitry Andricdef riscv_fmv_w_x_rv64 280b57cec5SDimitry Andric : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>; 290b57cec5SDimitry Andricdef riscv_fmv_x_anyextw_rv64 300b57cec5SDimitry Andric : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>; 31349cc55cSDimitry Andricdef riscv_fcvt_w_rtz_rv64 32349cc55cSDimitry Andric : SDNode<"RISCVISD::FCVT_W_RTZ_RV64", STD_RISCVFCVT_W_RV64>; 33349cc55cSDimitry Andricdef riscv_fcvt_wu_rtz_rv64 34349cc55cSDimitry Andric : SDNode<"RISCVISD::FCVT_WU_RTZ_RV64", STD_RISCVFCVT_W_RV64>; 35349cc55cSDimitry Andricdef riscv_fcvt_x_rtz 36349cc55cSDimitry Andric : SDNode<"RISCVISD::FCVT_X_RTZ", STD_RISCVFCVT_X>; 37349cc55cSDimitry Andricdef riscv_fcvt_xu_rtz 38349cc55cSDimitry Andric : SDNode<"RISCVISD::FCVT_XU_RTZ", STD_RISCVFCVT_X>; 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 410b57cec5SDimitry Andric// Operand and SDNode transformation definitions. 420b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric// Floating-point rounding mode 450b57cec5SDimitry Andric 460b57cec5SDimitry Andricdef FRMArg : AsmOperandClass { 470b57cec5SDimitry Andric let Name = "FRMArg"; 480b57cec5SDimitry Andric let RenderMethod = "addFRMArgOperands"; 490b57cec5SDimitry Andric let DiagnosticType = "InvalidFRMArg"; 500b57cec5SDimitry Andric} 510b57cec5SDimitry Andric 520b57cec5SDimitry Andricdef frmarg : Operand<XLenVT> { 530b57cec5SDimitry Andric let ParserMatchClass = FRMArg; 540b57cec5SDimitry Andric let PrintMethod = "printFRMArg"; 550b57cec5SDimitry Andric let DecoderMethod = "decodeFRMArg"; 560b57cec5SDimitry Andric} 570b57cec5SDimitry Andric 580b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 590b57cec5SDimitry Andric// Instruction class templates 600b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 610b57cec5SDimitry Andric 620b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 630b57cec5SDimitry Andricclass FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr> 64fe6060f1SDimitry Andric : RVInstR4Frm<0b00, opcode, (outs FPR32:$rd), 650b57cec5SDimitry Andric (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3), 660b57cec5SDimitry Andric opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andricclass FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr> 690b57cec5SDimitry Andric : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 700b57cec5SDimitry Andric (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 710b57cec5SDimitry Andric 720b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 730b57cec5SDimitry Andricclass FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 740b57cec5SDimitry Andric : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd), 755ffd83dbSDimitry Andric (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">; 760b57cec5SDimitry Andric 770b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 780b57cec5SDimitry Andricclass FPALUS_rr_frm<bits<7> funct7, string opcodestr> 790b57cec5SDimitry Andric : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd), 800b57cec5SDimitry Andric (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr, 810b57cec5SDimitry Andric "$rd, $rs1, $rs2, $funct3">; 820b57cec5SDimitry Andric 830b57cec5SDimitry Andricclass FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr> 840b57cec5SDimitry Andric : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 850b57cec5SDimitry Andric (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>; 860b57cec5SDimitry Andric 870b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 880b57cec5SDimitry Andricclass FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty, 890b57cec5SDimitry Andric RegisterClass rs1ty, string opcodestr> 900b57cec5SDimitry Andric : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), 910b57cec5SDimitry Andric opcodestr, "$rd, $rs1">; 920b57cec5SDimitry Andric 930b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 940b57cec5SDimitry Andricclass FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty, 950b57cec5SDimitry Andric string opcodestr> 960b57cec5SDimitry Andric : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd), 970b57cec5SDimitry Andric (ins rs1ty:$rs1, frmarg:$funct3), opcodestr, 980b57cec5SDimitry Andric "$rd, $rs1, $funct3">; 990b57cec5SDimitry Andric 1000b57cec5SDimitry Andricclass FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr, 1010b57cec5SDimitry Andric RegisterClass rdty, RegisterClass rs1ty> 1020b57cec5SDimitry Andric : InstAlias<OpcodeStr#" $rd, $rs1", 1030b57cec5SDimitry Andric (Inst rdty:$rd, rs1ty:$rs1, 0b111)>; 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 1060b57cec5SDimitry Andricclass FPCmpS_rr<bits<3> funct3, string opcodestr> 1070b57cec5SDimitry Andric : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd), 10813138422SDimitry Andric (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">, 10913138422SDimitry Andric Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>; 1100b57cec5SDimitry Andric 1110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 1120b57cec5SDimitry Andric// Instructions 1130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 1140b57cec5SDimitry Andric 1150b57cec5SDimitry Andriclet Predicates = [HasStdExtF] in { 1160b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 1170b57cec5SDimitry Andricdef FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd), 1180b57cec5SDimitry Andric (ins GPR:$rs1, simm12:$imm12), 11913138422SDimitry Andric "flw", "$rd, ${imm12}(${rs1})">, 1205ffd83dbSDimitry Andric Sched<[WriteFLD32, ReadFMemBase]>; 1210b57cec5SDimitry Andric 1220b57cec5SDimitry Andric// Operands for stores are in the order srcreg, base, offset rather than 1230b57cec5SDimitry Andric// reflecting the order these fields are specified in the instruction 1240b57cec5SDimitry Andric// encoding. 1250b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 1260b57cec5SDimitry Andricdef FSW : RVInstS<0b010, OPC_STORE_FP, (outs), 1270b57cec5SDimitry Andric (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), 12813138422SDimitry Andric "fsw", "$rs2, ${imm12}(${rs1})">, 1295ffd83dbSDimitry Andric Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>; 1300b57cec5SDimitry Andric 13113138422SDimitry Andricdef FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">, 132fe6060f1SDimitry Andric Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 1330b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">; 13413138422SDimitry Andricdef FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">, 135fe6060f1SDimitry Andric Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 1360b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">; 13713138422SDimitry Andricdef FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">, 138fe6060f1SDimitry Andric Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 1390b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">; 14013138422SDimitry Andricdef FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">, 141fe6060f1SDimitry Andric Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 1420b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">; 1430b57cec5SDimitry Andric 14413138422SDimitry Andricdef FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">, 14513138422SDimitry Andric Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 1460b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FADD_S, "fadd.s">; 14713138422SDimitry Andricdef FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">, 14813138422SDimitry Andric Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 1490b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FSUB_S, "fsub.s">; 15013138422SDimitry Andricdef FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">, 15113138422SDimitry Andric Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>; 1520b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 15313138422SDimitry Andricdef FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">, 15413138422SDimitry Andric Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; 1550b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">; 1560b57cec5SDimitry Andric 15713138422SDimitry Andricdef FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">, 15813138422SDimitry Andric Sched<[WriteFSqrt32, ReadFSqrt32]> { 1590b57cec5SDimitry Andric let rs2 = 0b00000; 1600b57cec5SDimitry Andric} 1610b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>; 1620b57cec5SDimitry Andric 1635ffd83dbSDimitry Andricdef FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">, 1645ffd83dbSDimitry Andric Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 1655ffd83dbSDimitry Andricdef FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">, 1665ffd83dbSDimitry Andric Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 1675ffd83dbSDimitry Andricdef FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">, 1685ffd83dbSDimitry Andric Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 1695ffd83dbSDimitry Andricdef FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">, 1705ffd83dbSDimitry Andric Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>; 1715ffd83dbSDimitry Andricdef FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">, 1725ffd83dbSDimitry Andric Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>; 1730b57cec5SDimitry Andric 17413138422SDimitry Andricdef FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">, 17513138422SDimitry Andric Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 1760b57cec5SDimitry Andric let rs2 = 0b00000; 1770b57cec5SDimitry Andric} 1780b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>; 1790b57cec5SDimitry Andric 18013138422SDimitry Andricdef FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">, 18113138422SDimitry Andric Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 1820b57cec5SDimitry Andric let rs2 = 0b00001; 1830b57cec5SDimitry Andric} 1840b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>; 1850b57cec5SDimitry Andric 18613138422SDimitry Andricdef FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">, 18713138422SDimitry Andric Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> { 1880b57cec5SDimitry Andric let rs2 = 0b00000; 1890b57cec5SDimitry Andric} 1900b57cec5SDimitry Andric 1910b57cec5SDimitry Andricdef FEQ_S : FPCmpS_rr<0b010, "feq.s">; 1920b57cec5SDimitry Andricdef FLT_S : FPCmpS_rr<0b001, "flt.s">; 1930b57cec5SDimitry Andricdef FLE_S : FPCmpS_rr<0b000, "fle.s">; 1940b57cec5SDimitry Andric 19513138422SDimitry Andricdef FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">, 19613138422SDimitry Andric Sched<[WriteFClass32, ReadFClass32]> { 1970b57cec5SDimitry Andric let rs2 = 0b00000; 1980b57cec5SDimitry Andric} 1990b57cec5SDimitry Andric 20013138422SDimitry Andricdef FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">, 20113138422SDimitry Andric Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 2020b57cec5SDimitry Andric let rs2 = 0b00000; 2030b57cec5SDimitry Andric} 2040b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>; 2050b57cec5SDimitry Andric 20613138422SDimitry Andricdef FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">, 20713138422SDimitry Andric Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 2080b57cec5SDimitry Andric let rs2 = 0b00001; 2090b57cec5SDimitry Andric} 2100b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>; 2110b57cec5SDimitry Andric 21213138422SDimitry Andricdef FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">, 21313138422SDimitry Andric Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> { 2140b57cec5SDimitry Andric let rs2 = 0b00000; 2150b57cec5SDimitry Andric} 2160b57cec5SDimitry Andric} // Predicates = [HasStdExtF] 2170b57cec5SDimitry Andric 2180b57cec5SDimitry Andriclet Predicates = [HasStdExtF, IsRV64] in { 21913138422SDimitry Andricdef FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">, 22013138422SDimitry Andric Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 2210b57cec5SDimitry Andric let rs2 = 0b00010; 2220b57cec5SDimitry Andric} 2230b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; 2240b57cec5SDimitry Andric 22513138422SDimitry Andricdef FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">, 22613138422SDimitry Andric Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 2270b57cec5SDimitry Andric let rs2 = 0b00011; 2280b57cec5SDimitry Andric} 2290b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>; 2300b57cec5SDimitry Andric 23113138422SDimitry Andricdef FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">, 23213138422SDimitry Andric Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 2330b57cec5SDimitry Andric let rs2 = 0b00010; 2340b57cec5SDimitry Andric} 2350b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>; 2360b57cec5SDimitry Andric 23713138422SDimitry Andricdef FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">, 23813138422SDimitry Andric Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 2390b57cec5SDimitry Andric let rs2 = 0b00011; 2400b57cec5SDimitry Andric} 2410b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>; 2420b57cec5SDimitry Andric} // Predicates = [HasStdExtF, IsRV64] 2430b57cec5SDimitry Andric 2440b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2450b57cec5SDimitry Andric// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 2460b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2470b57cec5SDimitry Andric 2480b57cec5SDimitry Andriclet Predicates = [HasStdExtF] in { 2490b57cec5SDimitry Andricdef : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>; 2500b57cec5SDimitry Andricdef : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 2510b57cec5SDimitry Andric 2520b57cec5SDimitry Andricdef : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 2530b57cec5SDimitry Andricdef : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 2540b57cec5SDimitry Andricdef : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 2550b57cec5SDimitry Andric 2560b57cec5SDimitry Andric// fgt.s/fge.s are recognised by the GNU assembler but the canonical 2570b57cec5SDimitry Andric// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. 2580b57cec5SDimitry Andricdef : InstAlias<"fgt.s $rd, $rs, $rt", 2590b57cec5SDimitry Andric (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 2600b57cec5SDimitry Andricdef : InstAlias<"fge.s $rd, $rs, $rt", 2610b57cec5SDimitry Andric (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 2620b57cec5SDimitry Andric 2630b57cec5SDimitry Andric// The following csr instructions actually alias instructions from the base ISA. 2640b57cec5SDimitry Andric// However, it only makes sense to support them when the F extension is enabled. 2650b57cec5SDimitry Andric// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". 266fe6060f1SDimitry Andricdef : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>; 267fe6060f1SDimitry Andricdef : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>; 268fe6060f1SDimitry Andricdef : InstAlias<"fscsr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 2>; 2690b57cec5SDimitry Andric 2708bcb0991SDimitry Andric// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them 2718bcb0991SDimitry Andric// zero weight. 272fe6060f1SDimitry Andricdef : InstAlias<"frsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>; 273fe6060f1SDimitry Andricdef : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>; 274fe6060f1SDimitry Andricdef : InstAlias<"fssr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 0>; 2758bcb0991SDimitry Andric 276fe6060f1SDimitry Andricdef : InstAlias<"frrm $rd", (CSRRS GPR:$rd, SysRegFRM.Encoding, X0), 2>; 277fe6060f1SDimitry Andricdef : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>; 278fe6060f1SDimitry Andricdef : InstAlias<"fsrm $rs", (CSRRW X0, SysRegFRM.Encoding, GPR:$rs), 2>; 279fe6060f1SDimitry Andricdef : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>; 280fe6060f1SDimitry Andricdef : InstAlias<"fsrmi $imm", (CSRRWI X0, SysRegFRM.Encoding, uimm5:$imm), 2>; 2810b57cec5SDimitry Andric 282fe6060f1SDimitry Andricdef : InstAlias<"frflags $rd", (CSRRS GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>; 283fe6060f1SDimitry Andricdef : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>; 284fe6060f1SDimitry Andricdef : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>; 285fe6060f1SDimitry Andricdef : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>; 286fe6060f1SDimitry Andricdef : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>; 2870b57cec5SDimitry Andric 2880b57cec5SDimitry Andric// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both 2890b57cec5SDimitry Andric// spellings should be supported by standard tools. 2900b57cec5SDimitry Andricdef : MnemonicAlias<"fmv.s.x", "fmv.w.x">; 2910b57cec5SDimitry Andricdef : MnemonicAlias<"fmv.x.s", "fmv.x.w">; 2920b57cec5SDimitry Andric 2930b57cec5SDimitry Andricdef PseudoFLW : PseudoFloatLoad<"flw", FPR32>; 2940b57cec5SDimitry Andricdef PseudoFSW : PseudoStore<"fsw", FPR32>; 2950b57cec5SDimitry Andric} // Predicates = [HasStdExtF] 2960b57cec5SDimitry Andric 2970b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2980b57cec5SDimitry Andric// Pseudo-instructions and codegen patterns 2990b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 3000b57cec5SDimitry Andric 3015ffd83dbSDimitry Andric/// Floating point constants 3025ffd83dbSDimitry Andricdef fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 3035ffd83dbSDimitry Andric 3040b57cec5SDimitry Andric/// Generic pattern classes 3050b57cec5SDimitry Andricclass PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst> 3060b57cec5SDimitry Andric : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>; 3070b57cec5SDimitry Andric 3080b57cec5SDimitry Andricclass PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 3090b57cec5SDimitry Andric : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>; 3100b57cec5SDimitry Andric 3110b57cec5SDimitry Andriclet Predicates = [HasStdExtF] in { 3120b57cec5SDimitry Andric 3135ffd83dbSDimitry Andric/// Float constants 3145ffd83dbSDimitry Andricdef : Pat<(f32 (fpimm0)), (FMV_W_X X0)>; 3155ffd83dbSDimitry Andric 3160b57cec5SDimitry Andric/// Float conversion operations 3170b57cec5SDimitry Andric 3180b57cec5SDimitry Andric// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 3190b57cec5SDimitry Andric// are defined later. 3200b57cec5SDimitry Andric 3210b57cec5SDimitry Andric/// Float arithmetic operations 3220b57cec5SDimitry Andric 3230b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fadd, FADD_S>; 3240b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fsub, FSUB_S>; 3250b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fmul, FMUL_S>; 3260b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>; 3270b57cec5SDimitry Andric 3280b57cec5SDimitry Andricdef : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; 3290b57cec5SDimitry Andric 3300b57cec5SDimitry Andricdef : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; 3310b57cec5SDimitry Andricdef : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; 3320b57cec5SDimitry Andric 3330b57cec5SDimitry Andricdef : PatFpr32Fpr32<fcopysign, FSGNJ_S>; 3340b57cec5SDimitry Andricdef : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 3350b57cec5SDimitry Andric 3360b57cec5SDimitry Andric// fmadd: rs1 * rs2 + rs3 3370b57cec5SDimitry Andricdef : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3), 3380b57cec5SDimitry Andric (FMADD_S $rs1, $rs2, $rs3, 0b111)>; 3390b57cec5SDimitry Andric 3400b57cec5SDimitry Andric// fmsub: rs1 * rs2 - rs3 3410b57cec5SDimitry Andricdef : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), 3420b57cec5SDimitry Andric (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 3430b57cec5SDimitry Andric 3440b57cec5SDimitry Andric// fnmsub: -rs1 * rs2 + rs3 3450b57cec5SDimitry Andricdef : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), 3460b57cec5SDimitry Andric (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 3470b57cec5SDimitry Andric 3480b57cec5SDimitry Andric// fnmadd: -rs1 * rs2 - rs3 3490b57cec5SDimitry Andricdef : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), 3500b57cec5SDimitry Andric (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 3510b57cec5SDimitry Andric 352fe6060f1SDimitry Andric// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 353fe6060f1SDimitry Andric// LLVM's fminnum and fmaxnum 3540b57cec5SDimitry Andric// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 3550b57cec5SDimitry Andricdef : PatFpr32Fpr32<fminnum, FMIN_S>; 3560b57cec5SDimitry Andricdef : PatFpr32Fpr32<fmaxnum, FMAX_S>; 3570b57cec5SDimitry Andric 3580b57cec5SDimitry Andric/// Setcc 3590b57cec5SDimitry Andric 3600b57cec5SDimitry Andricdef : PatFpr32Fpr32<seteq, FEQ_S>; 3610b57cec5SDimitry Andricdef : PatFpr32Fpr32<setoeq, FEQ_S>; 3620b57cec5SDimitry Andricdef : PatFpr32Fpr32<setlt, FLT_S>; 3630b57cec5SDimitry Andricdef : PatFpr32Fpr32<setolt, FLT_S>; 3640b57cec5SDimitry Andricdef : PatFpr32Fpr32<setle, FLE_S>; 3650b57cec5SDimitry Andricdef : PatFpr32Fpr32<setole, FLE_S>; 3660b57cec5SDimitry Andric 3670b57cec5SDimitry Andricdef Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>; 3680b57cec5SDimitry Andric 3690b57cec5SDimitry Andric/// Loads 3700b57cec5SDimitry Andric 371fe6060f1SDimitry Andricdefm : LdPat<load, FLW, f32>; 3720b57cec5SDimitry Andric 3730b57cec5SDimitry Andric/// Stores 3740b57cec5SDimitry Andric 375fe6060f1SDimitry Andricdefm : StPat<store, FSW, FPR32, f32>; 3760b57cec5SDimitry Andric 3770b57cec5SDimitry Andric} // Predicates = [HasStdExtF] 3780b57cec5SDimitry Andric 3790b57cec5SDimitry Andriclet Predicates = [HasStdExtF, IsRV32] in { 380e8d8bef9SDimitry Andric// Moves (no conversion) 381fe6060f1SDimitry Andricdef : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>; 382fe6060f1SDimitry Andricdef : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>; 383e8d8bef9SDimitry Andric 3840b57cec5SDimitry Andric// float->[u]int. Round-to-zero must be used. 385fe6060f1SDimitry Andricdef : Pat<(i32 (fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>; 386fe6060f1SDimitry Andricdef : Pat<(i32 (fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>; 387fe6060f1SDimitry Andric 388349cc55cSDimitry Andric// Saturating float->[u]int32. 389349cc55cSDimitry Andricdef : Pat<(i32 (riscv_fcvt_x_rtz FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>; 390349cc55cSDimitry Andricdef : Pat<(i32 (riscv_fcvt_xu_rtz FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>; 391349cc55cSDimitry Andric 392fe6060f1SDimitry Andric// float->int32 with current rounding mode. 393fe6060f1SDimitry Andricdef : Pat<(i32 (lrint FPR32:$rs1)), (FCVT_W_S $rs1, 0b111)>; 394fe6060f1SDimitry Andric 395fe6060f1SDimitry Andric// float->int32 rounded to nearest with ties rounded away from zero. 396fe6060f1SDimitry Andricdef : Pat<(i32 (lround FPR32:$rs1)), (FCVT_W_S $rs1, 0b100)>; 3970b57cec5SDimitry Andric 3980b57cec5SDimitry Andric// [u]int->float. Match GCC and default to using dynamic rounding mode. 399fe6060f1SDimitry Andricdef : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>; 400fe6060f1SDimitry Andricdef : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; 4010b57cec5SDimitry Andric} // Predicates = [HasStdExtF, IsRV32] 4020b57cec5SDimitry Andric 4030b57cec5SDimitry Andriclet Predicates = [HasStdExtF, IsRV64] in { 404e8d8bef9SDimitry Andric// Moves (no conversion) 4050b57cec5SDimitry Andricdef : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; 4060b57cec5SDimitry Andricdef : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; 407e8d8bef9SDimitry Andricdef : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32), 4080b57cec5SDimitry Andric (FMV_X_W FPR32:$src)>; 4090b57cec5SDimitry Andric 410fe6060f1SDimitry Andric// Use target specific isd nodes to help us remember the result is sign 411fe6060f1SDimitry Andric// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 412fe6060f1SDimitry Andric// duplicated if it has another user that didn't need the sign_extend. 413349cc55cSDimitry Andricdef : Pat<(riscv_fcvt_w_rtz_rv64 FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 414349cc55cSDimitry Andricdef : Pat<(riscv_fcvt_wu_rtz_rv64 FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 4150b57cec5SDimitry Andric 416fe6060f1SDimitry Andric// float->[u]int64. Round-to-zero must be used. 417fe6060f1SDimitry Andricdef : Pat<(i64 (fp_to_sint FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>; 418fe6060f1SDimitry Andricdef : Pat<(i64 (fp_to_uint FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>; 419fe6060f1SDimitry Andric 420349cc55cSDimitry Andric// Saturating float->[u]int64. 421349cc55cSDimitry Andricdef : Pat<(i64 (riscv_fcvt_x_rtz FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>; 422349cc55cSDimitry Andricdef : Pat<(i64 (riscv_fcvt_xu_rtz FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>; 423349cc55cSDimitry Andric 424fe6060f1SDimitry Andric// float->int64 with current rounding mode. 425fe6060f1SDimitry Andricdef : Pat<(i64 (lrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>; 426fe6060f1SDimitry Andricdef : Pat<(i64 (llrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>; 427fe6060f1SDimitry Andric 428fe6060f1SDimitry Andric// float->int64 rounded to neartest with ties rounded away from zero. 429fe6060f1SDimitry Andricdef : Pat<(i64 (lround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>; 430fe6060f1SDimitry Andricdef : Pat<(i64 (llround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>; 4310b57cec5SDimitry Andric 4320b57cec5SDimitry Andric// [u]int->fp. Match GCC and default to using dynamic rounding mode. 433fe6060f1SDimitry Andricdef : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>; 434fe6060f1SDimitry Andricdef : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>; 435fe6060f1SDimitry Andricdef : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>; 436fe6060f1SDimitry Andricdef : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>; 4370b57cec5SDimitry Andric} // Predicates = [HasStdExtF, IsRV64] 438