10b57cec5SDimitry Andric//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the RISC-V instructions from the standard 'F', 100b57cec5SDimitry Andric// Single-Precision Floating-Point instruction set extension. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 150b57cec5SDimitry Andric// RISC-V specific DAG Nodes. 160b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 170b57cec5SDimitry Andric 180b57cec5SDimitry Andricdef SDT_RISCVFMV_W_X_RV64 190b57cec5SDimitry Andric : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 200b57cec5SDimitry Andricdef SDT_RISCVFMV_X_ANYEXTW_RV64 210b57cec5SDimitry Andric : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 220b57cec5SDimitry Andric 230b57cec5SDimitry Andricdef riscv_fmv_w_x_rv64 240b57cec5SDimitry Andric : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>; 250b57cec5SDimitry Andricdef riscv_fmv_x_anyextw_rv64 260b57cec5SDimitry Andric : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>; 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 290b57cec5SDimitry Andric// Operand and SDNode transformation definitions. 300b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 310b57cec5SDimitry Andric 320b57cec5SDimitry Andric// Floating-point rounding mode 330b57cec5SDimitry Andric 340b57cec5SDimitry Andricdef FRMArg : AsmOperandClass { 350b57cec5SDimitry Andric let Name = "FRMArg"; 360b57cec5SDimitry Andric let RenderMethod = "addFRMArgOperands"; 370b57cec5SDimitry Andric let DiagnosticType = "InvalidFRMArg"; 380b57cec5SDimitry Andric} 390b57cec5SDimitry Andric 400b57cec5SDimitry Andricdef frmarg : Operand<XLenVT> { 410b57cec5SDimitry Andric let ParserMatchClass = FRMArg; 420b57cec5SDimitry Andric let PrintMethod = "printFRMArg"; 430b57cec5SDimitry Andric let DecoderMethod = "decodeFRMArg"; 440b57cec5SDimitry Andric} 450b57cec5SDimitry Andric 460b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 470b57cec5SDimitry Andric// Instruction class templates 480b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 490b57cec5SDimitry Andric 500b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 510b57cec5SDimitry Andricclass FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr> 520b57cec5SDimitry Andric : RVInstR4<0b00, opcode, (outs FPR32:$rd), 530b57cec5SDimitry Andric (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3), 540b57cec5SDimitry Andric opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 550b57cec5SDimitry Andric 560b57cec5SDimitry Andricclass FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr> 570b57cec5SDimitry Andric : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 580b57cec5SDimitry Andric (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 590b57cec5SDimitry Andric 600b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 610b57cec5SDimitry Andricclass FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 620b57cec5SDimitry Andric : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd), 630b57cec5SDimitry Andric (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">; 640b57cec5SDimitry Andric 650b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 660b57cec5SDimitry Andricclass FPALUS_rr_frm<bits<7> funct7, string opcodestr> 670b57cec5SDimitry Andric : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd), 680b57cec5SDimitry Andric (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr, 690b57cec5SDimitry Andric "$rd, $rs1, $rs2, $funct3">; 700b57cec5SDimitry Andric 710b57cec5SDimitry Andricclass FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr> 720b57cec5SDimitry Andric : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 730b57cec5SDimitry Andric (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>; 740b57cec5SDimitry Andric 750b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 760b57cec5SDimitry Andricclass FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty, 770b57cec5SDimitry Andric RegisterClass rs1ty, string opcodestr> 780b57cec5SDimitry Andric : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), 790b57cec5SDimitry Andric opcodestr, "$rd, $rs1">; 800b57cec5SDimitry Andric 810b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 820b57cec5SDimitry Andricclass FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty, 830b57cec5SDimitry Andric string opcodestr> 840b57cec5SDimitry Andric : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd), 850b57cec5SDimitry Andric (ins rs1ty:$rs1, frmarg:$funct3), opcodestr, 860b57cec5SDimitry Andric "$rd, $rs1, $funct3">; 870b57cec5SDimitry Andric 880b57cec5SDimitry Andricclass FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr, 890b57cec5SDimitry Andric RegisterClass rdty, RegisterClass rs1ty> 900b57cec5SDimitry Andric : InstAlias<OpcodeStr#" $rd, $rs1", 910b57cec5SDimitry Andric (Inst rdty:$rd, rs1ty:$rs1, 0b111)>; 920b57cec5SDimitry Andric 930b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 940b57cec5SDimitry Andricclass FPCmpS_rr<bits<3> funct3, string opcodestr> 950b57cec5SDimitry Andric : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd), 960b57cec5SDimitry Andric (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">; 970b57cec5SDimitry Andric 980b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 990b57cec5SDimitry Andric// Instructions 1000b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 1010b57cec5SDimitry Andric 1020b57cec5SDimitry Andriclet Predicates = [HasStdExtF] in { 1030b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 1040b57cec5SDimitry Andricdef FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd), 1050b57cec5SDimitry Andric (ins GPR:$rs1, simm12:$imm12), 1060b57cec5SDimitry Andric "flw", "$rd, ${imm12}(${rs1})">; 1070b57cec5SDimitry Andric 1080b57cec5SDimitry Andric// Operands for stores are in the order srcreg, base, offset rather than 1090b57cec5SDimitry Andric// reflecting the order these fields are specified in the instruction 1100b57cec5SDimitry Andric// encoding. 1110b57cec5SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 1120b57cec5SDimitry Andricdef FSW : RVInstS<0b010, OPC_STORE_FP, (outs), 1130b57cec5SDimitry Andric (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), 1140b57cec5SDimitry Andric "fsw", "$rs2, ${imm12}(${rs1})">; 1150b57cec5SDimitry Andric 1160b57cec5SDimitry Andricdef FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">; 1170b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">; 1180b57cec5SDimitry Andricdef FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">; 1190b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">; 1200b57cec5SDimitry Andricdef FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">; 1210b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">; 1220b57cec5SDimitry Andricdef FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">; 1230b57cec5SDimitry Andricdef : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">; 1240b57cec5SDimitry Andric 1250b57cec5SDimitry Andricdef FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">; 1260b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FADD_S, "fadd.s">; 1270b57cec5SDimitry Andricdef FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">; 1280b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FSUB_S, "fsub.s">; 1290b57cec5SDimitry Andricdef FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">; 1300b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 1310b57cec5SDimitry Andricdef FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">; 1320b57cec5SDimitry Andricdef : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">; 1330b57cec5SDimitry Andric 1340b57cec5SDimitry Andricdef FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s"> { 1350b57cec5SDimitry Andric let rs2 = 0b00000; 1360b57cec5SDimitry Andric} 1370b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>; 1380b57cec5SDimitry Andric 1390b57cec5SDimitry Andricdef FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">; 1400b57cec5SDimitry Andricdef FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">; 1410b57cec5SDimitry Andricdef FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">; 1420b57cec5SDimitry Andricdef FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">; 1430b57cec5SDimitry Andricdef FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">; 1440b57cec5SDimitry Andric 1450b57cec5SDimitry Andricdef FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s"> { 1460b57cec5SDimitry Andric let rs2 = 0b00000; 1470b57cec5SDimitry Andric} 1480b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>; 1490b57cec5SDimitry Andric 1500b57cec5SDimitry Andricdef FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s"> { 1510b57cec5SDimitry Andric let rs2 = 0b00001; 1520b57cec5SDimitry Andric} 1530b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>; 1540b57cec5SDimitry Andric 1550b57cec5SDimitry Andricdef FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w"> { 1560b57cec5SDimitry Andric let rs2 = 0b00000; 1570b57cec5SDimitry Andric} 1580b57cec5SDimitry Andric 1590b57cec5SDimitry Andricdef FEQ_S : FPCmpS_rr<0b010, "feq.s">; 1600b57cec5SDimitry Andricdef FLT_S : FPCmpS_rr<0b001, "flt.s">; 1610b57cec5SDimitry Andricdef FLE_S : FPCmpS_rr<0b000, "fle.s">; 1620b57cec5SDimitry Andric 1630b57cec5SDimitry Andricdef FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s"> { 1640b57cec5SDimitry Andric let rs2 = 0b00000; 1650b57cec5SDimitry Andric} 1660b57cec5SDimitry Andric 1670b57cec5SDimitry Andricdef FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w"> { 1680b57cec5SDimitry Andric let rs2 = 0b00000; 1690b57cec5SDimitry Andric} 1700b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>; 1710b57cec5SDimitry Andric 1720b57cec5SDimitry Andricdef FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu"> { 1730b57cec5SDimitry Andric let rs2 = 0b00001; 1740b57cec5SDimitry Andric} 1750b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>; 1760b57cec5SDimitry Andric 1770b57cec5SDimitry Andricdef FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x"> { 1780b57cec5SDimitry Andric let rs2 = 0b00000; 1790b57cec5SDimitry Andric} 1800b57cec5SDimitry Andric} // Predicates = [HasStdExtF] 1810b57cec5SDimitry Andric 1820b57cec5SDimitry Andriclet Predicates = [HasStdExtF, IsRV64] in { 1830b57cec5SDimitry Andricdef FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s"> { 1840b57cec5SDimitry Andric let rs2 = 0b00010; 1850b57cec5SDimitry Andric} 1860b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; 1870b57cec5SDimitry Andric 1880b57cec5SDimitry Andricdef FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s"> { 1890b57cec5SDimitry Andric let rs2 = 0b00011; 1900b57cec5SDimitry Andric} 1910b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>; 1920b57cec5SDimitry Andric 1930b57cec5SDimitry Andricdef FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l"> { 1940b57cec5SDimitry Andric let rs2 = 0b00010; 1950b57cec5SDimitry Andric} 1960b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>; 1970b57cec5SDimitry Andric 1980b57cec5SDimitry Andricdef FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu"> { 1990b57cec5SDimitry Andric let rs2 = 0b00011; 2000b57cec5SDimitry Andric} 2010b57cec5SDimitry Andricdef : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>; 2020b57cec5SDimitry Andric} // Predicates = [HasStdExtF, IsRV64] 2030b57cec5SDimitry Andric 2040b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2050b57cec5SDimitry Andric// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 2060b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2070b57cec5SDimitry Andric 2080b57cec5SDimitry Andriclet Predicates = [HasStdExtF] in { 2090b57cec5SDimitry Andricdef : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>; 2100b57cec5SDimitry Andricdef : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 2110b57cec5SDimitry Andric 2120b57cec5SDimitry Andricdef : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 2130b57cec5SDimitry Andricdef : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 2140b57cec5SDimitry Andricdef : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 2150b57cec5SDimitry Andric 2160b57cec5SDimitry Andric// fgt.s/fge.s are recognised by the GNU assembler but the canonical 2170b57cec5SDimitry Andric// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. 2180b57cec5SDimitry Andricdef : InstAlias<"fgt.s $rd, $rs, $rt", 2190b57cec5SDimitry Andric (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 2200b57cec5SDimitry Andricdef : InstAlias<"fge.s $rd, $rs, $rt", 2210b57cec5SDimitry Andric (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 2220b57cec5SDimitry Andric 2230b57cec5SDimitry Andric// The following csr instructions actually alias instructions from the base ISA. 2240b57cec5SDimitry Andric// However, it only makes sense to support them when the F extension is enabled. 2250b57cec5SDimitry Andric// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". 2260b57cec5SDimitry Andricdef : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 2>; 2270b57cec5SDimitry Andricdef : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs)>; 2280b57cec5SDimitry Andricdef : InstAlias<"fscsr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 2>; 2290b57cec5SDimitry Andric 2308bcb0991SDimitry Andric// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them 2318bcb0991SDimitry Andric// zero weight. 2328bcb0991SDimitry Andricdef : InstAlias<"frsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 0>; 2338bcb0991SDimitry Andricdef : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs), 0>; 2348bcb0991SDimitry Andricdef : InstAlias<"fssr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 0>; 2358bcb0991SDimitry Andric 2360b57cec5SDimitry Andricdef : InstAlias<"frrm $rd", (CSRRS GPR:$rd, FRM.Encoding, X0), 2>; 2370b57cec5SDimitry Andricdef : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, FRM.Encoding, GPR:$rs)>; 2380b57cec5SDimitry Andricdef : InstAlias<"fsrm $rs", (CSRRW X0, FRM.Encoding, GPR:$rs), 2>; 2390b57cec5SDimitry Andricdef : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, FRM.Encoding, uimm5:$imm)>; 2400b57cec5SDimitry Andricdef : InstAlias<"fsrmi $imm", (CSRRWI X0, FRM.Encoding, uimm5:$imm), 2>; 2410b57cec5SDimitry Andric 2420b57cec5SDimitry Andricdef : InstAlias<"frflags $rd", (CSRRS GPR:$rd, FFLAGS.Encoding, X0), 2>; 2430b57cec5SDimitry Andricdef : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, FFLAGS.Encoding, GPR:$rs)>; 2440b57cec5SDimitry Andricdef : InstAlias<"fsflags $rs", (CSRRW X0, FFLAGS.Encoding, GPR:$rs), 2>; 2450b57cec5SDimitry Andricdef : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, FFLAGS.Encoding, uimm5:$imm)>; 2460b57cec5SDimitry Andricdef : InstAlias<"fsflagsi $imm", (CSRRWI X0, FFLAGS.Encoding, uimm5:$imm), 2>; 2470b57cec5SDimitry Andric 2480b57cec5SDimitry Andric// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both 2490b57cec5SDimitry Andric// spellings should be supported by standard tools. 2500b57cec5SDimitry Andricdef : MnemonicAlias<"fmv.s.x", "fmv.w.x">; 2510b57cec5SDimitry Andricdef : MnemonicAlias<"fmv.x.s", "fmv.x.w">; 2520b57cec5SDimitry Andric 2530b57cec5SDimitry Andricdef PseudoFLW : PseudoFloatLoad<"flw", FPR32>; 2540b57cec5SDimitry Andricdef PseudoFSW : PseudoStore<"fsw", FPR32>; 2550b57cec5SDimitry Andric} // Predicates = [HasStdExtF] 2560b57cec5SDimitry Andric 2570b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2580b57cec5SDimitry Andric// Pseudo-instructions and codegen patterns 2590b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2600b57cec5SDimitry Andric 2610b57cec5SDimitry Andric/// Generic pattern classes 2620b57cec5SDimitry Andricclass PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst> 2630b57cec5SDimitry Andric : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>; 2640b57cec5SDimitry Andric 2650b57cec5SDimitry Andricclass PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 2660b57cec5SDimitry Andric : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>; 2670b57cec5SDimitry Andric 2680b57cec5SDimitry Andriclet Predicates = [HasStdExtF] in { 2690b57cec5SDimitry Andric 2700b57cec5SDimitry Andric/// Float conversion operations 2710b57cec5SDimitry Andric 2720b57cec5SDimitry Andric// Moves (no conversion) 2730b57cec5SDimitry Andricdef : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>; 2740b57cec5SDimitry Andricdef : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>; 2750b57cec5SDimitry Andric 2760b57cec5SDimitry Andric// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 2770b57cec5SDimitry Andric// are defined later. 2780b57cec5SDimitry Andric 2790b57cec5SDimitry Andric/// Float arithmetic operations 2800b57cec5SDimitry Andric 2810b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fadd, FADD_S>; 2820b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fsub, FSUB_S>; 2830b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fmul, FMUL_S>; 2840b57cec5SDimitry Andricdef : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>; 2850b57cec5SDimitry Andric 2860b57cec5SDimitry Andricdef : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; 2870b57cec5SDimitry Andric 2880b57cec5SDimitry Andricdef : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; 2890b57cec5SDimitry Andricdef : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; 2900b57cec5SDimitry Andric 2910b57cec5SDimitry Andricdef : PatFpr32Fpr32<fcopysign, FSGNJ_S>; 2920b57cec5SDimitry Andricdef : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 2930b57cec5SDimitry Andric 2940b57cec5SDimitry Andric// fmadd: rs1 * rs2 + rs3 2950b57cec5SDimitry Andricdef : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3), 2960b57cec5SDimitry Andric (FMADD_S $rs1, $rs2, $rs3, 0b111)>; 2970b57cec5SDimitry Andric 2980b57cec5SDimitry Andric// fmsub: rs1 * rs2 - rs3 2990b57cec5SDimitry Andricdef : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), 3000b57cec5SDimitry Andric (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 3010b57cec5SDimitry Andric 3020b57cec5SDimitry Andric// fnmsub: -rs1 * rs2 + rs3 3030b57cec5SDimitry Andricdef : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), 3040b57cec5SDimitry Andric (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 3050b57cec5SDimitry Andric 3060b57cec5SDimitry Andric// fnmadd: -rs1 * rs2 - rs3 3070b57cec5SDimitry Andricdef : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), 3080b57cec5SDimitry Andric (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 3090b57cec5SDimitry Andric 3100b57cec5SDimitry Andric// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the 3110b57cec5SDimitry Andric// canonical NaN when given a signaling NaN. This doesn't match the LLVM 3120b57cec5SDimitry Andric// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the 3130b57cec5SDimitry Andric// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that 3140b57cec5SDimitry Andric// matches LLVM's fminnum and fmaxnum 3150b57cec5SDimitry Andric// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 3160b57cec5SDimitry Andricdef : PatFpr32Fpr32<fminnum, FMIN_S>; 3170b57cec5SDimitry Andricdef : PatFpr32Fpr32<fmaxnum, FMAX_S>; 3180b57cec5SDimitry Andric 3190b57cec5SDimitry Andric/// Setcc 3200b57cec5SDimitry Andric 3210b57cec5SDimitry Andricdef : PatFpr32Fpr32<seteq, FEQ_S>; 3220b57cec5SDimitry Andricdef : PatFpr32Fpr32<setoeq, FEQ_S>; 3230b57cec5SDimitry Andricdef : PatFpr32Fpr32<setlt, FLT_S>; 3240b57cec5SDimitry Andricdef : PatFpr32Fpr32<setolt, FLT_S>; 3250b57cec5SDimitry Andricdef : PatFpr32Fpr32<setle, FLE_S>; 3260b57cec5SDimitry Andricdef : PatFpr32Fpr32<setole, FLE_S>; 3270b57cec5SDimitry Andric 3280b57cec5SDimitry Andric// Define pattern expansions for setcc operations which aren't directly 3290b57cec5SDimitry Andric// handled by a RISC-V instruction and aren't expanded in the SelectionDAG 3300b57cec5SDimitry Andric// Legalizer. 3310b57cec5SDimitry Andric 3320b57cec5SDimitry Andricdef : Pat<(seto FPR32:$rs1, FPR32:$rs2), 3330b57cec5SDimitry Andric (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 3340b57cec5SDimitry Andric (FEQ_S FPR32:$rs2, FPR32:$rs2))>; 3350b57cec5SDimitry Andric 3360b57cec5SDimitry Andricdef : Pat<(setuo FPR32:$rs1, FPR32:$rs2), 3370b57cec5SDimitry Andric (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 3380b57cec5SDimitry Andric (FEQ_S FPR32:$rs2, FPR32:$rs2)), 3390b57cec5SDimitry Andric 1)>; 3400b57cec5SDimitry Andric 3410b57cec5SDimitry Andricdef Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>; 3420b57cec5SDimitry Andric 3430b57cec5SDimitry Andric/// Loads 3440b57cec5SDimitry Andric 3450b57cec5SDimitry Andricdefm : LdPat<load, FLW>; 3460b57cec5SDimitry Andric 3470b57cec5SDimitry Andric/// Stores 3480b57cec5SDimitry Andric 3490b57cec5SDimitry Andricdefm : StPat<store, FSW, FPR32>; 3500b57cec5SDimitry Andric 3510b57cec5SDimitry Andric} // Predicates = [HasStdExtF] 3520b57cec5SDimitry Andric 3530b57cec5SDimitry Andriclet Predicates = [HasStdExtF, IsRV32] in { 3540b57cec5SDimitry Andric// float->[u]int. Round-to-zero must be used. 3550b57cec5SDimitry Andricdef : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 3560b57cec5SDimitry Andricdef : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 3570b57cec5SDimitry Andric 3580b57cec5SDimitry Andric// [u]int->float. Match GCC and default to using dynamic rounding mode. 3590b57cec5SDimitry Andricdef : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>; 3600b57cec5SDimitry Andricdef : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; 3610b57cec5SDimitry Andric} // Predicates = [HasStdExtF, IsRV32] 3620b57cec5SDimitry Andric 3630b57cec5SDimitry Andriclet Predicates = [HasStdExtF, IsRV32] in { 3640b57cec5SDimitry Andric// FP->[u]int. Round-to-zero must be used 3650b57cec5SDimitry Andricdef : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 3660b57cec5SDimitry Andricdef : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 3670b57cec5SDimitry Andric 3680b57cec5SDimitry Andric// [u]int->fp. Match GCC and default to using dynamic rounding mode. 3690b57cec5SDimitry Andricdef : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>; 3700b57cec5SDimitry Andricdef : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; 3710b57cec5SDimitry Andric} // Predicates = [HasStdExtF, IsRV32] 3720b57cec5SDimitry Andric 3730b57cec5SDimitry Andriclet Predicates = [HasStdExtF, IsRV64] in { 3740b57cec5SDimitry Andricdef : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; 3750b57cec5SDimitry Andricdef : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; 3760b57cec5SDimitry Andricdef : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)), 3770b57cec5SDimitry Andric (FMV_X_W FPR32:$src)>; 3780b57cec5SDimitry Andric 3790b57cec5SDimitry Andric// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe 3800b57cec5SDimitry Andric// because fpto[u|s]i produces poison if the value can't fit into the target. 3810b57cec5SDimitry Andric// We match the single case below because fcvt.wu.s sign-extends its result so 3820b57cec5SDimitry Andric// is cheaper than fcvt.lu.s+sext.w. 3830b57cec5SDimitry Andricdef : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32), 3840b57cec5SDimitry Andric (FCVT_WU_S $rs1, 0b001)>; 3850b57cec5SDimitry Andric 3860b57cec5SDimitry Andric// FP->[u]int64 3870b57cec5SDimitry Andricdef : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>; 3880b57cec5SDimitry Andricdef : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>; 3890b57cec5SDimitry Andric 3900b57cec5SDimitry Andric// [u]int->fp. Match GCC and default to using dynamic rounding mode. 3910b57cec5SDimitry Andricdef : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>; 3920b57cec5SDimitry Andricdef : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; 3930b57cec5SDimitry Andricdef : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>; 3940b57cec5SDimitry Andricdef : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>; 3950b57cec5SDimitry Andric} // Predicates = [HasStdExtF, IsRV64] 396