1//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'F', 10// Single-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_W_X_RV64 19 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 20def SDT_RISCVFMV_X_ANYEXTW_RV64 21 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 22 23def riscv_fmv_w_x_rv64 24 : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>; 25def riscv_fmv_x_anyextw_rv64 26 : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>; 27 28//===----------------------------------------------------------------------===// 29// Operand and SDNode transformation definitions. 30//===----------------------------------------------------------------------===// 31 32// Floating-point rounding mode 33 34def FRMArg : AsmOperandClass { 35 let Name = "FRMArg"; 36 let RenderMethod = "addFRMArgOperands"; 37 let DiagnosticType = "InvalidFRMArg"; 38} 39 40def frmarg : Operand<XLenVT> { 41 let ParserMatchClass = FRMArg; 42 let PrintMethod = "printFRMArg"; 43 let DecoderMethod = "decodeFRMArg"; 44} 45 46//===----------------------------------------------------------------------===// 47// Instruction class templates 48//===----------------------------------------------------------------------===// 49 50let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 51class FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr> 52 : RVInstR4<0b00, opcode, (outs FPR32:$rd), 53 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3), 54 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 55 56class FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr> 57 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 58 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 59 60let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 61class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 62 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd), 63 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">, 64 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 65 66let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 67class FPALUS_rr_frm<bits<7> funct7, string opcodestr> 68 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd), 69 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr, 70 "$rd, $rs1, $rs2, $funct3">; 71 72class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr> 73 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 74 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>; 75 76let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 77class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty, 78 RegisterClass rs1ty, string opcodestr> 79 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), 80 opcodestr, "$rd, $rs1">; 81 82let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 83class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty, 84 string opcodestr> 85 : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd), 86 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr, 87 "$rd, $rs1, $funct3">; 88 89class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr, 90 RegisterClass rdty, RegisterClass rs1ty> 91 : InstAlias<OpcodeStr#" $rd, $rs1", 92 (Inst rdty:$rd, rs1ty:$rs1, 0b111)>; 93 94let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 95class FPCmpS_rr<bits<3> funct3, string opcodestr> 96 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd), 97 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">, 98 Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>; 99 100//===----------------------------------------------------------------------===// 101// Instructions 102//===----------------------------------------------------------------------===// 103 104let Predicates = [HasStdExtF] in { 105let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 106def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd), 107 (ins GPR:$rs1, simm12:$imm12), 108 "flw", "$rd, ${imm12}(${rs1})">, 109 Sched<[WriteFLD32, ReadMemBase]>; 110 111// Operands for stores are in the order srcreg, base, offset rather than 112// reflecting the order these fields are specified in the instruction 113// encoding. 114let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 115def FSW : RVInstS<0b010, OPC_STORE_FP, (outs), 116 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), 117 "fsw", "$rs2, ${imm12}(${rs1})">, 118 Sched<[WriteFST32, ReadStoreData, ReadMemBase]>; 119 120def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">, 121 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>; 122def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">; 123def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">, 124 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>; 125def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">; 126def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">, 127 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>; 128def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">; 129def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">, 130 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>; 131def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">; 132 133def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">, 134 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 135def : FPALUSDynFrmAlias<FADD_S, "fadd.s">; 136def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">, 137 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 138def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">; 139def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">, 140 Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>; 141def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 142def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">, 143 Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; 144def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">; 145 146def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">, 147 Sched<[WriteFSqrt32, ReadFSqrt32]> { 148 let rs2 = 0b00000; 149} 150def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>; 151 152def FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">; 153def FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">; 154def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">; 155def FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">; 156def FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">; 157 158def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">, 159 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 160 let rs2 = 0b00000; 161} 162def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>; 163 164def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">, 165 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 166 let rs2 = 0b00001; 167} 168def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>; 169 170def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">, 171 Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> { 172 let rs2 = 0b00000; 173} 174 175def FEQ_S : FPCmpS_rr<0b010, "feq.s">; 176def FLT_S : FPCmpS_rr<0b001, "flt.s">; 177def FLE_S : FPCmpS_rr<0b000, "fle.s">; 178 179def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">, 180 Sched<[WriteFClass32, ReadFClass32]> { 181 let rs2 = 0b00000; 182} 183 184def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">, 185 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 186 let rs2 = 0b00000; 187} 188def : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>; 189 190def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">, 191 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 192 let rs2 = 0b00001; 193} 194def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>; 195 196def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">, 197 Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> { 198 let rs2 = 0b00000; 199} 200} // Predicates = [HasStdExtF] 201 202let Predicates = [HasStdExtF, IsRV64] in { 203def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">, 204 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 205 let rs2 = 0b00010; 206} 207def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; 208 209def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">, 210 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 211 let rs2 = 0b00011; 212} 213def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>; 214 215def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">, 216 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 217 let rs2 = 0b00010; 218} 219def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>; 220 221def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">, 222 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 223 let rs2 = 0b00011; 224} 225def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>; 226} // Predicates = [HasStdExtF, IsRV64] 227 228//===----------------------------------------------------------------------===// 229// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 230//===----------------------------------------------------------------------===// 231 232let Predicates = [HasStdExtF] in { 233def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>; 234def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 235 236def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 237def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 238def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 239 240// fgt.s/fge.s are recognised by the GNU assembler but the canonical 241// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. 242def : InstAlias<"fgt.s $rd, $rs, $rt", 243 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 244def : InstAlias<"fge.s $rd, $rs, $rt", 245 (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 246 247// The following csr instructions actually alias instructions from the base ISA. 248// However, it only makes sense to support them when the F extension is enabled. 249// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". 250def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 2>; 251def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs)>; 252def : InstAlias<"fscsr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 2>; 253 254// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them 255// zero weight. 256def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 0>; 257def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs), 0>; 258def : InstAlias<"fssr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 0>; 259 260def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, FRM.Encoding, X0), 2>; 261def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, FRM.Encoding, GPR:$rs)>; 262def : InstAlias<"fsrm $rs", (CSRRW X0, FRM.Encoding, GPR:$rs), 2>; 263def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, FRM.Encoding, uimm5:$imm)>; 264def : InstAlias<"fsrmi $imm", (CSRRWI X0, FRM.Encoding, uimm5:$imm), 2>; 265 266def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, FFLAGS.Encoding, X0), 2>; 267def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, FFLAGS.Encoding, GPR:$rs)>; 268def : InstAlias<"fsflags $rs", (CSRRW X0, FFLAGS.Encoding, GPR:$rs), 2>; 269def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, FFLAGS.Encoding, uimm5:$imm)>; 270def : InstAlias<"fsflagsi $imm", (CSRRWI X0, FFLAGS.Encoding, uimm5:$imm), 2>; 271 272// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both 273// spellings should be supported by standard tools. 274def : MnemonicAlias<"fmv.s.x", "fmv.w.x">; 275def : MnemonicAlias<"fmv.x.s", "fmv.x.w">; 276 277def PseudoFLW : PseudoFloatLoad<"flw", FPR32>; 278def PseudoFSW : PseudoStore<"fsw", FPR32>; 279} // Predicates = [HasStdExtF] 280 281//===----------------------------------------------------------------------===// 282// Pseudo-instructions and codegen patterns 283//===----------------------------------------------------------------------===// 284 285/// Generic pattern classes 286class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst> 287 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>; 288 289class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 290 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>; 291 292let Predicates = [HasStdExtF] in { 293 294/// Float conversion operations 295 296// Moves (no conversion) 297def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>; 298def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>; 299 300// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 301// are defined later. 302 303/// Float arithmetic operations 304 305def : PatFpr32Fpr32DynFrm<fadd, FADD_S>; 306def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>; 307def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>; 308def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>; 309 310def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; 311 312def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; 313def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; 314 315def : PatFpr32Fpr32<fcopysign, FSGNJ_S>; 316def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 317 318// fmadd: rs1 * rs2 + rs3 319def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3), 320 (FMADD_S $rs1, $rs2, $rs3, 0b111)>; 321 322// fmsub: rs1 * rs2 - rs3 323def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), 324 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 325 326// fnmsub: -rs1 * rs2 + rs3 327def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), 328 (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 329 330// fnmadd: -rs1 * rs2 - rs3 331def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), 332 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 333 334// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the 335// canonical NaN when given a signaling NaN. This doesn't match the LLVM 336// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the 337// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that 338// matches LLVM's fminnum and fmaxnum 339// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 340def : PatFpr32Fpr32<fminnum, FMIN_S>; 341def : PatFpr32Fpr32<fmaxnum, FMAX_S>; 342 343/// Setcc 344 345def : PatFpr32Fpr32<seteq, FEQ_S>; 346def : PatFpr32Fpr32<setoeq, FEQ_S>; 347def : PatFpr32Fpr32<setlt, FLT_S>; 348def : PatFpr32Fpr32<setolt, FLT_S>; 349def : PatFpr32Fpr32<setle, FLE_S>; 350def : PatFpr32Fpr32<setole, FLE_S>; 351 352// Define pattern expansions for setcc operations which aren't directly 353// handled by a RISC-V instruction and aren't expanded in the SelectionDAG 354// Legalizer. 355 356def : Pat<(seto FPR32:$rs1, FPR32:$rs2), 357 (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 358 (FEQ_S FPR32:$rs2, FPR32:$rs2))>; 359 360def : Pat<(setuo FPR32:$rs1, FPR32:$rs2), 361 (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 362 (FEQ_S FPR32:$rs2, FPR32:$rs2)), 363 1)>; 364 365def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>; 366 367/// Loads 368 369defm : LdPat<load, FLW>; 370 371/// Stores 372 373defm : StPat<store, FSW, FPR32>; 374 375} // Predicates = [HasStdExtF] 376 377let Predicates = [HasStdExtF, IsRV32] in { 378// float->[u]int. Round-to-zero must be used. 379def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 380def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 381 382// [u]int->float. Match GCC and default to using dynamic rounding mode. 383def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>; 384def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; 385} // Predicates = [HasStdExtF, IsRV32] 386 387let Predicates = [HasStdExtF, IsRV32] in { 388// FP->[u]int. Round-to-zero must be used 389def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 390def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 391 392// [u]int->fp. Match GCC and default to using dynamic rounding mode. 393def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>; 394def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; 395} // Predicates = [HasStdExtF, IsRV32] 396 397let Predicates = [HasStdExtF, IsRV64] in { 398def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; 399def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; 400def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)), 401 (FMV_X_W FPR32:$src)>; 402 403// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe 404// because fpto[u|s]i produces poison if the value can't fit into the target. 405// We match the single case below because fcvt.wu.s sign-extends its result so 406// is cheaper than fcvt.lu.s+sext.w. 407def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32), 408 (FCVT_WU_S $rs1, 0b001)>; 409 410// FP->[u]int64 411def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>; 412def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>; 413 414// [u]int->fp. Match GCC and default to using dynamic rounding mode. 415def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>; 416def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; 417def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>; 418def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>; 419} // Predicates = [HasStdExtF, IsRV64] 420