15ffd83dbSDimitry Andric//===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===// 25ffd83dbSDimitry Andric// 35ffd83dbSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 45ffd83dbSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 55ffd83dbSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65ffd83dbSDimitry Andric// 75ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 85ffd83dbSDimitry Andric/// 95ffd83dbSDimitry Andric/// This file describes the RISC-V instructions from the standard 'V' Vector 10d409305fSDimitry Andric/// extension, version 0.10. 115ffd83dbSDimitry Andric/// This version is still experimental as the 'V' extension hasn't been 125ffd83dbSDimitry Andric/// ratified yet. 135ffd83dbSDimitry Andric/// 145ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 155ffd83dbSDimitry Andric 165ffd83dbSDimitry Andricinclude "RISCVInstrFormatsV.td" 175ffd83dbSDimitry Andric 185ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 195ffd83dbSDimitry Andric// Operand and SDNode transformation definitions. 205ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 215ffd83dbSDimitry Andric 225ffd83dbSDimitry Andricdef VTypeIAsmOperand : AsmOperandClass { 235ffd83dbSDimitry Andric let Name = "VTypeI"; 245ffd83dbSDimitry Andric let ParserMethod = "parseVTypeI"; 255ffd83dbSDimitry Andric let DiagnosticType = "InvalidVTypeI"; 265ffd83dbSDimitry Andric} 275ffd83dbSDimitry Andric 285ffd83dbSDimitry Andricdef VTypeIOp : Operand<XLenVT> { 295ffd83dbSDimitry Andric let ParserMatchClass = VTypeIAsmOperand; 305ffd83dbSDimitry Andric let PrintMethod = "printVTypeI"; 315ffd83dbSDimitry Andric let DecoderMethod = "decodeUImmOperand<11>"; 325ffd83dbSDimitry Andric} 335ffd83dbSDimitry Andric 345ffd83dbSDimitry Andricdef VMaskAsmOperand : AsmOperandClass { 355ffd83dbSDimitry Andric let Name = "RVVMaskRegOpOperand"; 365ffd83dbSDimitry Andric let RenderMethod = "addRegOperands"; 375ffd83dbSDimitry Andric let PredicateMethod = "isV0Reg"; 385ffd83dbSDimitry Andric let ParserMethod = "parseMaskReg"; 395ffd83dbSDimitry Andric let IsOptional = 1; 405ffd83dbSDimitry Andric let DefaultMethod = "defaultMaskRegOp"; 415ffd83dbSDimitry Andric let DiagnosticType = "InvalidVMaskRegister"; 425ffd83dbSDimitry Andric} 435ffd83dbSDimitry Andric 445ffd83dbSDimitry Andricdef VMaskOp : RegisterOperand<VMV0> { 455ffd83dbSDimitry Andric let ParserMatchClass = VMaskAsmOperand; 465ffd83dbSDimitry Andric let PrintMethod = "printVMaskReg"; 475ffd83dbSDimitry Andric let EncoderMethod = "getVMaskReg"; 485ffd83dbSDimitry Andric let DecoderMethod = "decodeVMaskReg"; 495ffd83dbSDimitry Andric} 505ffd83dbSDimitry Andric 515ffd83dbSDimitry Andricdef simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> { 525ffd83dbSDimitry Andric let ParserMatchClass = SImmAsmOperand<5>; 535ffd83dbSDimitry Andric let EncoderMethod = "getImmOpValue"; 545ffd83dbSDimitry Andric let DecoderMethod = "decodeSImmOperand<5>"; 555ffd83dbSDimitry Andric let MCOperandPredicate = [{ 565ffd83dbSDimitry Andric int64_t Imm; 575ffd83dbSDimitry Andric if (MCOp.evaluateAsConstantImm(Imm)) 585ffd83dbSDimitry Andric return isInt<5>(Imm); 595ffd83dbSDimitry Andric return MCOp.isBareSymbolRef(); 605ffd83dbSDimitry Andric }]; 615ffd83dbSDimitry Andric} 625ffd83dbSDimitry Andric 635ffd83dbSDimitry Andricdef SImm5Plus1AsmOperand : AsmOperandClass { 645ffd83dbSDimitry Andric let Name = "SImm5Plus1"; 65e8d8bef9SDimitry Andric let RenderMethod = "addImmOperands"; 665ffd83dbSDimitry Andric let DiagnosticType = "InvalidSImm5Plus1"; 675ffd83dbSDimitry Andric} 685ffd83dbSDimitry Andric 695ffd83dbSDimitry Andricdef simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT, 70fe6060f1SDimitry Andric [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> { 715ffd83dbSDimitry Andric let ParserMatchClass = SImm5Plus1AsmOperand; 725ffd83dbSDimitry Andric let MCOperandPredicate = [{ 735ffd83dbSDimitry Andric int64_t Imm; 745ffd83dbSDimitry Andric if (MCOp.evaluateAsConstantImm(Imm)) 75fe6060f1SDimitry Andric return (isInt<5>(Imm) && Imm != -16) || Imm == 16; 765ffd83dbSDimitry Andric return MCOp.isBareSymbolRef(); 775ffd83dbSDimitry Andric }]; 785ffd83dbSDimitry Andric} 795ffd83dbSDimitry Andric 805ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 81*6e75b2fbSDimitry Andric// Scheduling definitions. 82*6e75b2fbSDimitry Andric//===----------------------------------------------------------------------===// 83*6e75b2fbSDimitry Andric 84*6e75b2fbSDimitry Andricclass VMVRSched<int n>: Sched <[!cast<SchedReadWrite>("WriteVMov" # n # "V"), 85*6e75b2fbSDimitry Andric !cast<SchedReadWrite>("ReadVMov" # n # "V")]>; 86*6e75b2fbSDimitry Andric 87*6e75b2fbSDimitry Andricclass VLESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDE" # n), 88*6e75b2fbSDimitry Andric ReadVLDX, ReadVMask]>; 89*6e75b2fbSDimitry Andric 90*6e75b2fbSDimitry Andricclass VSESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVSTE" # n), 91*6e75b2fbSDimitry Andric !cast<SchedReadWrite>("ReadVSTE" # n # "V"), 92*6e75b2fbSDimitry Andric ReadVSTX, ReadVMask]>; 93*6e75b2fbSDimitry Andric 94*6e75b2fbSDimitry Andricclass VLSSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDS" # n), 95*6e75b2fbSDimitry Andric ReadVLDX, ReadVLDSX, ReadVMask]>; 96*6e75b2fbSDimitry Andric 97*6e75b2fbSDimitry Andricclass VSSSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVSTS" # n), 98*6e75b2fbSDimitry Andric !cast<SchedReadWrite>("ReadVSTS" # n # "V"), 99*6e75b2fbSDimitry Andric ReadVSTX, ReadVSTSX, ReadVMask]>; 100*6e75b2fbSDimitry Andric 101*6e75b2fbSDimitry Andricclass VLXSched<int n, string o> : 102*6e75b2fbSDimitry Andric Sched <[!cast<SchedReadWrite>("WriteVLD" # o # "X" # n), 103*6e75b2fbSDimitry Andric ReadVLDX, !cast<SchedReadWrite>("ReadVLD" # o # "XV"), ReadVMask]>; 104*6e75b2fbSDimitry Andric 105*6e75b2fbSDimitry Andricclass VSXSched<int n, string o> : 106*6e75b2fbSDimitry Andric Sched <[!cast<SchedReadWrite>("WriteVST" # o # "X" # n), 107*6e75b2fbSDimitry Andric !cast<SchedReadWrite>("ReadVST" # o # "X" # n), 108*6e75b2fbSDimitry Andric ReadVSTX, !cast<SchedReadWrite>("ReadVST" # o # "XV"), ReadVMask]>; 109*6e75b2fbSDimitry Andric 110*6e75b2fbSDimitry Andricclass VLFSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDFF" # n), 111*6e75b2fbSDimitry Andric ReadVLDX, ReadVMask]>; 112*6e75b2fbSDimitry Andric 113*6e75b2fbSDimitry Andric//===----------------------------------------------------------------------===// 1145ffd83dbSDimitry Andric// Instruction class templates 1155ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 1165ffd83dbSDimitry Andric 1175ffd83dbSDimitry Andriclet hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { 118d409305fSDimitry Andric// load vd, (rs1) 119d409305fSDimitry Andricclass VUnitStrideLoadMask<string opcodestr> 120d409305fSDimitry Andric : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0}, 121d409305fSDimitry Andric (outs VR:$vd), 122fe6060f1SDimitry Andric (ins GPR:$rs1), opcodestr, "$vd, (${rs1})"> { 123fe6060f1SDimitry Andric let vm = 1; 124fe6060f1SDimitry Andric let RVVConstraint = NoConstraint; 125fe6060f1SDimitry Andric} 126d409305fSDimitry Andric 1275ffd83dbSDimitry Andric// load vd, (rs1), vm 128e8d8bef9SDimitry Andricclass VUnitStrideLoad<RISCVLSUMOP lumop, RISCVWidth width, 1295ffd83dbSDimitry Andric string opcodestr> 130e8d8bef9SDimitry Andric : RVInstVLU<0b000, width.Value{3}, lumop, width.Value{2-0}, 131e8d8bef9SDimitry Andric (outs VR:$vd), 1325ffd83dbSDimitry Andric (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; 1335ffd83dbSDimitry Andric 1345ffd83dbSDimitry Andric// load vd, (rs1), rs2, vm 135e8d8bef9SDimitry Andricclass VStridedLoad<RISCVWidth width, string opcodestr> 136e8d8bef9SDimitry Andric : RVInstVLS<0b000, width.Value{3}, width.Value{2-0}, 137e8d8bef9SDimitry Andric (outs VR:$vd), 1385ffd83dbSDimitry Andric (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, 1395ffd83dbSDimitry Andric "$vd, (${rs1}), $rs2$vm">; 1405ffd83dbSDimitry Andric 1415ffd83dbSDimitry Andric// load vd, (rs1), vs2, vm 1425ffd83dbSDimitry Andricclass VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr> 143e8d8bef9SDimitry Andric : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0}, 144e8d8bef9SDimitry Andric (outs VR:$vd), 145e8d8bef9SDimitry Andric (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, 1465ffd83dbSDimitry Andric "$vd, (${rs1}), $vs2$vm">; 1475ffd83dbSDimitry Andric 1485ffd83dbSDimitry Andric// vl<nf>r.v vd, (rs1) 149fe6060f1SDimitry Andricclass VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC> 150e8d8bef9SDimitry Andric : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg, 151fe6060f1SDimitry Andric width.Value{2-0}, (outs VRC:$vd), (ins GPR:$rs1), 1525ffd83dbSDimitry Andric opcodestr, "$vd, (${rs1})"> { 1535ffd83dbSDimitry Andric let vm = 1; 1545ffd83dbSDimitry Andric let Uses = []; 155e8d8bef9SDimitry Andric let RVVConstraint = NoConstraint; 1565ffd83dbSDimitry Andric} 157e8d8bef9SDimitry Andric 158e8d8bef9SDimitry Andric// segment load vd, (rs1), vm 159e8d8bef9SDimitry Andricclass VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop, 160e8d8bef9SDimitry Andric RISCVWidth width, string opcodestr> 161e8d8bef9SDimitry Andric : RVInstVLU<nf, width.Value{3}, lumop, width.Value{2-0}, 162e8d8bef9SDimitry Andric (outs VR:$vd), 163e8d8bef9SDimitry Andric (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; 164e8d8bef9SDimitry Andric 165e8d8bef9SDimitry Andric// segment load vd, (rs1), rs2, vm 166e8d8bef9SDimitry Andricclass VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr> 167e8d8bef9SDimitry Andric : RVInstVLS<nf, width.Value{3}, width.Value{2-0}, 168e8d8bef9SDimitry Andric (outs VR:$vd), 169e8d8bef9SDimitry Andric (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, 170e8d8bef9SDimitry Andric "$vd, (${rs1}), $rs2$vm">; 171e8d8bef9SDimitry Andric 172e8d8bef9SDimitry Andric// segment load vd, (rs1), vs2, vm 173e8d8bef9SDimitry Andricclass VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width, 174e8d8bef9SDimitry Andric string opcodestr> 175e8d8bef9SDimitry Andric : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0}, 176e8d8bef9SDimitry Andric (outs VR:$vd), 177e8d8bef9SDimitry Andric (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, 178e8d8bef9SDimitry Andric "$vd, (${rs1}), $vs2$vm">; 1795ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 1, mayStore = 0 1805ffd83dbSDimitry Andric 1815ffd83dbSDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { 182fe6060f1SDimitry Andric// store vd, vs3, (rs1) 183d409305fSDimitry Andricclass VUnitStrideStoreMask<string opcodestr> 184d409305fSDimitry Andric : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0}, 185d409305fSDimitry Andric (outs), (ins VR:$vs3, GPR:$rs1), opcodestr, 186fe6060f1SDimitry Andric "$vs3, (${rs1})"> { 187fe6060f1SDimitry Andric let vm = 1; 188fe6060f1SDimitry Andric} 189d409305fSDimitry Andric 190d409305fSDimitry Andric// store vd, vs3, (rs1), vm 191e8d8bef9SDimitry Andricclass VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width, 1925ffd83dbSDimitry Andric string opcodestr> 193e8d8bef9SDimitry Andric : RVInstVSU<0b000, width.Value{3}, sumop, width.Value{2-0}, 194e8d8bef9SDimitry Andric (outs), (ins VR:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr, 1955ffd83dbSDimitry Andric "$vs3, (${rs1})$vm">; 1965ffd83dbSDimitry Andric 1975ffd83dbSDimitry Andric// store vd, vs3, (rs1), rs2, vm 198e8d8bef9SDimitry Andricclass VStridedStore<RISCVWidth width, string opcodestr> 199e8d8bef9SDimitry Andric : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs), 200e8d8bef9SDimitry Andric (ins VR:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm), 2015ffd83dbSDimitry Andric opcodestr, "$vs3, (${rs1}), $rs2$vm">; 2025ffd83dbSDimitry Andric 2035ffd83dbSDimitry Andric// store vd, vs3, (rs1), vs2, vm 2045ffd83dbSDimitry Andricclass VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr> 205e8d8bef9SDimitry Andric : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs), 206e8d8bef9SDimitry Andric (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm), 2075ffd83dbSDimitry Andric opcodestr, "$vs3, (${rs1}), $vs2$vm">; 2085ffd83dbSDimitry Andric 2095ffd83dbSDimitry Andric// vs<nf>r.v vd, (rs1) 210fe6060f1SDimitry Andricclass VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC> 211e8d8bef9SDimitry Andric : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg, 212fe6060f1SDimitry Andric 0b000, (outs), (ins VRC:$vs3, GPR:$rs1), 2135ffd83dbSDimitry Andric opcodestr, "$vs3, (${rs1})"> { 2145ffd83dbSDimitry Andric let vm = 1; 2155ffd83dbSDimitry Andric let Uses = []; 2165ffd83dbSDimitry Andric} 217e8d8bef9SDimitry Andric 218e8d8bef9SDimitry Andric// segment store vd, vs3, (rs1), vm 219e8d8bef9SDimitry Andricclass VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> 220e8d8bef9SDimitry Andric : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, 221e8d8bef9SDimitry Andric (outs), (ins VR:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr, 222e8d8bef9SDimitry Andric "$vs3, (${rs1})$vm">; 223e8d8bef9SDimitry Andric 224e8d8bef9SDimitry Andric// segment store vd, vs3, (rs1), rs2, vm 225e8d8bef9SDimitry Andricclass VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> 226e8d8bef9SDimitry Andric : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs), 227e8d8bef9SDimitry Andric (ins VR:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm), 228e8d8bef9SDimitry Andric opcodestr, "$vs3, (${rs1}), $rs2$vm">; 229e8d8bef9SDimitry Andric 230e8d8bef9SDimitry Andric// segment store vd, vs3, (rs1), vs2, vm 231e8d8bef9SDimitry Andricclass VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width, 232e8d8bef9SDimitry Andric string opcodestr> 233e8d8bef9SDimitry Andric : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs), 234e8d8bef9SDimitry Andric (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm), 235e8d8bef9SDimitry Andric opcodestr, "$vs3, (${rs1}), $vs2$vm">; 2365ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 1 2375ffd83dbSDimitry Andric 2385ffd83dbSDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 2395ffd83dbSDimitry Andric// op vd, vs2, vs1, vm 2405ffd83dbSDimitry Andricclass VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 241e8d8bef9SDimitry Andric : RVInstVV<funct6, opv, (outs VR:$vd), 242e8d8bef9SDimitry Andric (ins VR:$vs2, VR:$vs1, VMaskOp:$vm), 2435ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $vs1$vm">; 2445ffd83dbSDimitry Andric 2455ffd83dbSDimitry Andric// op vd, vs2, vs1, v0 (without mask, use v0 as carry input) 2465ffd83dbSDimitry Andricclass VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 247e8d8bef9SDimitry Andric : RVInstVV<funct6, opv, (outs VR:$vd), 248e8d8bef9SDimitry Andric (ins VR:$vs2, VR:$vs1, VMV0:$v0), 2495ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $vs1, v0"> { 2505ffd83dbSDimitry Andric let vm = 0; 2515ffd83dbSDimitry Andric} 2525ffd83dbSDimitry Andric 2535ffd83dbSDimitry Andric// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2) 2545ffd83dbSDimitry Andricclass VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 255e8d8bef9SDimitry Andric : RVInstVV<funct6, opv, (outs VR:$vd), 256e8d8bef9SDimitry Andric (ins VR:$vs1, VR:$vs2, VMaskOp:$vm), 2575ffd83dbSDimitry Andric opcodestr, "$vd, $vs1, $vs2$vm">; 2585ffd83dbSDimitry Andric 259e8d8bef9SDimitry Andric// op vd, vs2, vs1 2605ffd83dbSDimitry Andricclass VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr> 261e8d8bef9SDimitry Andric : RVInstVV<funct6, opv, (outs VR:$vd), 262e8d8bef9SDimitry Andric (ins VR:$vs2, VR:$vs1), 2635ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $vs1"> { 2645ffd83dbSDimitry Andric let vm = 1; 2655ffd83dbSDimitry Andric} 2665ffd83dbSDimitry Andric 2675ffd83dbSDimitry Andric// op vd, vs2, rs1, vm 2685ffd83dbSDimitry Andricclass VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 269e8d8bef9SDimitry Andric : RVInstVX<funct6, opv, (outs VR:$vd), 270e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 2715ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $rs1$vm">; 2725ffd83dbSDimitry Andric 2735ffd83dbSDimitry Andric// op vd, vs2, rs1, v0 (without mask, use v0 as carry input) 2745ffd83dbSDimitry Andricclass VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 275e8d8bef9SDimitry Andric : RVInstVX<funct6, opv, (outs VR:$vd), 276e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1, VMV0:$v0), 2775ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $rs1, v0"> { 2785ffd83dbSDimitry Andric let vm = 0; 2795ffd83dbSDimitry Andric} 2805ffd83dbSDimitry Andric 2815ffd83dbSDimitry Andric// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2) 2825ffd83dbSDimitry Andricclass VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 283e8d8bef9SDimitry Andric : RVInstVX<funct6, opv, (outs VR:$vd), 284e8d8bef9SDimitry Andric (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), 2855ffd83dbSDimitry Andric opcodestr, "$vd, $rs1, $vs2$vm">; 2865ffd83dbSDimitry Andric 2875ffd83dbSDimitry Andric// op vd, vs1, vs2 2885ffd83dbSDimitry Andricclass VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr> 289e8d8bef9SDimitry Andric : RVInstVX<funct6, opv, (outs VR:$vd), 290e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1), 2915ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $rs1"> { 2925ffd83dbSDimitry Andric let vm = 1; 2935ffd83dbSDimitry Andric} 2945ffd83dbSDimitry Andric 2955ffd83dbSDimitry Andric// op vd, vs2, imm, vm 2965ffd83dbSDimitry Andricclass VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5> 297e8d8bef9SDimitry Andric : RVInstIVI<funct6, (outs VR:$vd), 298e8d8bef9SDimitry Andric (ins VR:$vs2, optype:$imm, VMaskOp:$vm), 2995ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $imm$vm">; 3005ffd83dbSDimitry Andric 3015ffd83dbSDimitry Andric// op vd, vs2, imm, v0 (without mask, use v0 as carry input) 3025ffd83dbSDimitry Andricclass VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5> 303e8d8bef9SDimitry Andric : RVInstIVI<funct6, (outs VR:$vd), 304e8d8bef9SDimitry Andric (ins VR:$vs2, optype:$imm, VMV0:$v0), 3055ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $imm, v0"> { 3065ffd83dbSDimitry Andric let vm = 0; 3075ffd83dbSDimitry Andric} 3085ffd83dbSDimitry Andric 3095ffd83dbSDimitry Andric// op vd, vs2, imm, vm 3105ffd83dbSDimitry Andricclass VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5> 311e8d8bef9SDimitry Andric : RVInstIVI<funct6, (outs VR:$vd), 312e8d8bef9SDimitry Andric (ins VR:$vs2, optype:$imm), 3135ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $imm"> { 3145ffd83dbSDimitry Andric let vm = 1; 3155ffd83dbSDimitry Andric} 3165ffd83dbSDimitry Andric 3175ffd83dbSDimitry Andric// op vd, vs2, rs1, vm (Float) 3185ffd83dbSDimitry Andricclass VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr> 319e8d8bef9SDimitry Andric : RVInstVX<funct6, opv, (outs VR:$vd), 320e8d8bef9SDimitry Andric (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm), 3215ffd83dbSDimitry Andric opcodestr, "$vd, $vs2, $rs1$vm">; 3225ffd83dbSDimitry Andric 3235ffd83dbSDimitry Andric// op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2) 3245ffd83dbSDimitry Andricclass VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr> 325e8d8bef9SDimitry Andric : RVInstVX<funct6, opv, (outs VR:$vd), 326e8d8bef9SDimitry Andric (ins FPR32:$rs1, VR:$vs2, VMaskOp:$vm), 3275ffd83dbSDimitry Andric opcodestr, "$vd, $rs1, $vs2$vm">; 3285ffd83dbSDimitry Andric 3295ffd83dbSDimitry Andric// op vd, vs2, vm (use vs1 as instruction encoding) 3305ffd83dbSDimitry Andricclass VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> 331e8d8bef9SDimitry Andric : RVInstV<funct6, vs1, opv, (outs VR:$vd), 332e8d8bef9SDimitry Andric (ins VR:$vs2, VMaskOp:$vm), 3335ffd83dbSDimitry Andric opcodestr, "$vd, $vs2$vm">; 3345ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 3355ffd83dbSDimitry Andric 336e8d8bef9SDimitry Andriclet hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 337e8d8bef9SDimitry Andric// vamo vd, (rs1), vs2, vd, vm 338e8d8bef9SDimitry Andricclass VAMOWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> 339e8d8bef9SDimitry Andric : RVInstVAMO<amoop, width.Value{2-0}, (outs VR:$vd_wd), 340e8d8bef9SDimitry Andric (ins GPR:$rs1, VR:$vs2, VR:$vd, VMaskOp:$vm), 341e8d8bef9SDimitry Andric opcodestr, "$vd_wd, (${rs1}), $vs2, $vd$vm"> { 342e8d8bef9SDimitry Andric let Constraints = "$vd_wd = $vd"; 343e8d8bef9SDimitry Andric let wd = 1; 344e8d8bef9SDimitry Andric bits<5> vd; 345e8d8bef9SDimitry Andric let Inst{11-7} = vd; 346e8d8bef9SDimitry Andric} 347e8d8bef9SDimitry Andric 348e8d8bef9SDimitry Andric// vamo x0, (rs1), vs2, vs3, vm 349e8d8bef9SDimitry Andricclass VAMONoWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> 350e8d8bef9SDimitry Andric : RVInstVAMO<amoop, width.Value{2-0}, (outs), 351e8d8bef9SDimitry Andric (ins GPR:$rs1, VR:$vs2, VR:$vs3, VMaskOp:$vm), 352e8d8bef9SDimitry Andric opcodestr, "x0, (${rs1}), $vs2, $vs3$vm"> { 353e8d8bef9SDimitry Andric bits<5> vs3; 354e8d8bef9SDimitry Andric let Inst{11-7} = vs3; 355e8d8bef9SDimitry Andric} 356e8d8bef9SDimitry Andric 357e8d8bef9SDimitry Andric} // hasSideEffects = 0, mayLoad = 1, mayStore = 1 358e8d8bef9SDimitry Andric 3595ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 3605ffd83dbSDimitry Andric// Combination of instruction classes. 3615ffd83dbSDimitry Andric// Use these multiclasses to define instructions more easily. 3625ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 3635ffd83dbSDimitry Andricmulticlass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 364*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 365*6e75b2fbSDimitry Andric Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>; 366*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 367*6e75b2fbSDimitry Andric Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>; 368*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 369*6e75b2fbSDimitry Andric Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>; 3705ffd83dbSDimitry Andric} 3715ffd83dbSDimitry Andric 3725ffd83dbSDimitry Andricmulticlass VALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 373*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 374*6e75b2fbSDimitry Andric Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>; 375*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 376*6e75b2fbSDimitry Andric Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>; 3775ffd83dbSDimitry Andric} 3785ffd83dbSDimitry Andric 3795ffd83dbSDimitry Andricmulticlass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 380*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 381*6e75b2fbSDimitry Andric Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUX, ReadVMask]>; 382*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 383*6e75b2fbSDimitry Andric Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>; 3845ffd83dbSDimitry Andric} 3855ffd83dbSDimitry Andric 3865ffd83dbSDimitry Andricmulticlass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 387*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 388*6e75b2fbSDimitry Andric Sched<[WriteVIWALUV, ReadVIWALUV, ReadVIWALUV, ReadVMask]>; 389*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 390*6e75b2fbSDimitry Andric Sched<[WriteVIWALUX, ReadVIWALUV, ReadVIWALUX, ReadVMask]>; 3915ffd83dbSDimitry Andric} 3925ffd83dbSDimitry Andric 393*6e75b2fbSDimitry Andricmulticlass VMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 394*6e75b2fbSDimitry Andric def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 395*6e75b2fbSDimitry Andric Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>; 396*6e75b2fbSDimitry Andric def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 397*6e75b2fbSDimitry Andric Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>; 3985ffd83dbSDimitry Andric} 3995ffd83dbSDimitry Andric 400*6e75b2fbSDimitry Andricmulticlass VWMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 401*6e75b2fbSDimitry Andric def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 402*6e75b2fbSDimitry Andric Sched<[WriteVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVMask]>; 403*6e75b2fbSDimitry Andric def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 404*6e75b2fbSDimitry Andric Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>; 4055ffd83dbSDimitry Andric} 4065ffd83dbSDimitry Andric 407*6e75b2fbSDimitry Andricmulticlass VWMAC_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> { 408*6e75b2fbSDimitry Andric def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 409*6e75b2fbSDimitry Andric Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>; 4105ffd83dbSDimitry Andric} 4115ffd83dbSDimitry Andric 4125ffd83dbSDimitry Andricmulticlass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 413*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 414*6e75b2fbSDimitry Andric Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; 4155ffd83dbSDimitry Andric} 4165ffd83dbSDimitry Andric 4175ffd83dbSDimitry Andricmulticlass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> { 418*6e75b2fbSDimitry Andric def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 419*6e75b2fbSDimitry Andric Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>; 420*6e75b2fbSDimitry Andric def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 421*6e75b2fbSDimitry Andric Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>; 422*6e75b2fbSDimitry Andric def IM : VALUmVI<funct6, opcodestr # ".vim">, 423*6e75b2fbSDimitry Andric Sched<[WriteVICALUI, ReadVIALUCV, ReadVMask]>; 424*6e75b2fbSDimitry Andric} 425*6e75b2fbSDimitry Andric 426*6e75b2fbSDimitry Andricmulticlass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> { 427*6e75b2fbSDimitry Andric def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 428*6e75b2fbSDimitry Andric Sched<[WriteVIMergeV, ReadVIMergeV, ReadVIMergeV, ReadVMask]>; 429*6e75b2fbSDimitry Andric def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 430*6e75b2fbSDimitry Andric Sched<[WriteVIMergeX, ReadVIMergeV, ReadVIMergeX, ReadVMask]>; 431*6e75b2fbSDimitry Andric def IM : VALUmVI<funct6, opcodestr # ".vim">, 432*6e75b2fbSDimitry Andric Sched<[WriteVIMergeI, ReadVIMergeV, ReadVMask]>; 4335ffd83dbSDimitry Andric} 4345ffd83dbSDimitry Andric 4355ffd83dbSDimitry Andricmulticlass VALUm_IV_V_X<string opcodestr, bits<6> funct6> { 436*6e75b2fbSDimitry Andric def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 437*6e75b2fbSDimitry Andric Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>; 438*6e75b2fbSDimitry Andric def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 439*6e75b2fbSDimitry Andric Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>; 4405ffd83dbSDimitry Andric} 4415ffd83dbSDimitry Andric 4425ffd83dbSDimitry Andricmulticlass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> { 443*6e75b2fbSDimitry Andric def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">, 444*6e75b2fbSDimitry Andric Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>; 445*6e75b2fbSDimitry Andric def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">, 446*6e75b2fbSDimitry Andric Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>; 447*6e75b2fbSDimitry Andric def I : VALUVINoVm<funct6, opcodestr # ".vi", optype>, 448*6e75b2fbSDimitry Andric Sched<[WriteVICALUI, ReadVIALUCV]>; 4495ffd83dbSDimitry Andric} 4505ffd83dbSDimitry Andric 4515ffd83dbSDimitry Andricmulticlass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> { 452*6e75b2fbSDimitry Andric def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">, 453*6e75b2fbSDimitry Andric Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>; 454*6e75b2fbSDimitry Andric def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">, 455*6e75b2fbSDimitry Andric Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>; 4565ffd83dbSDimitry Andric} 4575ffd83dbSDimitry Andric 4585ffd83dbSDimitry Andricmulticlass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 459*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 460*6e75b2fbSDimitry Andric Sched<[WriteVFALUV, ReadVFALUV, ReadVFALUV, ReadVMask]>; 461*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 462*6e75b2fbSDimitry Andric Sched<[WriteVFALUF, ReadVFALUV, ReadVFALUF, ReadVMask]>; 4635ffd83dbSDimitry Andric} 4645ffd83dbSDimitry Andric 4655ffd83dbSDimitry Andricmulticlass VALU_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 466*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 467*6e75b2fbSDimitry Andric Sched<[WriteVFALUF, ReadVFALUV, ReadVFALUF, ReadVMask]>; 4685ffd83dbSDimitry Andric} 4695ffd83dbSDimitry Andric 470*6e75b2fbSDimitry Andricmulticlass VWALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 471*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 472*6e75b2fbSDimitry Andric Sched<[WriteVFWALUV, ReadVFWALUV, ReadVFWALUV, ReadVMask]>; 473*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 474*6e75b2fbSDimitry Andric Sched<[WriteVFWALUF, ReadVFWALUV, ReadVFWALUF, ReadVMask]>; 4755ffd83dbSDimitry Andric} 4765ffd83dbSDimitry Andric 477*6e75b2fbSDimitry Andricmulticlass VMUL_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 478*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 479*6e75b2fbSDimitry Andric Sched<[WriteVFMulV, ReadVFMulV, ReadVFMulV, ReadVMask]>; 480*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 481*6e75b2fbSDimitry Andric Sched<[WriteVFMulF, ReadVFMulV, ReadVFMulF, ReadVMask]>; 4825ffd83dbSDimitry Andric} 4835ffd83dbSDimitry Andric 484*6e75b2fbSDimitry Andricmulticlass VDIV_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 485*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 486*6e75b2fbSDimitry Andric Sched<[WriteVFDivV, ReadVFDivV, ReadVFDivV, ReadVMask]>; 487*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 488*6e75b2fbSDimitry Andric Sched<[WriteVFDivF, ReadVFDivV, ReadVFDivF, ReadVMask]>; 489*6e75b2fbSDimitry Andric} 490*6e75b2fbSDimitry Andric 491*6e75b2fbSDimitry Andricmulticlass VRDIV_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 492*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 493*6e75b2fbSDimitry Andric Sched<[WriteVFDivF, ReadVFDivV, ReadVFDivF, ReadVMask]>; 494*6e75b2fbSDimitry Andric} 495*6e75b2fbSDimitry Andric 496*6e75b2fbSDimitry Andricmulticlass VWMUL_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 497*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 498*6e75b2fbSDimitry Andric Sched<[WriteVFWMulV, ReadVFWMulV, ReadVFWMulV, ReadVMask]>; 499*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 500*6e75b2fbSDimitry Andric Sched<[WriteVFWMulF, ReadVFWMulV, ReadVFWMulF, ReadVMask]>; 501*6e75b2fbSDimitry Andric} 502*6e75b2fbSDimitry Andric 503*6e75b2fbSDimitry Andricmulticlass VMAC_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 504*6e75b2fbSDimitry Andric def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 505*6e75b2fbSDimitry Andric Sched<[WriteVFMulAddV, ReadVFMulAddV, ReadVFMulAddV, ReadVMask]>; 506*6e75b2fbSDimitry Andric def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 507*6e75b2fbSDimitry Andric Sched<[WriteVFMulAddF, ReadVFMulAddV, ReadVFMulAddF, ReadVMask]>; 508*6e75b2fbSDimitry Andric} 509*6e75b2fbSDimitry Andric 510*6e75b2fbSDimitry Andricmulticlass VWMAC_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 511*6e75b2fbSDimitry Andric def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 512*6e75b2fbSDimitry Andric Sched<[WriteVFWMulAddV, ReadVFWMulAddV, ReadVFWMulAddV, ReadVMask]>; 513*6e75b2fbSDimitry Andric def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 514*6e75b2fbSDimitry Andric Sched<[WriteVFWMulAddF, ReadVFWMulAddV, ReadVFWMulAddF, ReadVMask]>; 515*6e75b2fbSDimitry Andric} 516*6e75b2fbSDimitry Andric 517*6e75b2fbSDimitry Andricmulticlass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 518*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 519*6e75b2fbSDimitry Andric Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>; 520*6e75b2fbSDimitry Andric} 521*6e75b2fbSDimitry Andric 522*6e75b2fbSDimitry Andricmulticlass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 523*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 524*6e75b2fbSDimitry Andric Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>; 525*6e75b2fbSDimitry Andric} 526*6e75b2fbSDimitry Andric 527*6e75b2fbSDimitry Andricmulticlass VCMP_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 528*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 529*6e75b2fbSDimitry Andric Sched<[WriteVFCmpV, ReadVFCmpV, ReadVFCmpV, ReadVMask]>; 530*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 531*6e75b2fbSDimitry Andric Sched<[WriteVFCmpF, ReadVFCmpV, ReadVFCmpF, ReadVMask]>; 532*6e75b2fbSDimitry Andric} 533*6e75b2fbSDimitry Andric 534*6e75b2fbSDimitry Andricmulticlass VCMP_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 535*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 536*6e75b2fbSDimitry Andric Sched<[WriteVFCmpF, ReadVFCmpV, ReadVFCmpF, ReadVMask]>; 537*6e75b2fbSDimitry Andric} 538*6e75b2fbSDimitry Andric 539*6e75b2fbSDimitry Andricmulticlass VSGNJ_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 540*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 541*6e75b2fbSDimitry Andric Sched<[WriteVFSgnjV, ReadVFSgnjV, ReadVFSgnjV, ReadVMask]>; 542*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 543*6e75b2fbSDimitry Andric Sched<[WriteVFSgnjF, ReadVFSgnjV, ReadVFSgnjF, ReadVMask]>; 544*6e75b2fbSDimitry Andric} 545*6e75b2fbSDimitry Andric 546*6e75b2fbSDimitry Andricmulticlass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 547*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 548*6e75b2fbSDimitry Andric Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>; 549*6e75b2fbSDimitry Andric} 550*6e75b2fbSDimitry Andric 551*6e75b2fbSDimitry Andricmulticlass VCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 552*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 553*6e75b2fbSDimitry Andric Sched<[WriteVFCvtIToFV, ReadVFCvtIToFV, ReadVMask]>; 554*6e75b2fbSDimitry Andric} 555*6e75b2fbSDimitry Andric 556*6e75b2fbSDimitry Andricmulticlass VCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 557*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 558*6e75b2fbSDimitry Andric Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>; 559*6e75b2fbSDimitry Andric} 560*6e75b2fbSDimitry Andric 561*6e75b2fbSDimitry Andricmulticlass VWCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 562*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 563*6e75b2fbSDimitry Andric Sched<[WriteVFWCvtIToFV, ReadVFWCvtIToFV, ReadVMask]>; 564*6e75b2fbSDimitry Andric} 565*6e75b2fbSDimitry Andric 566*6e75b2fbSDimitry Andricmulticlass VWCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 567*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 568*6e75b2fbSDimitry Andric Sched<[WriteVFWCvtFToIV, ReadVFWCvtFToIV, ReadVMask]>; 569*6e75b2fbSDimitry Andric} 570*6e75b2fbSDimitry Andric 571*6e75b2fbSDimitry Andricmulticlass VWCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 572*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 573*6e75b2fbSDimitry Andric Sched<[WriteVFWCvtFToFV, ReadVFWCvtFToFV, ReadVMask]>; 574*6e75b2fbSDimitry Andric} 575*6e75b2fbSDimitry Andric 576*6e75b2fbSDimitry Andricmulticlass VNCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 577*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 578*6e75b2fbSDimitry Andric Sched<[WriteVFNCvtIToFV, ReadVFNCvtIToFV, ReadVMask]>; 579*6e75b2fbSDimitry Andric} 580*6e75b2fbSDimitry Andric 581*6e75b2fbSDimitry Andricmulticlass VNCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 582*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 583*6e75b2fbSDimitry Andric Sched<[WriteVFNCvtFToIV, ReadVFNCvtFToIV, ReadVMask]>; 584*6e75b2fbSDimitry Andric} 585*6e75b2fbSDimitry Andric 586*6e75b2fbSDimitry Andricmulticlass VNCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 587*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 588*6e75b2fbSDimitry Andric Sched<[WriteVFNCvtFToFV, ReadVFNCvtFToFV, ReadVMask]>; 589*6e75b2fbSDimitry Andric} 590*6e75b2fbSDimitry Andric 591*6e75b2fbSDimitry Andricmulticlass VRED_MV_V<string opcodestr, bits<6> funct6> { 592*6e75b2fbSDimitry Andric def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">, 593*6e75b2fbSDimitry Andric Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV0, ReadVMask]>; 594*6e75b2fbSDimitry Andric} 595*6e75b2fbSDimitry Andric 596*6e75b2fbSDimitry Andricmulticlass VWRED_IV_V<string opcodestr, bits<6> funct6> { 597*6e75b2fbSDimitry Andric def _VS : VALUVV<funct6, OPIVV, opcodestr # ".vs">, 598*6e75b2fbSDimitry Andric Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV0, ReadVMask]>; 599*6e75b2fbSDimitry Andric} 600*6e75b2fbSDimitry Andric 601*6e75b2fbSDimitry Andricmulticlass VRED_FV_V<string opcodestr, bits<6> funct6> { 602*6e75b2fbSDimitry Andric def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 603*6e75b2fbSDimitry Andric Sched<[WriteVFRedV, ReadVFRedV, ReadVFRedV0, ReadVMask]>; 604*6e75b2fbSDimitry Andric} 605*6e75b2fbSDimitry Andric 606*6e75b2fbSDimitry Andricmulticlass VREDO_FV_V<string opcodestr, bits<6> funct6> { 607*6e75b2fbSDimitry Andric def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 608*6e75b2fbSDimitry Andric Sched<[WriteVFRedOV, ReadVFRedOV, ReadVFRedOV0, ReadVMask]>; 609*6e75b2fbSDimitry Andric} 610*6e75b2fbSDimitry Andric 611*6e75b2fbSDimitry Andricmulticlass VWRED_FV_V<string opcodestr, bits<6> funct6> { 612*6e75b2fbSDimitry Andric def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 613*6e75b2fbSDimitry Andric Sched<[WriteVFWRedV, ReadVFWRedV, ReadVFWRedV0, ReadVMask]>; 614*6e75b2fbSDimitry Andric} 615*6e75b2fbSDimitry Andric 616*6e75b2fbSDimitry Andricmulticlass VWREDO_FV_V<string opcodestr, bits<6> funct6> { 617*6e75b2fbSDimitry Andric def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 618*6e75b2fbSDimitry Andric Sched<[WriteVFWRedOV, ReadVFWRedOV, ReadVFWRedOV0, ReadVMask]>; 619*6e75b2fbSDimitry Andric} 620*6e75b2fbSDimitry Andric 621*6e75b2fbSDimitry Andricmulticlass VMALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> { 622*6e75b2fbSDimitry Andric def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">, 623*6e75b2fbSDimitry Andric Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; 624*6e75b2fbSDimitry Andric} 625*6e75b2fbSDimitry Andric 626*6e75b2fbSDimitry Andricmulticlass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> { 627*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 628*6e75b2fbSDimitry Andric Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; 629*6e75b2fbSDimitry Andric} 630*6e75b2fbSDimitry Andric 631*6e75b2fbSDimitry Andricmulticlass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> { 632*6e75b2fbSDimitry Andric def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 633*6e75b2fbSDimitry Andric Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; 634*6e75b2fbSDimitry Andric} 635*6e75b2fbSDimitry Andric 636*6e75b2fbSDimitry Andricmulticlass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 637*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 638*6e75b2fbSDimitry Andric Sched<[WriteVShiftV, ReadVShiftV, ReadVShiftV, ReadVMask]>; 639*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 640*6e75b2fbSDimitry Andric Sched<[WriteVShiftX, ReadVShiftV, ReadVShiftX, ReadVMask]>; 641*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 642*6e75b2fbSDimitry Andric Sched<[WriteVShiftI, ReadVShiftV, ReadVMask]>; 643*6e75b2fbSDimitry Andric} 644*6e75b2fbSDimitry Andric 645*6e75b2fbSDimitry Andricmulticlass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 646*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 647*6e75b2fbSDimitry Andric Sched<[WriteVNShiftV, ReadVNShiftV, ReadVNShiftV, ReadVMask]>; 648*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 649*6e75b2fbSDimitry Andric Sched<[WriteVNShiftX, ReadVNShiftV, ReadVNShiftX, ReadVMask]>; 650*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 651*6e75b2fbSDimitry Andric Sched<[WriteVNShiftI, ReadVNShiftV, ReadVMask]>; 652*6e75b2fbSDimitry Andric} 653*6e75b2fbSDimitry Andric 654*6e75b2fbSDimitry Andricmulticlass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 655*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 656*6e75b2fbSDimitry Andric Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>; 657*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 658*6e75b2fbSDimitry Andric Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>; 659*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 660*6e75b2fbSDimitry Andric Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>; 661*6e75b2fbSDimitry Andric} 662*6e75b2fbSDimitry Andric 663*6e75b2fbSDimitry Andricmulticlass VCMP_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 664*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 665*6e75b2fbSDimitry Andric Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpX, ReadVMask]>; 666*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 667*6e75b2fbSDimitry Andric Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>; 668*6e75b2fbSDimitry Andric} 669*6e75b2fbSDimitry Andric 670*6e75b2fbSDimitry Andricmulticlass VCMP_IV_V_X<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 671*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 672*6e75b2fbSDimitry Andric Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>; 673*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 674*6e75b2fbSDimitry Andric Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>; 675*6e75b2fbSDimitry Andric} 676*6e75b2fbSDimitry Andric 677*6e75b2fbSDimitry Andricmulticlass VMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 678*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 679*6e75b2fbSDimitry Andric Sched<[WriteVIMulV, ReadVIMulV, ReadVIMulV, ReadVMask]>; 680*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 681*6e75b2fbSDimitry Andric Sched<[WriteVIMulX, ReadVIMulV, ReadVIMulX, ReadVMask]>; 682*6e75b2fbSDimitry Andric} 683*6e75b2fbSDimitry Andric 684*6e75b2fbSDimitry Andricmulticlass VWMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 685*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 686*6e75b2fbSDimitry Andric Sched<[WriteVIWMulV, ReadVIWMulV, ReadVIWMulV, ReadVMask]>; 687*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 688*6e75b2fbSDimitry Andric Sched<[WriteVIWMulX, ReadVIWMulV, ReadVIWMulX, ReadVMask]>; 689*6e75b2fbSDimitry Andric} 690*6e75b2fbSDimitry Andric 691*6e75b2fbSDimitry Andricmulticlass VDIV_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 692*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 693*6e75b2fbSDimitry Andric Sched<[WriteVIDivV, ReadVIDivV, ReadVIDivV, ReadVMask]>; 694*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 695*6e75b2fbSDimitry Andric Sched<[WriteVIDivX, ReadVIDivV, ReadVIDivX, ReadVMask]>; 696*6e75b2fbSDimitry Andric} 697*6e75b2fbSDimitry Andric 698*6e75b2fbSDimitry Andricmulticlass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 699*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 700*6e75b2fbSDimitry Andric Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>; 701*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 702*6e75b2fbSDimitry Andric Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>; 703*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 704*6e75b2fbSDimitry Andric Sched<[WriteVSALUI, ReadVSALUV, ReadVMask]>; 705*6e75b2fbSDimitry Andric} 706*6e75b2fbSDimitry Andric 707*6e75b2fbSDimitry Andricmulticlass VSALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 708*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 709*6e75b2fbSDimitry Andric Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>; 710*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 711*6e75b2fbSDimitry Andric Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>; 712*6e75b2fbSDimitry Andric} 713*6e75b2fbSDimitry Andric 714*6e75b2fbSDimitry Andricmulticlass VAALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 715*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 716*6e75b2fbSDimitry Andric Sched<[WriteVAALUV, ReadVAALUV, ReadVAALUV, ReadVMask]>; 717*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 718*6e75b2fbSDimitry Andric Sched<[WriteVAALUX, ReadVAALUV, ReadVAALUX, ReadVMask]>; 719*6e75b2fbSDimitry Andric} 720*6e75b2fbSDimitry Andric 721*6e75b2fbSDimitry Andricmulticlass VSMUL_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 722*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 723*6e75b2fbSDimitry Andric Sched<[WriteVSMulV, ReadVSMulV, ReadVSMulV, ReadVMask]>; 724*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 725*6e75b2fbSDimitry Andric Sched<[WriteVSMulX, ReadVSMulV, ReadVSMulX, ReadVMask]>; 726*6e75b2fbSDimitry Andric} 727*6e75b2fbSDimitry Andric 728*6e75b2fbSDimitry Andricmulticlass VSSHF_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 729*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 730*6e75b2fbSDimitry Andric Sched<[WriteVSShiftV, ReadVSShiftV, ReadVSShiftV, ReadVMask]>; 731*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 732*6e75b2fbSDimitry Andric Sched<[WriteVSShiftX, ReadVSShiftV, ReadVSShiftX, ReadVMask]>; 733*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 734*6e75b2fbSDimitry Andric Sched<[WriteVSShiftI, ReadVSShiftV, ReadVMask]>; 735*6e75b2fbSDimitry Andric} 736*6e75b2fbSDimitry Andric 737*6e75b2fbSDimitry Andricmulticlass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 738*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 739*6e75b2fbSDimitry Andric Sched<[WriteVNClipV, ReadVNClipV, ReadVNClipV, ReadVMask]>; 740*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 741*6e75b2fbSDimitry Andric Sched<[WriteVNClipX, ReadVNClipV, ReadVNClipX, ReadVMask]>; 742*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 743*6e75b2fbSDimitry Andric Sched<[WriteVNClipI, ReadVNClipV, ReadVMask]>; 744*6e75b2fbSDimitry Andric} 745*6e75b2fbSDimitry Andric 746*6e75b2fbSDimitry Andricmulticlass VSLD_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 747*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 748*6e75b2fbSDimitry Andric Sched<[WriteVISlideX, ReadVISlideV, ReadVISlideX, ReadVMask]>; 749*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 750*6e75b2fbSDimitry Andric Sched<[WriteVISlideI, ReadVISlideV, ReadVMask]>; 751*6e75b2fbSDimitry Andric} 752*6e75b2fbSDimitry Andric 753*6e75b2fbSDimitry Andricmulticlass VSLD1_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> { 754*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 755*6e75b2fbSDimitry Andric Sched<[WriteVISlide1X, ReadVISlideV, ReadVISlideX, ReadVMask]>; 756*6e75b2fbSDimitry Andric} 757*6e75b2fbSDimitry Andric 758*6e75b2fbSDimitry Andricmulticlass VSLD1_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 759*6e75b2fbSDimitry Andric def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 760*6e75b2fbSDimitry Andric Sched<[WriteVFSlide1F, ReadVFSlideV, ReadVFSlideF, ReadVMask]>; 761*6e75b2fbSDimitry Andric} 762*6e75b2fbSDimitry Andric 763*6e75b2fbSDimitry Andricmulticlass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 764*6e75b2fbSDimitry Andric def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 765*6e75b2fbSDimitry Andric Sched<[WriteVGatherV, ReadVGatherV, ReadVGatherV, ReadVMask]>; 766*6e75b2fbSDimitry Andric def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 767*6e75b2fbSDimitry Andric Sched<[WriteVGatherX, ReadVGatherV, ReadVGatherX, ReadVMask]>; 768*6e75b2fbSDimitry Andric def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 769*6e75b2fbSDimitry Andric Sched<[WriteVGatherI, ReadVGatherV, ReadVMask]>; 770*6e75b2fbSDimitry Andric} 771*6e75b2fbSDimitry Andric 772*6e75b2fbSDimitry Andricmulticlass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> { 773*6e75b2fbSDimitry Andric def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">, 774*6e75b2fbSDimitry Andric Sched<[WriteVCompressV, ReadVCompressV, ReadVCompressV]>; 7755ffd83dbSDimitry Andric} 7765ffd83dbSDimitry Andric 777e8d8bef9SDimitry Andricmulticlass VAMO<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> { 778e8d8bef9SDimitry Andric def _WD : VAMOWd<amoop, width, opcodestr>; 779e8d8bef9SDimitry Andric def _UNWD : VAMONoWd<amoop, width, opcodestr>; 780e8d8bef9SDimitry Andric} 781e8d8bef9SDimitry Andric 782*6e75b2fbSDimitry Andricmulticlass VWholeLoad1<string opcodestr, RegisterClass VRC> { 783*6e75b2fbSDimitry Andric def E8_V : VWholeLoad<0, LSWidth8, opcodestr # "e8.v", VRC>, 784*6e75b2fbSDimitry Andric Sched<[WriteVLD1R8, ReadVLDX]>; 785*6e75b2fbSDimitry Andric def E16_V : VWholeLoad<0, LSWidth16, opcodestr # "e16.v", VRC>, 786*6e75b2fbSDimitry Andric Sched<[WriteVLD1R16, ReadVLDX]>; 787*6e75b2fbSDimitry Andric def E32_V : VWholeLoad<0, LSWidth32, opcodestr # "e32.v", VRC>, 788*6e75b2fbSDimitry Andric Sched<[WriteVLD1R32, ReadVLDX]>; 789*6e75b2fbSDimitry Andric def E64_V : VWholeLoad<0, LSWidth64, opcodestr # "e64.v", VRC>, 790*6e75b2fbSDimitry Andric Sched<[WriteVLD1R64, ReadVLDX]>; 791*6e75b2fbSDimitry Andric} 792*6e75b2fbSDimitry Andric 793*6e75b2fbSDimitry Andricmulticlass VWholeLoad2<string opcodestr, RegisterClass VRC> { 794*6e75b2fbSDimitry Andric def E8_V : VWholeLoad<1, LSWidth8, opcodestr # "e8.v", VRC>, 795*6e75b2fbSDimitry Andric Sched<[WriteVLD2R8, ReadVLDX]>; 796*6e75b2fbSDimitry Andric def E16_V : VWholeLoad<1, LSWidth16, opcodestr # "e16.v", VRC>, 797*6e75b2fbSDimitry Andric Sched<[WriteVLD2R16, ReadVLDX]>; 798*6e75b2fbSDimitry Andric def E32_V : VWholeLoad<1, LSWidth32, opcodestr # "e32.v", VRC>, 799*6e75b2fbSDimitry Andric Sched<[WriteVLD2R32, ReadVLDX]>; 800*6e75b2fbSDimitry Andric def E64_V : VWholeLoad<1, LSWidth64, opcodestr # "e64.v", VRC>, 801*6e75b2fbSDimitry Andric Sched<[WriteVLD2R64, ReadVLDX]>; 802*6e75b2fbSDimitry Andric} 803*6e75b2fbSDimitry Andric 804*6e75b2fbSDimitry Andricmulticlass VWholeLoad4<string opcodestr, RegisterClass VRC> { 805*6e75b2fbSDimitry Andric def E8_V : VWholeLoad<3, LSWidth8, opcodestr # "e8.v", VRC>, 806*6e75b2fbSDimitry Andric Sched<[WriteVLD4R8, ReadVLDX]>; 807*6e75b2fbSDimitry Andric def E16_V : VWholeLoad<3, LSWidth16, opcodestr # "e16.v", VRC>, 808*6e75b2fbSDimitry Andric Sched<[WriteVLD4R16, ReadVLDX]>; 809*6e75b2fbSDimitry Andric def E32_V : VWholeLoad<3, LSWidth32, opcodestr # "e32.v", VRC>, 810*6e75b2fbSDimitry Andric Sched<[WriteVLD4R32, ReadVLDX]>; 811*6e75b2fbSDimitry Andric def E64_V : VWholeLoad<3, LSWidth64, opcodestr # "e64.v", VRC>, 812*6e75b2fbSDimitry Andric Sched<[WriteVLD1R64, ReadVLDX]>; 813*6e75b2fbSDimitry Andric} 814*6e75b2fbSDimitry Andric 815*6e75b2fbSDimitry Andricmulticlass VWholeLoad8<string opcodestr, RegisterClass VRC> { 816*6e75b2fbSDimitry Andric def E8_V : VWholeLoad<7, LSWidth8, opcodestr # "e8.v", VRC>, 817*6e75b2fbSDimitry Andric Sched<[WriteVLD8R8, ReadVLDX]>; 818*6e75b2fbSDimitry Andric def E16_V : VWholeLoad<7, LSWidth16, opcodestr # "e16.v", VRC>, 819*6e75b2fbSDimitry Andric Sched<[WriteVLD8R16, ReadVLDX]>; 820*6e75b2fbSDimitry Andric def E32_V : VWholeLoad<7, LSWidth32, opcodestr # "e32.v", VRC>, 821*6e75b2fbSDimitry Andric Sched<[WriteVLD8R32, ReadVLDX]>; 822*6e75b2fbSDimitry Andric def E64_V : VWholeLoad<7, LSWidth64, opcodestr # "e64.v", VRC>, 823*6e75b2fbSDimitry Andric Sched<[WriteVLD8R64, ReadVLDX]>; 824e8d8bef9SDimitry Andric} 825e8d8bef9SDimitry Andric 8265ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 8275ffd83dbSDimitry Andric// Instructions 8285ffd83dbSDimitry Andric//===----------------------------------------------------------------------===// 8295ffd83dbSDimitry Andric 8305ffd83dbSDimitry Andriclet Predicates = [HasStdExtV] in { 8315ffd83dbSDimitry Andriclet hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 8325ffd83dbSDimitry Andricdef VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), 8335ffd83dbSDimitry Andric "vsetvli", "$rd, $rs1, $vtypei">; 8345ffd83dbSDimitry Andric 835d409305fSDimitry Andricdef VSETIVLI : RVInstSetiVLi<(outs GPR:$rd), (ins uimm5:$uimm, VTypeIOp:$vtypei), 836d409305fSDimitry Andric "vsetivli", "$rd, $uimm, $vtypei">; 837d409305fSDimitry Andric 8385ffd83dbSDimitry Andricdef VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), 8395ffd83dbSDimitry Andric "vsetvl", "$rd, $rs1, $rs2">; 8405ffd83dbSDimitry Andric} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 8415ffd83dbSDimitry Andric 8425ffd83dbSDimitry Andric// Vector Unit-Stride Instructions 843*6e75b2fbSDimitry Andricdef VLE8_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth8, "vle8.v">, 844*6e75b2fbSDimitry Andric VLESched<8>; 845*6e75b2fbSDimitry Andricdef VLE16_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth16, "vle16.v">, 846*6e75b2fbSDimitry Andric VLESched<16>; 847*6e75b2fbSDimitry Andricdef VLE32_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth32, "vle32.v">, 848*6e75b2fbSDimitry Andric VLESched<32>; 849*6e75b2fbSDimitry Andricdef VLE64_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth64, "vle64.v">, 850*6e75b2fbSDimitry Andric VLESched<64>; 8515ffd83dbSDimitry Andric 852*6e75b2fbSDimitry Andricdef VLE8FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth8, "vle8ff.v">, 853*6e75b2fbSDimitry Andric VLFSched<8>; 854*6e75b2fbSDimitry Andricdef VLE16FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth16, "vle16ff.v">, 855*6e75b2fbSDimitry Andric VLFSched<16>; 856*6e75b2fbSDimitry Andricdef VLE32FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth32, "vle32ff.v">, 857*6e75b2fbSDimitry Andric VLFSched<32>; 858*6e75b2fbSDimitry Andricdef VLE64FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth64, "vle64ff.v">, 859*6e75b2fbSDimitry Andric VLFSched<64>; 860d409305fSDimitry Andric 861*6e75b2fbSDimitry Andricdef VLE1_V : VUnitStrideLoadMask<"vle1.v">, 862*6e75b2fbSDimitry Andric Sched<[WriteVLDM, ReadVLDX]>; 863*6e75b2fbSDimitry Andricdef VSE1_V : VUnitStrideStoreMask<"vse1.v">, 864*6e75b2fbSDimitry Andric Sched<[WriteVSTM, ReadVSTM, ReadVSTX]>; 8655ffd83dbSDimitry Andric 866*6e75b2fbSDimitry Andricdef VSE8_V : VUnitStrideStore<SUMOPUnitStride, LSWidth8, "vse8.v">, 867*6e75b2fbSDimitry Andric VSESched<8>; 868*6e75b2fbSDimitry Andricdef VSE16_V : VUnitStrideStore<SUMOPUnitStride, LSWidth16, "vse16.v">, 869*6e75b2fbSDimitry Andric VSESched<16>; 870*6e75b2fbSDimitry Andricdef VSE32_V : VUnitStrideStore<SUMOPUnitStride, LSWidth32, "vse32.v">, 871*6e75b2fbSDimitry Andric VSESched<32>; 872*6e75b2fbSDimitry Andricdef VSE64_V : VUnitStrideStore<SUMOPUnitStride, LSWidth64, "vse64.v">, 873*6e75b2fbSDimitry Andric VSESched<64>; 8745ffd83dbSDimitry Andric 8755ffd83dbSDimitry Andric// Vector Strided Instructions 876*6e75b2fbSDimitry Andricdef VLSE8_V : VStridedLoad<LSWidth8, "vlse8.v">, 877*6e75b2fbSDimitry Andric VLSSched<8>; 878*6e75b2fbSDimitry Andricdef VLSE16_V : VStridedLoad<LSWidth16, "vlse16.v">, 879*6e75b2fbSDimitry Andric VLSSched<16>; 880*6e75b2fbSDimitry Andricdef VLSE32_V : VStridedLoad<LSWidth32, "vlse32.v">, 881*6e75b2fbSDimitry Andric VLSSched<32>; 882*6e75b2fbSDimitry Andricdef VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">, 883*6e75b2fbSDimitry Andric VLSSched<32>; 8845ffd83dbSDimitry Andric 885*6e75b2fbSDimitry Andricdef VSSE8_V : VStridedStore<LSWidth8, "vsse8.v">, 886*6e75b2fbSDimitry Andric VSSSched<8>; 887*6e75b2fbSDimitry Andricdef VSSE16_V : VStridedStore<LSWidth16, "vsse16.v">, 888*6e75b2fbSDimitry Andric VSSSched<16>; 889*6e75b2fbSDimitry Andricdef VSSE32_V : VStridedStore<LSWidth32, "vsse32.v">, 890*6e75b2fbSDimitry Andric VSSSched<32>; 891*6e75b2fbSDimitry Andricdef VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">, 892*6e75b2fbSDimitry Andric VSSSched<64>; 8935ffd83dbSDimitry Andric 8945ffd83dbSDimitry Andric// Vector Indexed Instructions 895*6e75b2fbSDimitry Andricforeach n = [8, 16, 32, 64] in { 896*6e75b2fbSDimitry Andricdefvar w = !cast<RISCVWidth>("LSWidth" # n); 8975ffd83dbSDimitry Andric 898*6e75b2fbSDimitry Andricdef VLUXEI # n # _V : 899*6e75b2fbSDimitry Andric VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # n # ".v">, 900*6e75b2fbSDimitry Andric VLXSched<n, "U">; 901*6e75b2fbSDimitry Andricdef VLOXEI # n # _V : 902*6e75b2fbSDimitry Andric VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # n # ".v">, 903*6e75b2fbSDimitry Andric VLXSched<n, "O">; 9045ffd83dbSDimitry Andric 905*6e75b2fbSDimitry Andricdef VSUXEI # n # _V : 906*6e75b2fbSDimitry Andric VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # n # ".v">, 907*6e75b2fbSDimitry Andric VSXSched<n, "U">; 908*6e75b2fbSDimitry Andricdef VSOXEI # n # _V : 909*6e75b2fbSDimitry Andric VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # n # ".v">, 910*6e75b2fbSDimitry Andric VSXSched<n, "O">; 911*6e75b2fbSDimitry Andric} 9125ffd83dbSDimitry Andric 913*6e75b2fbSDimitry Andricdefm VL1R : VWholeLoad1<"vl1r", VR>; 914*6e75b2fbSDimitry Andricdefm VL2R : VWholeLoad2<"vl2r", VRM2>; 915*6e75b2fbSDimitry Andricdefm VL4R : VWholeLoad4<"vl4r", VRM4>; 916*6e75b2fbSDimitry Andricdefm VL8R : VWholeLoad8<"vl8r", VRM8>; 9175ffd83dbSDimitry Andric 918e8d8bef9SDimitry Andricdef : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; 919fe6060f1SDimitry Andricdef : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; 920fe6060f1SDimitry Andricdef : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; 921fe6060f1SDimitry Andricdef : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; 9225ffd83dbSDimitry Andric 923*6e75b2fbSDimitry Andricdef VS1R_V : VWholeStore<0, "vs1r.v", VR>, 924*6e75b2fbSDimitry Andric Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>; 925*6e75b2fbSDimitry Andricdef VS2R_V : VWholeStore<1, "vs2r.v", VRM2>, 926*6e75b2fbSDimitry Andric Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>; 927*6e75b2fbSDimitry Andricdef VS4R_V : VWholeStore<3, "vs4r.v", VRM4>, 928*6e75b2fbSDimitry Andric Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>; 929*6e75b2fbSDimitry Andricdef VS8R_V : VWholeStore<7, "vs8r.v", VRM8>, 930*6e75b2fbSDimitry Andric Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>; 9315ffd83dbSDimitry Andric 9325ffd83dbSDimitry Andric// Vector Single-Width Integer Add and Subtract 9335ffd83dbSDimitry Andricdefm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; 9345ffd83dbSDimitry Andricdefm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; 9355ffd83dbSDimitry Andricdefm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; 9365ffd83dbSDimitry Andric 937e8d8bef9SDimitry Andricdef : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 938e8d8bef9SDimitry Andric 9395ffd83dbSDimitry Andric// Vector Widening Integer Add/Subtract 9405ffd83dbSDimitry Andric// Refer to 11.2 Widening Vector Arithmetic Instructions 9415ffd83dbSDimitry Andric// The destination vector register group cannot overlap a source vector 9425ffd83dbSDimitry Andric// register group of a different element width (including the mask register 9435ffd83dbSDimitry Andric// if masked), otherwise an illegal instruction exception is raised. 9445ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd" in { 9455ffd83dbSDimitry Andriclet RVVConstraint = WidenV in { 9465ffd83dbSDimitry Andricdefm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>; 9475ffd83dbSDimitry Andricdefm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010>; 9485ffd83dbSDimitry Andricdefm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001>; 9495ffd83dbSDimitry Andricdefm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011>; 9505ffd83dbSDimitry Andric} // RVVConstraint = WidenV 9515ffd83dbSDimitry Andric// Set earlyclobber for following instructions for second and mask operands. 9525ffd83dbSDimitry Andric// This has the downside that the earlyclobber constraint is too coarse and 9535ffd83dbSDimitry Andric// will impose unnecessary restrictions by not allowing the destination to 9545ffd83dbSDimitry Andric// overlap with the first (wide) operand. 9555ffd83dbSDimitry Andriclet RVVConstraint = WidenW in { 9565ffd83dbSDimitry Andricdefm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">; 9575ffd83dbSDimitry Andricdefm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">; 9585ffd83dbSDimitry Andricdefm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">; 9595ffd83dbSDimitry Andricdefm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">; 9605ffd83dbSDimitry Andric} // RVVConstraint = WidenW 9615ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd" 9625ffd83dbSDimitry Andric 9635ffd83dbSDimitry Andricdef : InstAlias<"vwcvt.x.x.v $vd, $vs$vm", 964e8d8bef9SDimitry Andric (VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 9655ffd83dbSDimitry Andricdef : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm", 966e8d8bef9SDimitry Andric (VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 967e8d8bef9SDimitry Andric 968e8d8bef9SDimitry Andric// Vector Integer Extension 969e8d8bef9SDimitry Andricdefm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>; 970e8d8bef9SDimitry Andricdefm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>; 971e8d8bef9SDimitry Andricdefm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>; 972e8d8bef9SDimitry Andricdefm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>; 973e8d8bef9SDimitry Andricdefm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>; 974e8d8bef9SDimitry Andricdefm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>; 9755ffd83dbSDimitry Andric 9765ffd83dbSDimitry Andric// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions 9775ffd83dbSDimitry Andricdefm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>; 978e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 9795ffd83dbSDimitry Andricdefm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>; 9805ffd83dbSDimitry Andricdefm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>; 981e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 9825ffd83dbSDimitry Andricdefm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>; 983e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 9845ffd83dbSDimitry Andricdefm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>; 9855ffd83dbSDimitry Andricdefm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>; 986e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 9875ffd83dbSDimitry Andric 9885ffd83dbSDimitry Andric// Vector Bitwise Logical Instructions 9895ffd83dbSDimitry Andricdefm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; 9905ffd83dbSDimitry Andricdefm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>; 9915ffd83dbSDimitry Andricdefm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>; 9925ffd83dbSDimitry Andric 9935ffd83dbSDimitry Andricdef : InstAlias<"vnot.v $vd, $vs$vm", 994e8d8bef9SDimitry Andric (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>; 9955ffd83dbSDimitry Andric 9965ffd83dbSDimitry Andric// Vector Single-Width Bit Shift Instructions 997*6e75b2fbSDimitry Andricdefm VSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101, uimm5>; 998*6e75b2fbSDimitry Andricdefm VSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000, uimm5>; 999*6e75b2fbSDimitry Andricdefm VSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001, uimm5>; 10005ffd83dbSDimitry Andric 10015ffd83dbSDimitry Andric// Vector Narrowing Integer Right Shift Instructions 10025ffd83dbSDimitry Andric// Refer to 11.3. Narrowing Vector Arithmetic Instructions 10035ffd83dbSDimitry Andric// The destination vector register group cannot overlap the first source 10045ffd83dbSDimitry Andric// vector register group (specified by vs2). The destination vector register 10055ffd83dbSDimitry Andric// group cannot overlap the mask register if used, unless LMUL=1. 1006e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd" in { 1007*6e75b2fbSDimitry Andricdefm VNSRL_W : VNSHT_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">; 1008*6e75b2fbSDimitry Andricdefm VNSRA_W : VNSHT_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">; 1009e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd" 1010e8d8bef9SDimitry Andric 1011e8d8bef9SDimitry Andricdef : InstAlias<"vncvt.x.x.w $vd, $vs$vm", 1012e8d8bef9SDimitry Andric (VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 10135ffd83dbSDimitry Andric 10145ffd83dbSDimitry Andric// Vector Integer Comparison Instructions 1015e8d8bef9SDimitry Andriclet RVVConstraint = NoConstraint in { 1016*6e75b2fbSDimitry Andricdefm VMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>; 1017*6e75b2fbSDimitry Andricdefm VMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>; 1018*6e75b2fbSDimitry Andricdefm VMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>; 1019*6e75b2fbSDimitry Andricdefm VMSLT_V : VCMP_IV_V_X<"vmslt", 0b011011>; 1020*6e75b2fbSDimitry Andricdefm VMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>; 1021*6e75b2fbSDimitry Andricdefm VMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>; 1022*6e75b2fbSDimitry Andricdefm VMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>; 1023*6e75b2fbSDimitry Andricdefm VMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>; 1024e8d8bef9SDimitry Andric} // RVVConstraint = NoConstraint 10255ffd83dbSDimitry Andric 10265ffd83dbSDimitry Andricdef : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm", 1027e8d8bef9SDimitry Andric (VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 10285ffd83dbSDimitry Andricdef : InstAlias<"vmsgt.vv $vd, $va, $vb$vm", 1029e8d8bef9SDimitry Andric (VMSLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 10305ffd83dbSDimitry Andricdef : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm", 1031e8d8bef9SDimitry Andric (VMSLEU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 10325ffd83dbSDimitry Andricdef : InstAlias<"vmsge.vv $vd, $va, $vb$vm", 1033e8d8bef9SDimitry Andric (VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1034e8d8bef9SDimitry Andric 1035e8d8bef9SDimitry Andriclet isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, 1036e8d8bef9SDimitry Andric mayStore = 0 in { 1037e8d8bef9SDimitry Andric// For unsigned comparisons we need to special case 0 immediate to maintain 1038e8d8bef9SDimitry Andric// the always true/false semantics we would invert if we just decremented the 1039e8d8bef9SDimitry Andric// immediate like we do for signed. To match the GNU assembler we will use 1040e8d8bef9SDimitry Andric// vmseq/vmsne.vv with the same register for both operands which we can't do 1041e8d8bef9SDimitry Andric// from an InstAlias. 1042e8d8bef9SDimitry Andricdef PseudoVMSGEU_VI : Pseudo<(outs VR:$vd), 1043e8d8bef9SDimitry Andric (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1044e8d8bef9SDimitry Andric [], "vmsgeu.vi", "$vd, $vs2, $imm$vm">; 1045e8d8bef9SDimitry Andricdef PseudoVMSLTU_VI : Pseudo<(outs VR:$vd), 1046e8d8bef9SDimitry Andric (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1047e8d8bef9SDimitry Andric [], "vmsltu.vi", "$vd, $vs2, $imm$vm">; 1048e8d8bef9SDimitry Andric// Handle signed with pseudos as well for more consistency in the 1049e8d8bef9SDimitry Andric// implementation. 1050e8d8bef9SDimitry Andricdef PseudoVMSGE_VI : Pseudo<(outs VR:$vd), 1051e8d8bef9SDimitry Andric (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1052e8d8bef9SDimitry Andric [], "vmsge.vi", "$vd, $vs2, $imm$vm">; 1053e8d8bef9SDimitry Andricdef PseudoVMSLT_VI : Pseudo<(outs VR:$vd), 1054e8d8bef9SDimitry Andric (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1055e8d8bef9SDimitry Andric [], "vmslt.vi", "$vd, $vs2, $imm$vm">; 1056e8d8bef9SDimitry Andric} 1057e8d8bef9SDimitry Andric 1058e8d8bef9SDimitry Andriclet isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, 1059e8d8bef9SDimitry Andric mayStore = 0 in { 1060e8d8bef9SDimitry Andricdef PseudoVMSGEU_VX : Pseudo<(outs VR:$vd), 1061e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1), 1062e8d8bef9SDimitry Andric [], "vmsgeu.vx", "$vd, $vs2, $rs1">; 1063e8d8bef9SDimitry Andricdef PseudoVMSGE_VX : Pseudo<(outs VR:$vd), 1064e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1), 1065e8d8bef9SDimitry Andric [], "vmsge.vx", "$vd, $vs2, $rs1">; 1066e8d8bef9SDimitry Andricdef PseudoVMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd), 1067e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1068e8d8bef9SDimitry Andric [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">; 1069e8d8bef9SDimitry Andricdef PseudoVMSGE_VX_M : Pseudo<(outs VRNoV0:$vd), 1070e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1071e8d8bef9SDimitry Andric [], "vmsge.vx", "$vd, $vs2, $rs1$vm">; 1072fe6060f1SDimitry Andricdef PseudoVMSGEU_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), 1073e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1074e8d8bef9SDimitry Andric [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">; 1075fe6060f1SDimitry Andricdef PseudoVMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), 1076e8d8bef9SDimitry Andric (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1077e8d8bef9SDimitry Andric [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">; 1078e8d8bef9SDimitry Andric} 10795ffd83dbSDimitry Andric 10805ffd83dbSDimitry Andric// Vector Integer Min/Max Instructions 1081*6e75b2fbSDimitry Andricdefm VMINU_V : VCMP_IV_V_X<"vminu", 0b000100>; 1082*6e75b2fbSDimitry Andricdefm VMIN_V : VCMP_IV_V_X<"vmin", 0b000101>; 1083*6e75b2fbSDimitry Andricdefm VMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>; 1084*6e75b2fbSDimitry Andricdefm VMAX_V : VCMP_IV_V_X<"vmax", 0b000111>; 10855ffd83dbSDimitry Andric 10865ffd83dbSDimitry Andric// Vector Single-Width Integer Multiply Instructions 1087*6e75b2fbSDimitry Andricdefm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>; 1088*6e75b2fbSDimitry Andricdefm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; 1089*6e75b2fbSDimitry Andricdefm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; 1090*6e75b2fbSDimitry Andricdefm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; 10915ffd83dbSDimitry Andric 10925ffd83dbSDimitry Andric// Vector Integer Divide Instructions 1093*6e75b2fbSDimitry Andricdefm VDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>; 1094*6e75b2fbSDimitry Andricdefm VDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>; 1095*6e75b2fbSDimitry Andricdefm VREMU_V : VDIV_MV_V_X<"vremu", 0b100010>; 1096*6e75b2fbSDimitry Andricdefm VREM_V : VDIV_MV_V_X<"vrem", 0b100011>; 10975ffd83dbSDimitry Andric 10985ffd83dbSDimitry Andric// Vector Widening Integer Multiply Instructions 10995ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1100*6e75b2fbSDimitry Andricdefm VWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>; 1101*6e75b2fbSDimitry Andricdefm VWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>; 1102*6e75b2fbSDimitry Andricdefm VWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>; 11035ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 11045ffd83dbSDimitry Andric 11055ffd83dbSDimitry Andric// Vector Single-Width Integer Multiply-Add Instructions 1106*6e75b2fbSDimitry Andricdefm VMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>; 1107*6e75b2fbSDimitry Andricdefm VNMSAC_V : VMAC_MV_V_X<"vnmsac", 0b101111>; 1108*6e75b2fbSDimitry Andricdefm VMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>; 1109*6e75b2fbSDimitry Andricdefm VNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>; 11105ffd83dbSDimitry Andric 11115ffd83dbSDimitry Andric// Vector Widening Integer Multiply-Add Instructions 11125ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1113*6e75b2fbSDimitry Andricdefm VWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>; 1114*6e75b2fbSDimitry Andricdefm VWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>; 1115*6e75b2fbSDimitry Andricdefm VWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>; 1116*6e75b2fbSDimitry Andricdefm VWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>; 11175ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 11185ffd83dbSDimitry Andric 11195ffd83dbSDimitry Andric// Vector Integer Merge Instructions 1120*6e75b2fbSDimitry Andricdefm VMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>; 11215ffd83dbSDimitry Andric 11225ffd83dbSDimitry Andric// Vector Integer Move Instructions 1123e8d8bef9SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1, 1124e8d8bef9SDimitry Andric RVVConstraint = NoConstraint in { 11255ffd83dbSDimitry Andric// op vd, vs1 1126e8d8bef9SDimitry Andricdef VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd), 1127*6e75b2fbSDimitry Andric (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">, 1128*6e75b2fbSDimitry Andric Sched<[WriteVIMovV, ReadVIMovV]>; 11295ffd83dbSDimitry Andric// op vd, rs1 1130e8d8bef9SDimitry Andricdef VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd), 1131*6e75b2fbSDimitry Andric (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">, 1132*6e75b2fbSDimitry Andric Sched<[WriteVIMovX, ReadVIMovX]>; 11335ffd83dbSDimitry Andric// op vd, imm 1134e8d8bef9SDimitry Andricdef VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd), 1135*6e75b2fbSDimitry Andric (ins simm5:$imm), "vmv.v.i", "$vd, $imm">, 1136*6e75b2fbSDimitry Andric Sched<[WriteVIMovI]>; 11375ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 11385ffd83dbSDimitry Andric 11395ffd83dbSDimitry Andric// Vector Fixed-Point Arithmetic Instructions 1140*6e75b2fbSDimitry Andricdefm VSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>; 1141*6e75b2fbSDimitry Andricdefm VSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>; 1142*6e75b2fbSDimitry Andricdefm VSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>; 1143*6e75b2fbSDimitry Andricdefm VSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>; 11445ffd83dbSDimitry Andric 11455ffd83dbSDimitry Andric// Vector Single-Width Averaging Add and Subtract 1146*6e75b2fbSDimitry Andricdefm VAADDU_V : VAALU_MV_V_X<"vaaddu", 0b001000>; 1147*6e75b2fbSDimitry Andricdefm VAADD_V : VAALU_MV_V_X<"vaadd", 0b001001>; 1148*6e75b2fbSDimitry Andricdefm VASUBU_V : VAALU_MV_V_X<"vasubu", 0b001010>; 1149*6e75b2fbSDimitry Andricdefm VASUB_V : VAALU_MV_V_X<"vasub", 0b001011>; 11505ffd83dbSDimitry Andric 11515ffd83dbSDimitry Andric// Vector Single-Width Fractional Multiply with Rounding and Saturation 1152*6e75b2fbSDimitry Andricdefm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>; 11535ffd83dbSDimitry Andric 11545ffd83dbSDimitry Andric// Vector Single-Width Scaling Shift Instructions 1155*6e75b2fbSDimitry Andricdefm VSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010, uimm5>; 1156*6e75b2fbSDimitry Andricdefm VSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011, uimm5>; 11575ffd83dbSDimitry Andric 11585ffd83dbSDimitry Andric// Vector Narrowing Fixed-Point Clip Instructions 1159e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd" in { 1160*6e75b2fbSDimitry Andricdefm VNCLIPU_W : VNCLP_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">; 1161*6e75b2fbSDimitry Andricdefm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">; 1162e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd" 1163e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV] 11645ffd83dbSDimitry Andric 1165e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV, HasStdExtF] in { 11665ffd83dbSDimitry Andric// Vector Single-Width Floating-Point Add/Subtract Instructions 11675ffd83dbSDimitry Andricdefm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>; 11685ffd83dbSDimitry Andricdefm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>; 11695ffd83dbSDimitry Andricdefm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>; 11705ffd83dbSDimitry Andric 11715ffd83dbSDimitry Andric// Vector Widening Floating-Point Add/Subtract Instructions 11725ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd" in { 11735ffd83dbSDimitry Andriclet RVVConstraint = WidenV in { 1174*6e75b2fbSDimitry Andricdefm VFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000>; 1175*6e75b2fbSDimitry Andricdefm VFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010>; 11765ffd83dbSDimitry Andric} // RVVConstraint = WidenV 11775ffd83dbSDimitry Andric// Set earlyclobber for following instructions for second and mask operands. 11785ffd83dbSDimitry Andric// This has the downside that the earlyclobber constraint is too coarse and 11795ffd83dbSDimitry Andric// will impose unnecessary restrictions by not allowing the destination to 11805ffd83dbSDimitry Andric// overlap with the first (wide) operand. 11815ffd83dbSDimitry Andriclet RVVConstraint = WidenW in { 1182*6e75b2fbSDimitry Andricdefm VFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">; 1183*6e75b2fbSDimitry Andricdefm VFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">; 11845ffd83dbSDimitry Andric} // RVVConstraint = WidenW 11855ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd" 11865ffd83dbSDimitry Andric 11875ffd83dbSDimitry Andric// Vector Single-Width Floating-Point Multiply/Divide Instructions 1188*6e75b2fbSDimitry Andricdefm VFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>; 1189*6e75b2fbSDimitry Andricdefm VFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>; 1190*6e75b2fbSDimitry Andricdefm VFRDIV_V : VRDIV_FV_F<"vfrdiv", 0b100001>; 11915ffd83dbSDimitry Andric 11925ffd83dbSDimitry Andric// Vector Widening Floating-Point Multiply 11935ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1194*6e75b2fbSDimitry Andricdefm VFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>; 11955ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 11965ffd83dbSDimitry Andric 11975ffd83dbSDimitry Andric// Vector Single-Width Floating-Point Fused Multiply-Add Instructions 1198*6e75b2fbSDimitry Andricdefm VFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>; 1199*6e75b2fbSDimitry Andricdefm VFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>; 1200*6e75b2fbSDimitry Andricdefm VFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>; 1201*6e75b2fbSDimitry Andricdefm VFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>; 1202*6e75b2fbSDimitry Andricdefm VFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>; 1203*6e75b2fbSDimitry Andricdefm VFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>; 1204*6e75b2fbSDimitry Andricdefm VFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>; 1205*6e75b2fbSDimitry Andricdefm VFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>; 12065ffd83dbSDimitry Andric 12075ffd83dbSDimitry Andric// Vector Widening Floating-Point Fused Multiply-Add Instructions 12085ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1209*6e75b2fbSDimitry Andricdefm VFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>; 1210*6e75b2fbSDimitry Andricdefm VFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>; 1211*6e75b2fbSDimitry Andricdefm VFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>; 1212*6e75b2fbSDimitry Andricdefm VFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>; 12135ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 12145ffd83dbSDimitry Andric 12155ffd83dbSDimitry Andric// Vector Floating-Point Square-Root Instruction 1216*6e75b2fbSDimitry Andricdefm VFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>; 1217*6e75b2fbSDimitry Andricdefm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>; 1218*6e75b2fbSDimitry Andricdefm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>; 12195ffd83dbSDimitry Andric 12205ffd83dbSDimitry Andric// Vector Floating-Point MIN/MAX Instructions 1221*6e75b2fbSDimitry Andricdefm VFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>; 1222*6e75b2fbSDimitry Andricdefm VFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>; 12235ffd83dbSDimitry Andric 12245ffd83dbSDimitry Andric// Vector Floating-Point Sign-Injection Instructions 1225*6e75b2fbSDimitry Andricdefm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>; 1226*6e75b2fbSDimitry Andricdefm VFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>; 1227*6e75b2fbSDimitry Andricdefm VFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>; 12285ffd83dbSDimitry Andric 1229e8d8bef9SDimitry Andricdef : InstAlias<"vfneg.v $vd, $vs$vm", 1230e8d8bef9SDimitry Andric (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; 1231fe6060f1SDimitry Andricdef : InstAlias<"vfabs.v $vd, $vs$vm", 1232fe6060f1SDimitry Andric (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; 1233e8d8bef9SDimitry Andric 12345ffd83dbSDimitry Andric// Vector Floating-Point Compare Instructions 1235e8d8bef9SDimitry Andriclet RVVConstraint = NoConstraint in { 1236*6e75b2fbSDimitry Andricdefm VMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>; 1237*6e75b2fbSDimitry Andricdefm VMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>; 1238*6e75b2fbSDimitry Andricdefm VMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>; 1239*6e75b2fbSDimitry Andricdefm VMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>; 1240*6e75b2fbSDimitry Andricdefm VMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>; 1241*6e75b2fbSDimitry Andricdefm VMFGE_V : VCMP_FV_F<"vmfge", 0b011111>; 1242e8d8bef9SDimitry Andric} // RVVConstraint = NoConstraint 12435ffd83dbSDimitry Andric 12445ffd83dbSDimitry Andricdef : InstAlias<"vmfgt.vv $vd, $va, $vb$vm", 1245e8d8bef9SDimitry Andric (VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 12465ffd83dbSDimitry Andricdef : InstAlias<"vmfge.vv $vd, $va, $vb$vm", 1247e8d8bef9SDimitry Andric (VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 12485ffd83dbSDimitry Andric 12495ffd83dbSDimitry Andric// Vector Floating-Point Classify Instruction 1250*6e75b2fbSDimitry Andricdefm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>; 12515ffd83dbSDimitry Andric 12525ffd83dbSDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 1253*6e75b2fbSDimitry Andric 12545ffd83dbSDimitry Andric// Vector Floating-Point Merge Instruction 1255*6e75b2fbSDimitry Andriclet vm = 0 in 1256e8d8bef9SDimitry Andricdef VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd), 1257e8d8bef9SDimitry Andric (ins VR:$vs2, FPR32:$rs1, VMV0:$v0), 1258*6e75b2fbSDimitry Andric "vfmerge.vfm", "$vd, $vs2, $rs1, v0">, 1259*6e75b2fbSDimitry Andric Sched<[WriteVFMergeV, ReadVFMergeV, ReadVFMergeF, ReadVMask]>; 12605ffd83dbSDimitry Andric 12615ffd83dbSDimitry Andric// Vector Floating-Point Move Instruction 1262e8d8bef9SDimitry Andriclet RVVConstraint = NoConstraint in 1263*6e75b2fbSDimitry Andriclet vm = 1, vs2 = 0 in 1264e8d8bef9SDimitry Andricdef VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd), 1265*6e75b2fbSDimitry Andric (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">, 1266*6e75b2fbSDimitry Andric Sched<[WriteVFMovV, ReadVFMovF]>; 1267*6e75b2fbSDimitry Andric 12685ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 12695ffd83dbSDimitry Andric 12705ffd83dbSDimitry Andric// Single-Width Floating-Point/Integer Type-Convert Instructions 1271*6e75b2fbSDimitry Andricdefm VFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>; 1272*6e75b2fbSDimitry Andricdefm VFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>; 1273*6e75b2fbSDimitry Andricdefm VFCVT_RTZ_XU_F_V : VCVTI_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>; 1274*6e75b2fbSDimitry Andricdefm VFCVT_RTZ_X_F_V : VCVTI_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>; 1275*6e75b2fbSDimitry Andricdefm VFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>; 1276*6e75b2fbSDimitry Andricdefm VFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>; 12775ffd83dbSDimitry Andric 12785ffd83dbSDimitry Andric// Widening Floating-Point/Integer Type-Convert Instructions 12795ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in { 1280*6e75b2fbSDimitry Andricdefm VFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>; 1281*6e75b2fbSDimitry Andricdefm VFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>; 1282*6e75b2fbSDimitry Andricdefm VFWCVT_RTZ_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>; 1283*6e75b2fbSDimitry Andricdefm VFWCVT_RTZ_X_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>; 1284*6e75b2fbSDimitry Andricdefm VFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>; 1285*6e75b2fbSDimitry Andricdefm VFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>; 1286*6e75b2fbSDimitry Andricdefm VFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>; 12875ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt 12885ffd83dbSDimitry Andric 12895ffd83dbSDimitry Andric// Narrowing Floating-Point/Integer Type-Convert Instructions 1290e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd" in { 1291*6e75b2fbSDimitry Andricdefm VFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>; 1292*6e75b2fbSDimitry Andricdefm VFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>; 1293*6e75b2fbSDimitry Andricdefm VFNCVT_RTZ_XU_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>; 1294*6e75b2fbSDimitry Andricdefm VFNCVT_RTZ_X_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>; 1295*6e75b2fbSDimitry Andricdefm VFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>; 1296*6e75b2fbSDimitry Andricdefm VFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>; 1297*6e75b2fbSDimitry Andricdefm VFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>; 1298*6e75b2fbSDimitry Andricdefm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>; 1299e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd" 1300e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV, HasStdExtF] 13015ffd83dbSDimitry Andric 1302e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV] in { 1303*6e75b2fbSDimitry Andric 13045ffd83dbSDimitry Andric// Vector Single-Width Integer Reduction Instructions 1305e8d8bef9SDimitry Andriclet RVVConstraint = NoConstraint in { 1306*6e75b2fbSDimitry Andricdefm VREDSUM : VRED_MV_V<"vredsum", 0b000000>; 1307*6e75b2fbSDimitry Andricdefm VREDMAXU : VRED_MV_V<"vredmaxu", 0b000110>; 1308*6e75b2fbSDimitry Andricdefm VREDMAX : VRED_MV_V<"vredmax", 0b000111>; 1309*6e75b2fbSDimitry Andricdefm VREDMINU : VRED_MV_V<"vredminu", 0b000100>; 1310*6e75b2fbSDimitry Andricdefm VREDMIN : VRED_MV_V<"vredmin", 0b000101>; 1311*6e75b2fbSDimitry Andricdefm VREDAND : VRED_MV_V<"vredand", 0b000001>; 1312*6e75b2fbSDimitry Andricdefm VREDOR : VRED_MV_V<"vredor", 0b000010>; 1313*6e75b2fbSDimitry Andricdefm VREDXOR : VRED_MV_V<"vredxor", 0b000011>; 1314e8d8bef9SDimitry Andric} // RVVConstraint = NoConstraint 13155ffd83dbSDimitry Andric 13165ffd83dbSDimitry Andric// Vector Widening Integer Reduction Instructions 1317e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 13185ffd83dbSDimitry Andric// Set earlyclobber for following instructions for second and mask operands. 13195ffd83dbSDimitry Andric// This has the downside that the earlyclobber constraint is too coarse and 13205ffd83dbSDimitry Andric// will impose unnecessary restrictions by not allowing the destination to 13215ffd83dbSDimitry Andric// overlap with the first (wide) operand. 1322*6e75b2fbSDimitry Andricdefm VWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>; 1323*6e75b2fbSDimitry Andricdefm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>; 1324e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1325*6e75b2fbSDimitry Andric 1326e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV] 13275ffd83dbSDimitry Andric 1328e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV, HasStdExtF] in { 13295ffd83dbSDimitry Andric// Vector Single-Width Floating-Point Reduction Instructions 1330e8d8bef9SDimitry Andriclet RVVConstraint = NoConstraint in { 1331*6e75b2fbSDimitry Andricdefm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>; 1332*6e75b2fbSDimitry Andricdefm VFREDSUM : VRED_FV_V<"vfredsum", 0b000001>; 1333*6e75b2fbSDimitry Andricdefm VFREDMAX : VRED_FV_V<"vfredmax", 0b000111>; 1334*6e75b2fbSDimitry Andricdefm VFREDMIN : VRED_FV_V<"vfredmin", 0b000101>; 1335e8d8bef9SDimitry Andric} // RVVConstraint = NoConstraint 13365ffd83dbSDimitry Andric 13375ffd83dbSDimitry Andric// Vector Widening Floating-Point Reduction Instructions 1338e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 13395ffd83dbSDimitry Andric// Set earlyclobber for following instructions for second and mask operands. 13405ffd83dbSDimitry Andric// This has the downside that the earlyclobber constraint is too coarse and 13415ffd83dbSDimitry Andric// will impose unnecessary restrictions by not allowing the destination to 13425ffd83dbSDimitry Andric// overlap with the first (wide) operand. 1343*6e75b2fbSDimitry Andricdefm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>; 1344*6e75b2fbSDimitry Andricdefm VFWREDSUM : VWRED_FV_V<"vfwredsum", 0b110001>; 1345e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1346e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV, HasStdExtF] 13475ffd83dbSDimitry Andric 1348e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV] in { 13495ffd83dbSDimitry Andric// Vector Mask-Register Logical Instructions 1350e8d8bef9SDimitry Andriclet RVVConstraint = NoConstraint in { 1351*6e75b2fbSDimitry Andricdefm VMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">; 1352*6e75b2fbSDimitry Andricdefm VMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">; 1353*6e75b2fbSDimitry Andricdefm VMANDNOT_M : VMALU_MV_Mask<"vmandnot", 0b011000, "m">; 1354*6e75b2fbSDimitry Andricdefm VMXOR_M : VMALU_MV_Mask<"vmxor", 0b011011, "m">; 1355*6e75b2fbSDimitry Andricdefm VMOR_M : VMALU_MV_Mask<"vmor", 0b011010, "m">; 1356*6e75b2fbSDimitry Andricdefm VMNOR_M : VMALU_MV_Mask<"vmnor", 0b011110, "m">; 1357*6e75b2fbSDimitry Andricdefm VMORNOT_M : VMALU_MV_Mask<"vmornot", 0b011100, "m">; 1358*6e75b2fbSDimitry Andricdefm VMXNOR_M : VMALU_MV_Mask<"vmxnor", 0b011111, "m">; 1359e8d8bef9SDimitry Andric} 13605ffd83dbSDimitry Andric 1361e8d8bef9SDimitry Andricdef : InstAlias<"vmmv.m $vd, $vs", 1362e8d8bef9SDimitry Andric (VMAND_MM VR:$vd, VR:$vs, VR:$vs)>; 13635ffd83dbSDimitry Andricdef : InstAlias<"vmclr.m $vd", 1364e8d8bef9SDimitry Andric (VMXOR_MM VR:$vd, VR:$vd, VR:$vd)>; 13655ffd83dbSDimitry Andricdef : InstAlias<"vmset.m $vd", 1366e8d8bef9SDimitry Andric (VMXNOR_MM VR:$vd, VR:$vd, VR:$vd)>; 13675ffd83dbSDimitry Andricdef : InstAlias<"vmnot.m $vd, $vs", 1368e8d8bef9SDimitry Andric (VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>; 13695ffd83dbSDimitry Andric 1370e8d8bef9SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0, 1371e8d8bef9SDimitry Andric RVVConstraint = NoConstraint in { 1372*6e75b2fbSDimitry Andric 13735ffd83dbSDimitry Andric// Vector mask population count vpopc 13745ffd83dbSDimitry Andricdef VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd), 1375e8d8bef9SDimitry Andric (ins VR:$vs2, VMaskOp:$vm), 1376*6e75b2fbSDimitry Andric "vpopc.m", "$vd, $vs2$vm">, 1377*6e75b2fbSDimitry Andric Sched<[WriteVMPopV, ReadVMPopV, ReadVMask]>; 13785ffd83dbSDimitry Andric 13795ffd83dbSDimitry Andric// vfirst find-first-set mask bit 13805ffd83dbSDimitry Andricdef VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd), 1381e8d8bef9SDimitry Andric (ins VR:$vs2, VMaskOp:$vm), 1382*6e75b2fbSDimitry Andric "vfirst.m", "$vd, $vs2$vm">, 1383*6e75b2fbSDimitry Andric Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMask]>; 1384*6e75b2fbSDimitry Andric 13855ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 13865ffd83dbSDimitry Andric 1387e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { 1388*6e75b2fbSDimitry Andric 13895ffd83dbSDimitry Andric// vmsbf.m set-before-first mask bit 1390*6e75b2fbSDimitry Andricdefm VMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010100, 0b00001>; 13915ffd83dbSDimitry Andric// vmsif.m set-including-first mask bit 1392*6e75b2fbSDimitry Andricdefm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>; 13935ffd83dbSDimitry Andric// vmsof.m set-only-first mask bit 1394*6e75b2fbSDimitry Andricdefm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>; 13955ffd83dbSDimitry Andric// Vector Iota Instruction 1396*6e75b2fbSDimitry Andricdefm VIOTA_M : VMIOT_MV_V<"viota.m", 0b010100, 0b10000>; 1397*6e75b2fbSDimitry Andric 13985ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota 13995ffd83dbSDimitry Andric 14005ffd83dbSDimitry Andric// Vector Element Index Instruction 14015ffd83dbSDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 1402*6e75b2fbSDimitry Andric 1403*6e75b2fbSDimitry Andriclet vs2 = 0 in 1404e8d8bef9SDimitry Andricdef VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), 1405*6e75b2fbSDimitry Andric (ins VMaskOp:$vm), "vid.v", "$vd$vm">, 1406*6e75b2fbSDimitry Andric Sched<[WriteVMIdxV, ReadVMask]>; 14075ffd83dbSDimitry Andric 14085ffd83dbSDimitry Andric// Integer Scalar Move Instructions 1409e8d8bef9SDimitry Andriclet vm = 1, RVVConstraint = NoConstraint in { 14105ffd83dbSDimitry Andricdef VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd), 1411*6e75b2fbSDimitry Andric (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">, 1412*6e75b2fbSDimitry Andric Sched<[WriteVIMovVX, ReadVIMovVX]>; 1413e8d8bef9SDimitry Andriclet Constraints = "$vd = $vd_wb" in 1414e8d8bef9SDimitry Andricdef VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb), 1415*6e75b2fbSDimitry Andric (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">, 1416*6e75b2fbSDimitry Andric Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>; 14175ffd83dbSDimitry Andric} 1418*6e75b2fbSDimitry Andric 14195ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1420*6e75b2fbSDimitry Andric 1421e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV] 14225ffd83dbSDimitry Andric 1423e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV, HasStdExtF] in { 1424*6e75b2fbSDimitry Andric 1425e8d8bef9SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1, 1426e8d8bef9SDimitry Andric RVVConstraint = NoConstraint in { 14275ffd83dbSDimitry Andric// Floating-Point Scalar Move Instructions 14285ffd83dbSDimitry Andricdef VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd), 1429*6e75b2fbSDimitry Andric (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">, 1430*6e75b2fbSDimitry Andric Sched<[WriteVFMovVF, ReadVFMovVF]>; 1431e8d8bef9SDimitry Andriclet Constraints = "$vd = $vd_wb" in 1432e8d8bef9SDimitry Andricdef VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb), 1433*6e75b2fbSDimitry Andric (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">, 1434*6e75b2fbSDimitry Andric Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>; 14355ffd83dbSDimitry Andric 14365ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 1437*6e75b2fbSDimitry Andric 1438e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV, HasStdExtF] 14395ffd83dbSDimitry Andric 1440e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV] in { 14415ffd83dbSDimitry Andric// Vector Slide Instructions 14425ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { 1443*6e75b2fbSDimitry Andricdefm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, uimm5>; 1444*6e75b2fbSDimitry Andricdefm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>; 14455ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp 1446*6e75b2fbSDimitry Andricdefm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, uimm5>; 1447*6e75b2fbSDimitry Andricdefm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>; 1448e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV] 14495ffd83dbSDimitry Andric 1450e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV, HasStdExtF] in { 1451e8d8bef9SDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { 1452*6e75b2fbSDimitry Andricdefm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>; 1453e8d8bef9SDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp 1454*6e75b2fbSDimitry Andricdefm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>; 1455e8d8bef9SDimitry Andric} // Predicates = [HasStdExtV, HasStdExtF] 1456e8d8bef9SDimitry Andric 1457e8d8bef9SDimitry Andriclet Predicates = [HasStdExtV] in { 14585ffd83dbSDimitry Andric// Vector Register Gather Instruction 14595ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { 1460*6e75b2fbSDimitry Andricdefm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100, uimm5>; 1461*6e75b2fbSDimitry Andricdef VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">, 1462*6e75b2fbSDimitry Andric Sched<[WriteVGatherV, ReadVGatherV, ReadVGatherV]>; 14635ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather 14645ffd83dbSDimitry Andric 14655ffd83dbSDimitry Andric// Vector Compress Instruction 14665ffd83dbSDimitry Andriclet Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in { 1467*6e75b2fbSDimitry Andricdefm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>; 14685ffd83dbSDimitry Andric} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress 14695ffd83dbSDimitry Andric 1470e8d8bef9SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0, 1471e8d8bef9SDimitry Andric RVVConstraint = NoConstraint in { 1472*6e75b2fbSDimitry Andricforeach n = [1, 2, 4, 8] in { 1473*6e75b2fbSDimitry Andric def VMV#n#R_V : RVInstV<0b100111, !add(n, -1), OPIVI, (outs VR:$vd), 1474*6e75b2fbSDimitry Andric (ins VR:$vs2), "vmv" # n # "r.v", "$vd, $vs2">, 1475*6e75b2fbSDimitry Andric VMVRSched<n> { 14765ffd83dbSDimitry Andric let Uses = []; 14775ffd83dbSDimitry Andric let vm = 1; 14785ffd83dbSDimitry Andric} 14795ffd83dbSDimitry Andric} 14805ffd83dbSDimitry Andric} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 14815ffd83dbSDimitry Andric} // Predicates = [HasStdExtV] 1482e8d8bef9SDimitry Andric 1483e8d8bef9SDimitry Andriclet Predicates = [HasStdExtZvlsseg] in { 1484e8d8bef9SDimitry Andric foreach nf=2-8 in { 1485e8d8bef9SDimitry Andric def VLSEG#nf#E8_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth8, "vlseg"#nf#"e8.v">; 1486e8d8bef9SDimitry Andric def VLSEG#nf#E16_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth16, "vlseg"#nf#"e16.v">; 1487e8d8bef9SDimitry Andric def VLSEG#nf#E32_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth32, "vlseg"#nf#"e32.v">; 1488e8d8bef9SDimitry Andric def VLSEG#nf#E64_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth64, "vlseg"#nf#"e64.v">; 1489e8d8bef9SDimitry Andric 1490e8d8bef9SDimitry Andric def VLSEG#nf#E8FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth8, "vlseg"#nf#"e8ff.v">; 1491e8d8bef9SDimitry Andric def VLSEG#nf#E16FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth16, "vlseg"#nf#"e16ff.v">; 1492e8d8bef9SDimitry Andric def VLSEG#nf#E32FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth32, "vlseg"#nf#"e32ff.v">; 1493e8d8bef9SDimitry Andric def VLSEG#nf#E64FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth64, "vlseg"#nf#"e64ff.v">; 1494e8d8bef9SDimitry Andric 1495e8d8bef9SDimitry Andric def VSSEG#nf#E8_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth8, "vsseg"#nf#"e8.v">; 1496e8d8bef9SDimitry Andric def VSSEG#nf#E16_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth16, "vsseg"#nf#"e16.v">; 1497e8d8bef9SDimitry Andric def VSSEG#nf#E32_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth32, "vsseg"#nf#"e32.v">; 1498e8d8bef9SDimitry Andric def VSSEG#nf#E64_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth64, "vsseg"#nf#"e64.v">; 1499e8d8bef9SDimitry Andric 1500e8d8bef9SDimitry Andric // Vector Strided Instructions 1501e8d8bef9SDimitry Andric def VLSSEG#nf#E8_V : VStridedSegmentLoad<!add(nf, -1), LSWidth8, "vlsseg"#nf#"e8.v">; 1502e8d8bef9SDimitry Andric def VLSSEG#nf#E16_V : VStridedSegmentLoad<!add(nf, -1), LSWidth16, "vlsseg"#nf#"e16.v">; 1503e8d8bef9SDimitry Andric def VLSSEG#nf#E32_V : VStridedSegmentLoad<!add(nf, -1), LSWidth32, "vlsseg"#nf#"e32.v">; 1504e8d8bef9SDimitry Andric def VLSSEG#nf#E64_V : VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">; 1505e8d8bef9SDimitry Andric 1506e8d8bef9SDimitry Andric def VSSSEG#nf#E8_V : VStridedSegmentStore<!add(nf, -1), LSWidth8, "vssseg"#nf#"e8.v">; 1507e8d8bef9SDimitry Andric def VSSSEG#nf#E16_V : VStridedSegmentStore<!add(nf, -1), LSWidth16, "vssseg"#nf#"e16.v">; 1508e8d8bef9SDimitry Andric def VSSSEG#nf#E32_V : VStridedSegmentStore<!add(nf, -1), LSWidth32, "vssseg"#nf#"e32.v">; 1509e8d8bef9SDimitry Andric def VSSSEG#nf#E64_V : VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">; 1510e8d8bef9SDimitry Andric 1511e8d8bef9SDimitry Andric // Vector Indexed Instructions 1512e8d8bef9SDimitry Andric def VLUXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1513e8d8bef9SDimitry Andric LSWidth8, "vluxseg"#nf#"ei8.v">; 1514e8d8bef9SDimitry Andric def VLUXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1515e8d8bef9SDimitry Andric LSWidth16, "vluxseg"#nf#"ei16.v">; 1516e8d8bef9SDimitry Andric def VLUXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1517e8d8bef9SDimitry Andric LSWidth32, "vluxseg"#nf#"ei32.v">; 1518e8d8bef9SDimitry Andric def VLUXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1519e8d8bef9SDimitry Andric LSWidth64, "vluxseg"#nf#"ei64.v">; 1520e8d8bef9SDimitry Andric 1521e8d8bef9SDimitry Andric def VLOXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1522e8d8bef9SDimitry Andric LSWidth8, "vloxseg"#nf#"ei8.v">; 1523e8d8bef9SDimitry Andric def VLOXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1524e8d8bef9SDimitry Andric LSWidth16, "vloxseg"#nf#"ei16.v">; 1525e8d8bef9SDimitry Andric def VLOXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1526e8d8bef9SDimitry Andric LSWidth32, "vloxseg"#nf#"ei32.v">; 1527e8d8bef9SDimitry Andric def VLOXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1528e8d8bef9SDimitry Andric LSWidth64, "vloxseg"#nf#"ei64.v">; 1529e8d8bef9SDimitry Andric 1530e8d8bef9SDimitry Andric def VSUXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1531e8d8bef9SDimitry Andric LSWidth8, "vsuxseg"#nf#"ei8.v">; 1532e8d8bef9SDimitry Andric def VSUXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1533e8d8bef9SDimitry Andric LSWidth16, "vsuxseg"#nf#"ei16.v">; 1534e8d8bef9SDimitry Andric def VSUXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1535e8d8bef9SDimitry Andric LSWidth32, "vsuxseg"#nf#"ei32.v">; 1536e8d8bef9SDimitry Andric def VSUXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1537e8d8bef9SDimitry Andric LSWidth64, "vsuxseg"#nf#"ei64.v">; 1538e8d8bef9SDimitry Andric 1539e8d8bef9SDimitry Andric def VSOXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1540e8d8bef9SDimitry Andric LSWidth8, "vsoxseg"#nf#"ei8.v">; 1541e8d8bef9SDimitry Andric def VSOXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1542e8d8bef9SDimitry Andric LSWidth16, "vsoxseg"#nf#"ei16.v">; 1543e8d8bef9SDimitry Andric def VSOXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1544e8d8bef9SDimitry Andric LSWidth32, "vsoxseg"#nf#"ei32.v">; 1545e8d8bef9SDimitry Andric def VSOXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1546e8d8bef9SDimitry Andric LSWidth64, "vsoxseg"#nf#"ei64.v">; 1547e8d8bef9SDimitry Andric } 1548e8d8bef9SDimitry Andric} // Predicates = [HasStdExtZvlsseg] 1549e8d8bef9SDimitry Andric 1550e8d8bef9SDimitry Andriclet Predicates = [HasStdExtZvamo, HasStdExtA] in { 1551e8d8bef9SDimitry Andric defm VAMOSWAPEI8 : VAMO<AMOOPVamoSwap, LSWidth8, "vamoswapei8.v">; 1552e8d8bef9SDimitry Andric defm VAMOSWAPEI16 : VAMO<AMOOPVamoSwap, LSWidth16, "vamoswapei16.v">; 1553e8d8bef9SDimitry Andric defm VAMOSWAPEI32 : VAMO<AMOOPVamoSwap, LSWidth32, "vamoswapei32.v">; 1554e8d8bef9SDimitry Andric 1555e8d8bef9SDimitry Andric defm VAMOADDEI8 : VAMO<AMOOPVamoAdd, LSWidth8, "vamoaddei8.v">; 1556e8d8bef9SDimitry Andric defm VAMOADDEI16 : VAMO<AMOOPVamoAdd, LSWidth16, "vamoaddei16.v">; 1557e8d8bef9SDimitry Andric defm VAMOADDEI32 : VAMO<AMOOPVamoAdd, LSWidth32, "vamoaddei32.v">; 1558e8d8bef9SDimitry Andric 1559e8d8bef9SDimitry Andric defm VAMOXOREI8 : VAMO<AMOOPVamoXor, LSWidth8, "vamoxorei8.v">; 1560e8d8bef9SDimitry Andric defm VAMOXOREI16 : VAMO<AMOOPVamoXor, LSWidth16, "vamoxorei16.v">; 1561e8d8bef9SDimitry Andric defm VAMOXOREI32 : VAMO<AMOOPVamoXor, LSWidth32, "vamoxorei32.v">; 1562e8d8bef9SDimitry Andric 1563e8d8bef9SDimitry Andric defm VAMOANDEI8 : VAMO<AMOOPVamoAnd, LSWidth8, "vamoandei8.v">; 1564e8d8bef9SDimitry Andric defm VAMOANDEI16 : VAMO<AMOOPVamoAnd, LSWidth16, "vamoandei16.v">; 1565e8d8bef9SDimitry Andric defm VAMOANDEI32 : VAMO<AMOOPVamoAnd, LSWidth32, "vamoandei32.v">; 1566e8d8bef9SDimitry Andric 1567e8d8bef9SDimitry Andric defm VAMOOREI8 : VAMO<AMOOPVamoOr, LSWidth8, "vamoorei8.v">; 1568e8d8bef9SDimitry Andric defm VAMOOREI16 : VAMO<AMOOPVamoOr, LSWidth16, "vamoorei16.v">; 1569e8d8bef9SDimitry Andric defm VAMOOREI32 : VAMO<AMOOPVamoOr, LSWidth32, "vamoorei32.v">; 1570e8d8bef9SDimitry Andric 1571e8d8bef9SDimitry Andric defm VAMOMINEI8 : VAMO<AMOOPVamoMin, LSWidth8, "vamominei8.v">; 1572e8d8bef9SDimitry Andric defm VAMOMINEI16 : VAMO<AMOOPVamoMin, LSWidth16, "vamominei16.v">; 1573e8d8bef9SDimitry Andric defm VAMOMINEI32 : VAMO<AMOOPVamoMin, LSWidth32, "vamominei32.v">; 1574e8d8bef9SDimitry Andric 1575e8d8bef9SDimitry Andric defm VAMOMAXEI8 : VAMO<AMOOPVamoMax, LSWidth8, "vamomaxei8.v">; 1576e8d8bef9SDimitry Andric defm VAMOMAXEI16 : VAMO<AMOOPVamoMax, LSWidth16, "vamomaxei16.v">; 1577e8d8bef9SDimitry Andric defm VAMOMAXEI32 : VAMO<AMOOPVamoMax, LSWidth32, "vamomaxei32.v">; 1578e8d8bef9SDimitry Andric 1579e8d8bef9SDimitry Andric defm VAMOMINUEI8 : VAMO<AMOOPVamoMinu, LSWidth8, "vamominuei8.v">; 1580e8d8bef9SDimitry Andric defm VAMOMINUEI16 : VAMO<AMOOPVamoMinu, LSWidth16, "vamominuei16.v">; 1581e8d8bef9SDimitry Andric defm VAMOMINUEI32 : VAMO<AMOOPVamoMinu, LSWidth32, "vamominuei32.v">; 1582e8d8bef9SDimitry Andric 1583e8d8bef9SDimitry Andric defm VAMOMAXUEI8 : VAMO<AMOOPVamoMaxu, LSWidth8, "vamomaxuei8.v">; 1584e8d8bef9SDimitry Andric defm VAMOMAXUEI16 : VAMO<AMOOPVamoMaxu, LSWidth16, "vamomaxuei16.v">; 1585e8d8bef9SDimitry Andric defm VAMOMAXUEI32 : VAMO<AMOOPVamoMaxu, LSWidth32, "vamomaxuei32.v">; 1586e8d8bef9SDimitry Andric} // Predicates = [HasStdExtZvamo, HasStdExtA] 1587e8d8bef9SDimitry Andric 1588e8d8bef9SDimitry Andriclet Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64] in { 1589e8d8bef9SDimitry Andric defm VAMOSWAPEI64 : VAMO<AMOOPVamoSwap, LSWidth64, "vamoswapei64.v">; 1590e8d8bef9SDimitry Andric defm VAMOADDEI64 : VAMO<AMOOPVamoAdd, LSWidth64, "vamoaddei64.v">; 1591e8d8bef9SDimitry Andric defm VAMOXOREI64 : VAMO<AMOOPVamoXor, LSWidth64, "vamoxorei64.v">; 1592e8d8bef9SDimitry Andric defm VAMOANDEI64 : VAMO<AMOOPVamoAnd, LSWidth64, "vamoandei64.v">; 1593e8d8bef9SDimitry Andric defm VAMOOREI64 : VAMO<AMOOPVamoOr, LSWidth64, "vamoorei64.v">; 1594e8d8bef9SDimitry Andric defm VAMOMINEI64 : VAMO<AMOOPVamoMin, LSWidth64, "vamominei64.v">; 1595e8d8bef9SDimitry Andric defm VAMOMAXEI64 : VAMO<AMOOPVamoMax, LSWidth64, "vamomaxei64.v">; 1596e8d8bef9SDimitry Andric defm VAMOMINUEI64 : VAMO<AMOOPVamoMinu, LSWidth64, "vamominuei64.v">; 1597e8d8bef9SDimitry Andric defm VAMOMAXUEI64 : VAMO<AMOOPVamoMaxu, LSWidth64, "vamomaxuei64.v">; 1598e8d8bef9SDimitry Andric} // Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64] 1599e8d8bef9SDimitry Andric 1600e8d8bef9SDimitry Andricinclude "RISCVInstrInfoVPseudos.td" 1601