1e8d8bef9SDimitry Andric//===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===// 2e8d8bef9SDimitry Andric// 3e8d8bef9SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4e8d8bef9SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5e8d8bef9SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6e8d8bef9SDimitry Andric// 7e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 8e8d8bef9SDimitry Andric/// 9e8d8bef9SDimitry Andric/// This file contains the required infrastructure to support code generation 1081ad6265SDimitry Andric/// for the standard 'V' (Vector) extension, version 1.0. 11e8d8bef9SDimitry Andric/// 12e8d8bef9SDimitry Andric/// This file is included from RISCVInstrInfoV.td 13e8d8bef9SDimitry Andric/// 1406c3fb27SDimitry Andric/// Overview of our vector instruction pseudos. Many of the instructions 1506c3fb27SDimitry Andric/// have behavior which depends on the value of VTYPE. Several core aspects of 1606c3fb27SDimitry Andric/// the compiler - e.g. register allocation - depend on fields in this 1706c3fb27SDimitry Andric/// configuration register. The details of which fields matter differ by the 1806c3fb27SDimitry Andric/// specific instruction, but the common dimensions are: 1906c3fb27SDimitry Andric/// 2006c3fb27SDimitry Andric/// LMUL/EMUL - Most instructions can write to differently sized register groups 2106c3fb27SDimitry Andric/// depending on LMUL. 2206c3fb27SDimitry Andric/// 2306c3fb27SDimitry Andric/// Masked vs Unmasked - Many instructions which allow a mask disallow register 2406c3fb27SDimitry Andric/// overlap. As a result, masked vs unmasked require different register 2506c3fb27SDimitry Andric/// allocation constraints. 2606c3fb27SDimitry Andric/// 2706c3fb27SDimitry Andric/// Policy - For each of mask and tail policy, there are three options: 2806c3fb27SDimitry Andric/// * "Undisturbed" - As defined in the specification, required to preserve the 2906c3fb27SDimitry Andric/// exact bit pattern of inactive lanes. 3006c3fb27SDimitry Andric/// * "Agnostic" - As defined in the specification, required to either preserve 3106c3fb27SDimitry Andric/// the exact bit pattern of inactive lanes, or produce the bit pattern -1 for 3206c3fb27SDimitry Andric/// those lanes. Note that each lane can make this choice independently. 3306c3fb27SDimitry Andric/// Instructions which produce masks (and only those instructions) also have the 3406c3fb27SDimitry Andric/// option of producing a result as-if VL had been VLMAX. 3506c3fb27SDimitry Andric/// * "Undefined" - The bit pattern of the inactive lanes is unspecified, and 3606c3fb27SDimitry Andric/// can be changed without impacting the semantics of the program. Note that 3706c3fb27SDimitry Andric/// this concept does not exist in the specification, and requires source 3806c3fb27SDimitry Andric/// knowledge to be preserved. 3906c3fb27SDimitry Andric/// 4006c3fb27SDimitry Andric/// SEW - Some instructions have semantics which depend on SEW. This is 4106c3fb27SDimitry Andric/// relatively rare, and mostly impacts scheduling and cost estimation. 4206c3fb27SDimitry Andric/// 4306c3fb27SDimitry Andric/// We have two techniques we use to represent the impact of these fields: 4406c3fb27SDimitry Andric/// * For fields which don't impact register classes, we largely use 4506c3fb27SDimitry Andric/// dummy operands on the pseudo instructions which convey information 4606c3fb27SDimitry Andric/// about the value of VTYPE. 4706c3fb27SDimitry Andric/// * For fields which do impact register classes (and a few bits of 4806c3fb27SDimitry Andric/// legacy - see policy discussion below), we define a family of pseudo 4906c3fb27SDimitry Andric/// instructions for each actual instruction. Said differently, we encode 5006c3fb27SDimitry Andric/// each of the preceding fields which are relevant for a given instruction 5106c3fb27SDimitry Andric/// in the opcode space. 5206c3fb27SDimitry Andric/// 5306c3fb27SDimitry Andric/// Currently, the policy is represented via the following instrinsic families: 5406c3fb27SDimitry Andric/// * _MASK - Can represent all three policy states for both tail and mask. If 555f757f3fSDimitry Andric/// passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined". 565f757f3fSDimitry Andric/// Otherwise, policy operand and tablegen flags drive the interpretation. 575f757f3fSDimitry Andric/// (If policy operand is not present - there are a couple, though we're 585f757f3fSDimitry Andric/// rapidly removing them - a non-undefined policy defaults to "tail 595f757f3fSDimitry Andric/// agnostic", and "mask undisturbed". Since this is the only variant with 605f757f3fSDimitry Andric/// a mask, all other variants are "mask undefined". 6106c3fb27SDimitry Andric/// * Unsuffixed w/ both passthrough and policy operand. Can represent all 625f757f3fSDimitry Andric/// three policy states. If passthrough is IMPLICIT_DEF (or NoReg), then 635f757f3fSDimitry Andric/// represents "undefined". Otherwise, policy operand and tablegen flags 645f757f3fSDimitry Andric/// drive the interpretation. 6506c3fb27SDimitry Andric/// * Unsuffixed w/o passthrough or policy operand -- Does not have a 6606c3fb27SDimitry Andric/// passthrough operand, and thus represents the "undefined" state. Note 6706c3fb27SDimitry Andric/// that terminology in code frequently refers to these as "TA" which is 6806c3fb27SDimitry Andric/// confusing. We're in the process of migrating away from this 6906c3fb27SDimitry Andric/// representation. 7006c3fb27SDimitry Andric/// * _TU w/o policy operand -- Has a passthrough operand, and always 7106c3fb27SDimitry Andric/// represents the tail undisturbed state. 7206c3fb27SDimitry Andric/// * _TU w/policy operand - Can represent all three policy states. If 735f757f3fSDimitry Andric/// passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined". 745f757f3fSDimitry Andric/// Otherwise, policy operand and tablegen flags drive the interpretation. 7506c3fb27SDimitry Andric/// 76e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 77e8d8bef9SDimitry Andric 78e8d8bef9SDimitry Andricdef riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", 79e8d8bef9SDimitry Andric SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>, 80e8d8bef9SDimitry Andric SDTCisInt<1>]>>; 81e8d8bef9SDimitry Andricdef riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", 82e8d8bef9SDimitry Andric SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; 83e8d8bef9SDimitry Andric 845f757f3fSDimitry Andric// Operand that is allowed to be a register other than X0, a 5 bit unsigned 855f757f3fSDimitry Andric// immediate, or -1. -1 means VLMAX. This allows us to pick between VSETIVLI and 865f757f3fSDimitry Andric// VSETVLI opcodes using the same pseudo instructions. 87349cc55cSDimitry Andricdef AVL : RegisterOperand<GPRNoX0> { 88fe6060f1SDimitry Andric let OperandNamespace = "RISCVOp"; 89fe6060f1SDimitry Andric let OperandType = "OPERAND_AVL"; 90fe6060f1SDimitry Andric} 91e8d8bef9SDimitry Andric 92e8d8bef9SDimitry Andric// X0 has special meaning for vsetvl/vsetvli. 93e8d8bef9SDimitry Andric// rd | rs1 | AVL value | Effect on vl 94e8d8bef9SDimitry Andric//-------------------------------------------------------------- 95e8d8bef9SDimitry Andric// !X0 | X0 | VLMAX | Set vl to VLMAX 96e8d8bef9SDimitry Andric// X0 | X0 | Value in vl | Keep current vl, just change vtype. 97d409305fSDimitry Andricdef VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">; 98e8d8bef9SDimitry Andric 99e8d8bef9SDimitry Andricdef DecImm : SDNodeXForm<imm, [{ 100e8d8bef9SDimitry Andric return CurDAG->getTargetConstant(N->getSExtValue() - 1, SDLoc(N), 101e8d8bef9SDimitry Andric N->getValueType(0)); 102e8d8bef9SDimitry Andric}]>; 103e8d8bef9SDimitry Andric 104349cc55cSDimitry Andricdefvar TAIL_AGNOSTIC = 1; 10506c3fb27SDimitry Andricdefvar TU_MU = 0; 106bdd1243dSDimitry Andricdefvar TA_MA = 3; 107349cc55cSDimitry Andric 108e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 109e8d8bef9SDimitry Andric// Utilities. 110e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 111e8d8bef9SDimitry Andric 11281ad6265SDimitry Andricclass PseudoToVInst<string PseudoInst> { 11306c3fb27SDimitry Andric defvar AffixSubsts = [["Pseudo", ""], 11406c3fb27SDimitry Andric ["_E64", ""], 11506c3fb27SDimitry Andric ["_E32", ""], 11606c3fb27SDimitry Andric ["_E16", ""], 11706c3fb27SDimitry Andric ["_E8", ""], 1185f757f3fSDimitry Andric ["FPR64", "F"], 1195f757f3fSDimitry Andric ["FPR32", "F"], 1205f757f3fSDimitry Andric ["FPR16", "F"], 12106c3fb27SDimitry Andric ["_TIED", ""], 12206c3fb27SDimitry Andric ["_MASK", ""], 12306c3fb27SDimitry Andric ["_B64", ""], 12406c3fb27SDimitry Andric ["_B32", ""], 12506c3fb27SDimitry Andric ["_B16", ""], 12606c3fb27SDimitry Andric ["_B8", ""], 12706c3fb27SDimitry Andric ["_B4", ""], 12806c3fb27SDimitry Andric ["_B2", ""], 12906c3fb27SDimitry Andric ["_B1", ""], 13006c3fb27SDimitry Andric ["_MF8", ""], 13106c3fb27SDimitry Andric ["_MF4", ""], 13206c3fb27SDimitry Andric ["_MF2", ""], 13306c3fb27SDimitry Andric ["_M1", ""], 13406c3fb27SDimitry Andric ["_M2", ""], 13506c3fb27SDimitry Andric ["_M4", ""], 13606c3fb27SDimitry Andric ["_M8", ""], 1375f757f3fSDimitry Andric ["_SE", ""], 1385f757f3fSDimitry Andric ["_RM", ""] 13906c3fb27SDimitry Andric ]; 14006c3fb27SDimitry Andric string VInst = !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst, 14106c3fb27SDimitry Andric !subst(AffixSubst[0], AffixSubst[1], Acc)); 14281ad6265SDimitry Andric} 14381ad6265SDimitry Andric 144e8d8bef9SDimitry Andric// This class describes information associated to the LMUL. 145fe6060f1SDimitry Andricclass LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass, 146e8d8bef9SDimitry Andric VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> { 147e8d8bef9SDimitry Andric bits<3> value = lmul; // This is encoded as the vlmul field of vtype. 148e8d8bef9SDimitry Andric VReg vrclass = regclass; 149e8d8bef9SDimitry Andric VReg wvrclass = wregclass; 150e8d8bef9SDimitry Andric VReg f8vrclass = f8regclass; 151e8d8bef9SDimitry Andric VReg f4vrclass = f4regclass; 152e8d8bef9SDimitry Andric VReg f2vrclass = f2regclass; 153e8d8bef9SDimitry Andric string MX = mx; 154fe6060f1SDimitry Andric int octuple = oct; 155e8d8bef9SDimitry Andric} 156e8d8bef9SDimitry Andric 157e8d8bef9SDimitry Andric// Associate LMUL with tablegen records of register classes. 158fe6060f1SDimitry Andricdef V_M1 : LMULInfo<0b000, 8, VR, VRM2, VR, VR, VR, "M1">; 159fe6060f1SDimitry Andricdef V_M2 : LMULInfo<0b001, 16, VRM2, VRM4, VR, VR, VR, "M2">; 160fe6060f1SDimitry Andricdef V_M4 : LMULInfo<0b010, 32, VRM4, VRM8, VRM2, VR, VR, "M4">; 161fe6060f1SDimitry Andricdef V_M8 : LMULInfo<0b011, 64, VRM8,/*NoVReg*/VR, VRM4, VRM2, VR, "M8">; 162e8d8bef9SDimitry Andric 163fe6060f1SDimitry Andricdef V_MF8 : LMULInfo<0b101, 1, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF8">; 164fe6060f1SDimitry Andricdef V_MF4 : LMULInfo<0b110, 2, VR, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF4">; 165fe6060f1SDimitry Andricdef V_MF2 : LMULInfo<0b111, 4, VR, VR, VR, VR,/*NoVReg*/VR, "MF2">; 166e8d8bef9SDimitry Andric 167e8d8bef9SDimitry Andric// Used to iterate over all possible LMULs. 16804eeddc0SDimitry Andricdefvar MxList = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8]; 16904eeddc0SDimitry Andric// For floating point which don't need MF8. 17004eeddc0SDimitry Andricdefvar MxListF = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8]; 17104eeddc0SDimitry Andric 172fe6060f1SDimitry Andric// Used for widening and narrowing instructions as it doesn't contain M8. 17304eeddc0SDimitry Andricdefvar MxListW = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4]; 17406c3fb27SDimitry Andric// Used for widening reductions. It can contain M8 because wider operands are 17506c3fb27SDimitry Andric// scalar operands. 17606c3fb27SDimitry Andricdefvar MxListWRed = MxList; 17704eeddc0SDimitry Andric// For floating point which don't need MF8. 17804eeddc0SDimitry Andricdefvar MxListFW = [V_MF4, V_MF2, V_M1, V_M2, V_M4]; 17906c3fb27SDimitry Andric// For widening floating-point Reduction as it doesn't contain MF8. It can 18006c3fb27SDimitry Andric// contain M8 because wider operands are scalar operands. 18106c3fb27SDimitry Andricdefvar MxListFWRed = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8]; 18204eeddc0SDimitry Andric 183fe6060f1SDimitry Andric// Use for zext/sext.vf2 18404eeddc0SDimitry Andricdefvar MxListVF2 = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8]; 18504eeddc0SDimitry Andric 1865f757f3fSDimitry Andric// Use for zext/sext.vf4 and vector crypto instructions 18704eeddc0SDimitry Andricdefvar MxListVF4 = [V_MF2, V_M1, V_M2, V_M4, V_M8]; 18804eeddc0SDimitry Andric 189fe6060f1SDimitry Andric// Use for zext/sext.vf8 19004eeddc0SDimitry Andricdefvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8]; 191e8d8bef9SDimitry Andric 192e8d8bef9SDimitry Andricclass MxSet<int eew> { 193e8d8bef9SDimitry Andric list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], 194e8d8bef9SDimitry Andric !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], 195e8d8bef9SDimitry Andric !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8], 196e8d8bef9SDimitry Andric !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]); 197e8d8bef9SDimitry Andric} 198e8d8bef9SDimitry Andric 19906c3fb27SDimitry Andricclass FPR_Info<int sew> { 20006c3fb27SDimitry Andric RegisterClass fprclass = !cast<RegisterClass>("FPR" # sew); 2015f757f3fSDimitry Andric string FX = "FPR" # sew; 20206c3fb27SDimitry Andric int SEW = sew; 20306c3fb27SDimitry Andric list<LMULInfo> MxList = MxSet<sew>.m; 20406c3fb27SDimitry Andric list<LMULInfo> MxListFW = !if(!eq(sew, 64), [], !listremove(MxList, [V_M8])); 20504eeddc0SDimitry Andric} 20604eeddc0SDimitry Andric 20706c3fb27SDimitry Andricdef SCALAR_F16 : FPR_Info<16>; 20806c3fb27SDimitry Andricdef SCALAR_F32 : FPR_Info<32>; 20906c3fb27SDimitry Andricdef SCALAR_F64 : FPR_Info<64>; 21004eeddc0SDimitry Andric 2115f757f3fSDimitry Andric// BF16 uses the same register class as F16. 2125f757f3fSDimitry Andricdef SCALAR_BF16 : FPR_Info<16>; 2135f757f3fSDimitry Andric 21404eeddc0SDimitry Andricdefvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64]; 21504eeddc0SDimitry Andric 21604eeddc0SDimitry Andric// Used for widening instructions. It excludes F64. 21704eeddc0SDimitry Andricdefvar FPListW = [SCALAR_F16, SCALAR_F32]; 21804eeddc0SDimitry Andric 2195f757f3fSDimitry Andric// Used for widening bf16 instructions. 2205f757f3fSDimitry Andricdefvar BFPListW = [SCALAR_BF16]; 2215f757f3fSDimitry Andric 222e8d8bef9SDimitry Andricclass NFSet<LMULInfo m> { 2235f757f3fSDimitry Andric defvar lmul = !shl(1, m.value); 2245f757f3fSDimitry Andric list<int> L = NFList<lmul>.L; 225e8d8bef9SDimitry Andric} 226e8d8bef9SDimitry Andric 227e8d8bef9SDimitry Andricclass octuple_to_str<int octuple> { 22806c3fb27SDimitry Andric string ret = !cond(!eq(octuple, 1): "MF8", 22906c3fb27SDimitry Andric !eq(octuple, 2): "MF4", 23006c3fb27SDimitry Andric !eq(octuple, 4): "MF2", 23106c3fb27SDimitry Andric !eq(octuple, 8): "M1", 23206c3fb27SDimitry Andric !eq(octuple, 16): "M2", 23306c3fb27SDimitry Andric !eq(octuple, 32): "M4", 23406c3fb27SDimitry Andric !eq(octuple, 64): "M8"); 235e8d8bef9SDimitry Andric} 236e8d8bef9SDimitry Andric 237fe6060f1SDimitry Andricdef VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>; 238fe6060f1SDimitry Andric 239e8d8bef9SDimitry Andric// Output pattern for X0 used to represent VLMAX in the pseudo instructions. 240349cc55cSDimitry Andric// We can't use X0 register becuase the AVL operands use GPRNoX0. 241349cc55cSDimitry Andric// This must be kept in sync with RISCV::VLMaxSentinel. 242349cc55cSDimitry Andricdef VLMax : OutPatFrag<(ops), (XLenVT -1)>; 243e8d8bef9SDimitry Andric 2445f757f3fSDimitry Andricdef SelectFPImm : ComplexPattern<fAny, 1, "selectFPImm", [], [], 1>; 2455f757f3fSDimitry Andric 246e8d8bef9SDimitry Andric// List of EEW. 247e8d8bef9SDimitry Andricdefvar EEWList = [8, 16, 32, 64]; 248e8d8bef9SDimitry Andric 249e8d8bef9SDimitry Andricclass SegRegClass<LMULInfo m, int nf> { 250e8d8bef9SDimitry Andric VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX, 251e8d8bef9SDimitry Andric !eq(m.value, V_MF4.value): V_M1.MX, 252e8d8bef9SDimitry Andric !eq(m.value, V_MF2.value): V_M1.MX, 253e8d8bef9SDimitry Andric true: m.MX)); 254e8d8bef9SDimitry Andric} 255e8d8bef9SDimitry Andric 256e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 257e8d8bef9SDimitry Andric// Vector register and vector group type information. 258e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 259e8d8bef9SDimitry Andric 260647cbc5dSDimitry Andricclass VTypeInfo<ValueType Vec, ValueType Mas, int Sew, LMULInfo M, 26106c3fb27SDimitry Andric ValueType Scal = XLenVT, RegisterClass ScalarReg = GPR> { 262e8d8bef9SDimitry Andric ValueType Vector = Vec; 263e8d8bef9SDimitry Andric ValueType Mask = Mas; 264e8d8bef9SDimitry Andric int SEW = Sew; 26506c3fb27SDimitry Andric int Log2SEW = !logtwo(Sew); 266647cbc5dSDimitry Andric VReg RegClass = M.vrclass; 267e8d8bef9SDimitry Andric LMULInfo LMul = M; 268e8d8bef9SDimitry Andric ValueType Scalar = Scal; 269e8d8bef9SDimitry Andric RegisterClass ScalarRegClass = ScalarReg; 270e8d8bef9SDimitry Andric // The pattern fragment which produces the AVL operand, representing the 271e8d8bef9SDimitry Andric // "natural" vector length for this type. For scalable vectors this is VLMax. 272e8d8bef9SDimitry Andric OutPatFrag AVL = VLMax; 273e8d8bef9SDimitry Andric 274e8d8bef9SDimitry Andric string ScalarSuffix = !cond(!eq(Scal, XLenVT) : "X", 2755f757f3fSDimitry Andric !eq(Scal, f16) : "FPR16", 2765f757f3fSDimitry Andric !eq(Scal, bf16) : "FPR16", 2775f757f3fSDimitry Andric !eq(Scal, f32) : "FPR32", 2785f757f3fSDimitry Andric !eq(Scal, f64) : "FPR64"); 279e8d8bef9SDimitry Andric} 280e8d8bef9SDimitry Andric 281e8d8bef9SDimitry Andricclass GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew, 282647cbc5dSDimitry Andric LMULInfo M, ValueType Scal = XLenVT, 283e8d8bef9SDimitry Andric RegisterClass ScalarReg = GPR> 284647cbc5dSDimitry Andric : VTypeInfo<Vec, Mas, Sew, M, Scal, ScalarReg> { 285e8d8bef9SDimitry Andric ValueType VectorM1 = VecM1; 286e8d8bef9SDimitry Andric} 287e8d8bef9SDimitry Andric 288e8d8bef9SDimitry Andricdefset list<VTypeInfo> AllVectors = { 289e8d8bef9SDimitry Andric defset list<VTypeInfo> AllIntegerVectors = { 290e8d8bef9SDimitry Andric defset list<VTypeInfo> NoGroupIntegerVectors = { 291fe6060f1SDimitry Andric defset list<VTypeInfo> FractionalGroupIntegerVectors = { 292647cbc5dSDimitry Andric def VI8MF8: VTypeInfo<vint8mf8_t, vbool64_t, 8, V_MF8>; 293647cbc5dSDimitry Andric def VI8MF4: VTypeInfo<vint8mf4_t, vbool32_t, 8, V_MF4>; 294647cbc5dSDimitry Andric def VI8MF2: VTypeInfo<vint8mf2_t, vbool16_t, 8, V_MF2>; 295647cbc5dSDimitry Andric def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, V_MF4>; 296647cbc5dSDimitry Andric def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, V_MF2>; 297647cbc5dSDimitry Andric def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, V_MF2>; 298fe6060f1SDimitry Andric } 299647cbc5dSDimitry Andric def VI8M1: VTypeInfo<vint8m1_t, vbool8_t, 8, V_M1>; 300647cbc5dSDimitry Andric def VI16M1: VTypeInfo<vint16m1_t, vbool16_t, 16, V_M1>; 301647cbc5dSDimitry Andric def VI32M1: VTypeInfo<vint32m1_t, vbool32_t, 32, V_M1>; 302647cbc5dSDimitry Andric def VI64M1: VTypeInfo<vint64m1_t, vbool64_t, 64, V_M1>; 303e8d8bef9SDimitry Andric } 304e8d8bef9SDimitry Andric defset list<GroupVTypeInfo> GroupIntegerVectors = { 305647cbc5dSDimitry Andric def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, V_M2>; 306647cbc5dSDimitry Andric def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, V_M4>; 307647cbc5dSDimitry Andric def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, V_M8>; 308e8d8bef9SDimitry Andric 309647cbc5dSDimitry Andric def VI16M2: GroupVTypeInfo<vint16m2_t, vint16m1_t, vbool8_t, 16, V_M2>; 310647cbc5dSDimitry Andric def VI16M4: GroupVTypeInfo<vint16m4_t, vint16m1_t, vbool4_t, 16, V_M4>; 311647cbc5dSDimitry Andric def VI16M8: GroupVTypeInfo<vint16m8_t, vint16m1_t, vbool2_t, 16, V_M8>; 312e8d8bef9SDimitry Andric 313647cbc5dSDimitry Andric def VI32M2: GroupVTypeInfo<vint32m2_t, vint32m1_t, vbool16_t, 32, V_M2>; 314647cbc5dSDimitry Andric def VI32M4: GroupVTypeInfo<vint32m4_t, vint32m1_t, vbool8_t, 32, V_M4>; 315647cbc5dSDimitry Andric def VI32M8: GroupVTypeInfo<vint32m8_t, vint32m1_t, vbool4_t, 32, V_M8>; 316e8d8bef9SDimitry Andric 317647cbc5dSDimitry Andric def VI64M2: GroupVTypeInfo<vint64m2_t, vint64m1_t, vbool32_t, 64, V_M2>; 318647cbc5dSDimitry Andric def VI64M4: GroupVTypeInfo<vint64m4_t, vint64m1_t, vbool16_t, 64, V_M4>; 319647cbc5dSDimitry Andric def VI64M8: GroupVTypeInfo<vint64m8_t, vint64m1_t, vbool8_t, 64, V_M8>; 320e8d8bef9SDimitry Andric } 321e8d8bef9SDimitry Andric } 322e8d8bef9SDimitry Andric 323e8d8bef9SDimitry Andric defset list<VTypeInfo> AllFloatVectors = { 324e8d8bef9SDimitry Andric defset list<VTypeInfo> NoGroupFloatVectors = { 325fe6060f1SDimitry Andric defset list<VTypeInfo> FractionalGroupFloatVectors = { 326647cbc5dSDimitry Andric def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, V_MF4, f16, FPR16>; 327647cbc5dSDimitry Andric def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, V_MF2, f16, FPR16>; 328647cbc5dSDimitry Andric def VF32MF2: VTypeInfo<vfloat32mf2_t, vbool64_t, 32, V_MF2, f32, FPR32>; 329fe6060f1SDimitry Andric } 330647cbc5dSDimitry Andric def VF16M1: VTypeInfo<vfloat16m1_t, vbool16_t, 16, V_M1, f16, FPR16>; 331647cbc5dSDimitry Andric def VF32M1: VTypeInfo<vfloat32m1_t, vbool32_t, 32, V_M1, f32, FPR32>; 332647cbc5dSDimitry Andric def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, V_M1, f64, FPR64>; 333e8d8bef9SDimitry Andric } 334e8d8bef9SDimitry Andric 335e8d8bef9SDimitry Andric defset list<GroupVTypeInfo> GroupFloatVectors = { 336e8d8bef9SDimitry Andric def VF16M2: GroupVTypeInfo<vfloat16m2_t, vfloat16m1_t, vbool8_t, 16, 337647cbc5dSDimitry Andric V_M2, f16, FPR16>; 338e8d8bef9SDimitry Andric def VF16M4: GroupVTypeInfo<vfloat16m4_t, vfloat16m1_t, vbool4_t, 16, 339647cbc5dSDimitry Andric V_M4, f16, FPR16>; 340e8d8bef9SDimitry Andric def VF16M8: GroupVTypeInfo<vfloat16m8_t, vfloat16m1_t, vbool2_t, 16, 341647cbc5dSDimitry Andric V_M8, f16, FPR16>; 342e8d8bef9SDimitry Andric 343e8d8bef9SDimitry Andric def VF32M2: GroupVTypeInfo<vfloat32m2_t, vfloat32m1_t, vbool16_t, 32, 344647cbc5dSDimitry Andric V_M2, f32, FPR32>; 345e8d8bef9SDimitry Andric def VF32M4: GroupVTypeInfo<vfloat32m4_t, vfloat32m1_t, vbool8_t, 32, 346647cbc5dSDimitry Andric V_M4, f32, FPR32>; 347e8d8bef9SDimitry Andric def VF32M8: GroupVTypeInfo<vfloat32m8_t, vfloat32m1_t, vbool4_t, 32, 348647cbc5dSDimitry Andric V_M8, f32, FPR32>; 349e8d8bef9SDimitry Andric 350e8d8bef9SDimitry Andric def VF64M2: GroupVTypeInfo<vfloat64m2_t, vfloat64m1_t, vbool32_t, 64, 351647cbc5dSDimitry Andric V_M2, f64, FPR64>; 352e8d8bef9SDimitry Andric def VF64M4: GroupVTypeInfo<vfloat64m4_t, vfloat64m1_t, vbool16_t, 64, 353647cbc5dSDimitry Andric V_M4, f64, FPR64>; 354e8d8bef9SDimitry Andric def VF64M8: GroupVTypeInfo<vfloat64m8_t, vfloat64m1_t, vbool8_t, 64, 355647cbc5dSDimitry Andric V_M8, f64, FPR64>; 356e8d8bef9SDimitry Andric } 357e8d8bef9SDimitry Andric } 358e8d8bef9SDimitry Andric} 359e8d8bef9SDimitry Andric 3605f757f3fSDimitry Andricdefset list<VTypeInfo> AllBFloatVectors = { 3615f757f3fSDimitry Andric defset list<VTypeInfo> NoGroupBFloatVectors = { 3625f757f3fSDimitry Andric defset list<VTypeInfo> FractionalGroupBFloatVectors = { 363647cbc5dSDimitry Andric def VBF16MF4: VTypeInfo<vbfloat16mf4_t, vbool64_t, 16, V_MF4, bf16, FPR16>; 364647cbc5dSDimitry Andric def VBF16MF2: VTypeInfo<vbfloat16mf2_t, vbool32_t, 16, V_MF2, bf16, FPR16>; 3655f757f3fSDimitry Andric } 366647cbc5dSDimitry Andric def VBF16M1: VTypeInfo<vbfloat16m1_t, vbool16_t, 16, V_M1, bf16, FPR16>; 3675f757f3fSDimitry Andric } 3685f757f3fSDimitry Andric 3695f757f3fSDimitry Andric defset list<GroupVTypeInfo> GroupBFloatVectors = { 3705f757f3fSDimitry Andric def VBF16M2: GroupVTypeInfo<vbfloat16m2_t, vbfloat16m1_t, vbool8_t, 16, 371647cbc5dSDimitry Andric V_M2, bf16, FPR16>; 3725f757f3fSDimitry Andric def VBF16M4: GroupVTypeInfo<vbfloat16m4_t, vbfloat16m1_t, vbool4_t, 16, 373647cbc5dSDimitry Andric V_M4, bf16, FPR16>; 3745f757f3fSDimitry Andric def VBF16M8: GroupVTypeInfo<vbfloat16m8_t, vbfloat16m1_t, vbool2_t, 16, 375647cbc5dSDimitry Andric V_M8, bf16, FPR16>; 3765f757f3fSDimitry Andric } 3775f757f3fSDimitry Andric} 3785f757f3fSDimitry Andric 379e8d8bef9SDimitry Andric// This functor is used to obtain the int vector type that has the same SEW and 380e8d8bef9SDimitry Andric// multiplier as the input parameter type 38106c3fb27SDimitry Andricclass GetIntVTypeInfo<VTypeInfo vti> { 382e8d8bef9SDimitry Andric // Equivalent integer vector type. Eg. 383e8d8bef9SDimitry Andric // VI8M1 → VI8M1 (identity) 384e8d8bef9SDimitry Andric // VF64M4 → VI64M4 385e8d8bef9SDimitry Andric VTypeInfo Vti = !cast<VTypeInfo>(!subst("VF", "VI", !cast<string>(vti))); 386e8d8bef9SDimitry Andric} 387e8d8bef9SDimitry Andric 388e8d8bef9SDimitry Andricclass MTypeInfo<ValueType Mas, LMULInfo M, string Bx> { 389e8d8bef9SDimitry Andric ValueType Mask = Mas; 390e8d8bef9SDimitry Andric // {SEW, VLMul} values set a valid VType to deal with this mask type. 391fe6060f1SDimitry Andric // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will 392fe6060f1SDimitry Andric // look for SEW=1 to optimize based on surrounding instructions. 393fe6060f1SDimitry Andric int SEW = 1; 394fe6060f1SDimitry Andric int Log2SEW = 0; 395e8d8bef9SDimitry Andric LMULInfo LMul = M; 396e8d8bef9SDimitry Andric string BX = Bx; // Appendix of mask operations. 397e8d8bef9SDimitry Andric // The pattern fragment which produces the AVL operand, representing the 398e8d8bef9SDimitry Andric // "natural" vector length for this mask type. For scalable masks this is 399e8d8bef9SDimitry Andric // VLMax. 400e8d8bef9SDimitry Andric OutPatFrag AVL = VLMax; 401e8d8bef9SDimitry Andric} 402e8d8bef9SDimitry Andric 403e8d8bef9SDimitry Andricdefset list<MTypeInfo> AllMasks = { 404e8d8bef9SDimitry Andric // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL. 405e8d8bef9SDimitry Andric def : MTypeInfo<vbool64_t, V_MF8, "B1">; 406e8d8bef9SDimitry Andric def : MTypeInfo<vbool32_t, V_MF4, "B2">; 407e8d8bef9SDimitry Andric def : MTypeInfo<vbool16_t, V_MF2, "B4">; 408e8d8bef9SDimitry Andric def : MTypeInfo<vbool8_t, V_M1, "B8">; 409e8d8bef9SDimitry Andric def : MTypeInfo<vbool4_t, V_M2, "B16">; 410e8d8bef9SDimitry Andric def : MTypeInfo<vbool2_t, V_M4, "B32">; 411e8d8bef9SDimitry Andric def : MTypeInfo<vbool1_t, V_M8, "B64">; 412e8d8bef9SDimitry Andric} 413e8d8bef9SDimitry Andric 41406c3fb27SDimitry Andricclass VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti> { 415e8d8bef9SDimitry Andric VTypeInfo Vti = vti; 416e8d8bef9SDimitry Andric VTypeInfo Wti = wti; 417e8d8bef9SDimitry Andric} 418e8d8bef9SDimitry Andric 41906c3fb27SDimitry Andricclass VTypeInfoToFraction<VTypeInfo vti, VTypeInfo fti> { 420e8d8bef9SDimitry Andric VTypeInfo Vti = vti; 421e8d8bef9SDimitry Andric VTypeInfo Fti = fti; 422e8d8bef9SDimitry Andric} 423e8d8bef9SDimitry Andric 424e8d8bef9SDimitry Andricdefset list<VTypeInfoToWide> AllWidenableIntVectors = { 425e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8MF8, VI16MF4>; 426e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8MF4, VI16MF2>; 427e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8MF2, VI16M1>; 428e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8M1, VI16M2>; 429e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8M2, VI16M4>; 430e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8M4, VI16M8>; 431e8d8bef9SDimitry Andric 432e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16MF4, VI32MF2>; 433e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16MF2, VI32M1>; 434e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16M1, VI32M2>; 435e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16M2, VI32M4>; 436e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16M4, VI32M8>; 437e8d8bef9SDimitry Andric 438e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32MF2, VI64M1>; 439e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32M1, VI64M2>; 440e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32M2, VI64M4>; 441e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32M4, VI64M8>; 442e8d8bef9SDimitry Andric} 443e8d8bef9SDimitry Andric 444e8d8bef9SDimitry Andricdefset list<VTypeInfoToWide> AllWidenableFloatVectors = { 445e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF16MF4, VF32MF2>; 446e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF16MF2, VF32M1>; 447e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF16M1, VF32M2>; 448e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF16M2, VF32M4>; 449e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF16M4, VF32M8>; 450e8d8bef9SDimitry Andric 451e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF32MF2, VF64M1>; 452e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF32M1, VF64M2>; 453e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF32M2, VF64M4>; 454e8d8bef9SDimitry Andric def : VTypeInfoToWide<VF32M4, VF64M8>; 455e8d8bef9SDimitry Andric} 456e8d8bef9SDimitry Andric 457e8d8bef9SDimitry Andricdefset list<VTypeInfoToFraction> AllFractionableVF2IntVectors = { 458e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI16MF4, VI8MF8>; 459e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI16MF2, VI8MF4>; 460e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI16M1, VI8MF2>; 461e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI16M2, VI8M1>; 462e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI16M4, VI8M2>; 463e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI16M8, VI8M4>; 464e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32MF2, VI16MF4>; 465e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M1, VI16MF2>; 466e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M2, VI16M1>; 467e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M4, VI16M2>; 468e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M8, VI16M4>; 469e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M1, VI32MF2>; 470e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M2, VI32M1>; 471e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M4, VI32M2>; 472e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M8, VI32M4>; 473e8d8bef9SDimitry Andric} 474e8d8bef9SDimitry Andric 475e8d8bef9SDimitry Andricdefset list<VTypeInfoToFraction> AllFractionableVF4IntVectors = { 476e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32MF2, VI8MF8>; 477e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M1, VI8MF4>; 478e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M2, VI8MF2>; 479e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M4, VI8M1>; 480e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI32M8, VI8M2>; 481e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M1, VI16MF4>; 482e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M2, VI16MF2>; 483e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M4, VI16M1>; 484e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M8, VI16M2>; 485e8d8bef9SDimitry Andric} 486e8d8bef9SDimitry Andric 487e8d8bef9SDimitry Andricdefset list<VTypeInfoToFraction> AllFractionableVF8IntVectors = { 488e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M1, VI8MF8>; 489e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M2, VI8MF4>; 490e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M4, VI8MF2>; 491e8d8bef9SDimitry Andric def : VTypeInfoToFraction<VI64M8, VI8M1>; 492e8d8bef9SDimitry Andric} 493e8d8bef9SDimitry Andric 494e8d8bef9SDimitry Andricdefset list<VTypeInfoToWide> AllWidenableIntToFloatVectors = { 495e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8MF8, VF16MF4>; 496e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8MF4, VF16MF2>; 497e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8MF2, VF16M1>; 498e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8M1, VF16M2>; 499e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8M2, VF16M4>; 500e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI8M4, VF16M8>; 501e8d8bef9SDimitry Andric 502e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16MF4, VF32MF2>; 503e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16MF2, VF32M1>; 504e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16M1, VF32M2>; 505e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16M2, VF32M4>; 506e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI16M4, VF32M8>; 507e8d8bef9SDimitry Andric 508e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32MF2, VF64M1>; 509e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32M1, VF64M2>; 510e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32M2, VF64M4>; 511e8d8bef9SDimitry Andric def : VTypeInfoToWide<VI32M4, VF64M8>; 512e8d8bef9SDimitry Andric} 513e8d8bef9SDimitry Andric 5145f757f3fSDimitry Andricdefset list<VTypeInfoToWide> AllWidenableBFloatToFloatVectors = { 5155f757f3fSDimitry Andric def : VTypeInfoToWide<VBF16MF4, VF32MF2>; 5165f757f3fSDimitry Andric def : VTypeInfoToWide<VBF16MF2, VF32M1>; 5175f757f3fSDimitry Andric def : VTypeInfoToWide<VBF16M1, VF32M2>; 5185f757f3fSDimitry Andric def : VTypeInfoToWide<VBF16M2, VF32M4>; 5195f757f3fSDimitry Andric def : VTypeInfoToWide<VBF16M4, VF32M8>; 5205f757f3fSDimitry Andric} 5215f757f3fSDimitry Andric 522e8d8bef9SDimitry Andric// This class holds the record of the RISCVVPseudoTable below. 523e8d8bef9SDimitry Andric// This represents the information we need in codegen for each pseudo. 524e8d8bef9SDimitry Andric// The definition should be consistent with `struct PseudoInfo` in 52506c3fb27SDimitry Andric// RISCVInstrInfo.h. 526e8d8bef9SDimitry Andricclass RISCVVPseudo { 527e8d8bef9SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key. 52881ad6265SDimitry Andric Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 52906c3fb27SDimitry Andric // SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown). 53006c3fb27SDimitry Andric bits<8> SEW = 0; 5315f757f3fSDimitry Andric bit NeedBeInPseudoTable = 1; 532e8d8bef9SDimitry Andric} 533e8d8bef9SDimitry Andric 534e8d8bef9SDimitry Andric// The actual table. 535e8d8bef9SDimitry Andricdef RISCVVPseudosTable : GenericTable { 536e8d8bef9SDimitry Andric let FilterClass = "RISCVVPseudo"; 5375f757f3fSDimitry Andric let FilterClassField = "NeedBeInPseudoTable"; 538e8d8bef9SDimitry Andric let CppTypeName = "PseudoInfo"; 539e8d8bef9SDimitry Andric let Fields = [ "Pseudo", "BaseInstr" ]; 540e8d8bef9SDimitry Andric let PrimaryKey = [ "Pseudo" ]; 541e8d8bef9SDimitry Andric let PrimaryKeyName = "getPseudoInfo"; 542fe6060f1SDimitry Andric let PrimaryKeyEarlyOut = true; 543e8d8bef9SDimitry Andric} 544e8d8bef9SDimitry Andric 545bdd1243dSDimitry Andricdef RISCVVInversePseudosTable : GenericTable { 546bdd1243dSDimitry Andric let FilterClass = "RISCVVPseudo"; 547bdd1243dSDimitry Andric let CppTypeName = "PseudoInfo"; 54806c3fb27SDimitry Andric let Fields = [ "Pseudo", "BaseInstr", "VLMul", "SEW"]; 54906c3fb27SDimitry Andric let PrimaryKey = [ "BaseInstr", "VLMul", "SEW"]; 550bdd1243dSDimitry Andric let PrimaryKeyName = "getBaseInfo"; 551bdd1243dSDimitry Andric let PrimaryKeyEarlyOut = true; 552bdd1243dSDimitry Andric} 553bdd1243dSDimitry Andric 554e8d8bef9SDimitry Andricdef RISCVVIntrinsicsTable : GenericTable { 555e8d8bef9SDimitry Andric let FilterClass = "RISCVVIntrinsic"; 556e8d8bef9SDimitry Andric let CppTypeName = "RISCVVIntrinsicInfo"; 55781ad6265SDimitry Andric let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand"]; 558e8d8bef9SDimitry Andric let PrimaryKey = ["IntrinsicID"]; 559e8d8bef9SDimitry Andric let PrimaryKeyName = "getRISCVVIntrinsicInfo"; 560e8d8bef9SDimitry Andric} 561e8d8bef9SDimitry Andric 56206c3fb27SDimitry Andric// Describes the relation of a masked pseudo to the unmasked variants. 56306c3fb27SDimitry Andric// Note that all masked variants (in this table) have exactly one 56406c3fb27SDimitry Andric// unmasked variant. For all but compares, both the masked and 56506c3fb27SDimitry Andric// unmasked variant have a passthru and policy operand. For compares, 56606c3fb27SDimitry Andric// neither has a policy op, and only the masked version has a passthru. 5675f757f3fSDimitry Andricclass RISCVMaskedPseudo<bits<4> MaskIdx, bit MaskAffectsRes=false> { 56881ad6265SDimitry Andric Pseudo MaskedPseudo = !cast<Pseudo>(NAME); 56981ad6265SDimitry Andric Pseudo UnmaskedPseudo = !cast<Pseudo>(!subst("_MASK", "", NAME)); 57081ad6265SDimitry Andric bits<4> MaskOpIdx = MaskIdx; 5715f757f3fSDimitry Andric bit MaskAffectsResult = MaskAffectsRes; 57281ad6265SDimitry Andric} 57381ad6265SDimitry Andric 57481ad6265SDimitry Andricdef RISCVMaskedPseudosTable : GenericTable { 57581ad6265SDimitry Andric let FilterClass = "RISCVMaskedPseudo"; 57681ad6265SDimitry Andric let CppTypeName = "RISCVMaskedPseudoInfo"; 5775f757f3fSDimitry Andric let Fields = ["MaskedPseudo", "UnmaskedPseudo", "MaskOpIdx", "MaskAffectsResult"]; 57881ad6265SDimitry Andric let PrimaryKey = ["MaskedPseudo"]; 57981ad6265SDimitry Andric let PrimaryKeyName = "getMaskedPseudoInfo"; 58081ad6265SDimitry Andric} 58181ad6265SDimitry Andric 58206c3fb27SDimitry Andricclass RISCVVLE<bit M, bit Str, bit F, bits<3> S, bits<3> L> { 583fe6060f1SDimitry Andric bits<1> Masked = M; 584fe6060f1SDimitry Andric bits<1> Strided = Str; 585fe6060f1SDimitry Andric bits<1> FF = F; 586fe6060f1SDimitry Andric bits<3> Log2SEW = S; 587fe6060f1SDimitry Andric bits<3> LMUL = L; 588fe6060f1SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); 589fe6060f1SDimitry Andric} 590fe6060f1SDimitry Andric 59106c3fb27SDimitry Andricdef lookupMaskedIntrinsicByUnmasked : SearchIndex { 592bdd1243dSDimitry Andric let Table = RISCVMaskedPseudosTable; 593bdd1243dSDimitry Andric let Key = ["UnmaskedPseudo"]; 594bdd1243dSDimitry Andric} 595bdd1243dSDimitry Andric 596fe6060f1SDimitry Andricdef RISCVVLETable : GenericTable { 597fe6060f1SDimitry Andric let FilterClass = "RISCVVLE"; 598fe6060f1SDimitry Andric let CppTypeName = "VLEPseudo"; 59906c3fb27SDimitry Andric let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"]; 60006c3fb27SDimitry Andric let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"]; 601fe6060f1SDimitry Andric let PrimaryKeyName = "getVLEPseudo"; 602fe6060f1SDimitry Andric} 603fe6060f1SDimitry Andric 604fe6060f1SDimitry Andricclass RISCVVSE<bit M, bit Str, bits<3> S, bits<3> L> { 605fe6060f1SDimitry Andric bits<1> Masked = M; 606fe6060f1SDimitry Andric bits<1> Strided = Str; 607fe6060f1SDimitry Andric bits<3> Log2SEW = S; 608fe6060f1SDimitry Andric bits<3> LMUL = L; 609fe6060f1SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); 610fe6060f1SDimitry Andric} 611fe6060f1SDimitry Andric 612fe6060f1SDimitry Andricdef RISCVVSETable : GenericTable { 613fe6060f1SDimitry Andric let FilterClass = "RISCVVSE"; 614fe6060f1SDimitry Andric let CppTypeName = "VSEPseudo"; 615fe6060f1SDimitry Andric let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"]; 616fe6060f1SDimitry Andric let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"]; 617fe6060f1SDimitry Andric let PrimaryKeyName = "getVSEPseudo"; 618fe6060f1SDimitry Andric} 619fe6060f1SDimitry Andric 62006c3fb27SDimitry Andricclass RISCVVLX_VSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> { 621fe6060f1SDimitry Andric bits<1> Masked = M; 622fe6060f1SDimitry Andric bits<1> Ordered = O; 623fe6060f1SDimitry Andric bits<3> Log2SEW = S; 624e8d8bef9SDimitry Andric bits<3> LMUL = L; 625e8d8bef9SDimitry Andric bits<3> IndexLMUL = IL; 626e8d8bef9SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); 627e8d8bef9SDimitry Andric} 628e8d8bef9SDimitry Andric 62906c3fb27SDimitry Andricclass RISCVVLX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> : 63006c3fb27SDimitry Andric RISCVVLX_VSX<M, O, S, L, IL>; 631fe6060f1SDimitry Andricclass RISCVVSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> : 63206c3fb27SDimitry Andric RISCVVLX_VSX<M, O, S, L, IL>; 633fe6060f1SDimitry Andric 634fe6060f1SDimitry Andricclass RISCVVLX_VSXTable : GenericTable { 635fe6060f1SDimitry Andric let CppTypeName = "VLX_VSXPseudo"; 63606c3fb27SDimitry Andric let Fields = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"]; 63706c3fb27SDimitry Andric let PrimaryKey = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"]; 638fe6060f1SDimitry Andric} 639fe6060f1SDimitry Andric 640fe6060f1SDimitry Andricdef RISCVVLXTable : RISCVVLX_VSXTable { 641fe6060f1SDimitry Andric let FilterClass = "RISCVVLX"; 642fe6060f1SDimitry Andric let PrimaryKeyName = "getVLXPseudo"; 643fe6060f1SDimitry Andric} 644fe6060f1SDimitry Andric 645fe6060f1SDimitry Andricdef RISCVVSXTable : RISCVVLX_VSXTable { 646fe6060f1SDimitry Andric let FilterClass = "RISCVVSX"; 647fe6060f1SDimitry Andric let PrimaryKeyName = "getVSXPseudo"; 648fe6060f1SDimitry Andric} 649fe6060f1SDimitry Andric 65006c3fb27SDimitry Andricclass RISCVVLSEG<bits<4> N, bit M, bit Str, bit F, bits<3> S, bits<3> L> { 651fe6060f1SDimitry Andric bits<4> NF = N; 652fe6060f1SDimitry Andric bits<1> Masked = M; 653fe6060f1SDimitry Andric bits<1> Strided = Str; 654fe6060f1SDimitry Andric bits<1> FF = F; 655fe6060f1SDimitry Andric bits<3> Log2SEW = S; 656fe6060f1SDimitry Andric bits<3> LMUL = L; 657fe6060f1SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); 658fe6060f1SDimitry Andric} 659fe6060f1SDimitry Andric 660fe6060f1SDimitry Andricdef RISCVVLSEGTable : GenericTable { 661fe6060f1SDimitry Andric let FilterClass = "RISCVVLSEG"; 662fe6060f1SDimitry Andric let CppTypeName = "VLSEGPseudo"; 66306c3fb27SDimitry Andric let Fields = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"]; 66406c3fb27SDimitry Andric let PrimaryKey = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL"]; 665fe6060f1SDimitry Andric let PrimaryKeyName = "getVLSEGPseudo"; 666fe6060f1SDimitry Andric} 667fe6060f1SDimitry Andric 66806c3fb27SDimitry Andricclass RISCVVLXSEG<bits<4> N, bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> { 669fe6060f1SDimitry Andric bits<4> NF = N; 670fe6060f1SDimitry Andric bits<1> Masked = M; 671fe6060f1SDimitry Andric bits<1> Ordered = O; 672fe6060f1SDimitry Andric bits<3> Log2SEW = S; 673fe6060f1SDimitry Andric bits<3> LMUL = L; 674fe6060f1SDimitry Andric bits<3> IndexLMUL = IL; 675fe6060f1SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); 676fe6060f1SDimitry Andric} 677fe6060f1SDimitry Andric 678fe6060f1SDimitry Andricdef RISCVVLXSEGTable : GenericTable { 679fe6060f1SDimitry Andric let FilterClass = "RISCVVLXSEG"; 680fe6060f1SDimitry Andric let CppTypeName = "VLXSEGPseudo"; 68106c3fb27SDimitry Andric let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"]; 68206c3fb27SDimitry Andric let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"]; 683fe6060f1SDimitry Andric let PrimaryKeyName = "getVLXSEGPseudo"; 684fe6060f1SDimitry Andric} 685fe6060f1SDimitry Andric 686fe6060f1SDimitry Andricclass RISCVVSSEG<bits<4> N, bit M, bit Str, bits<3> S, bits<3> L> { 687fe6060f1SDimitry Andric bits<4> NF = N; 688fe6060f1SDimitry Andric bits<1> Masked = M; 689fe6060f1SDimitry Andric bits<1> Strided = Str; 690fe6060f1SDimitry Andric bits<3> Log2SEW = S; 691fe6060f1SDimitry Andric bits<3> LMUL = L; 692fe6060f1SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); 693fe6060f1SDimitry Andric} 694fe6060f1SDimitry Andric 695fe6060f1SDimitry Andricdef RISCVVSSEGTable : GenericTable { 696fe6060f1SDimitry Andric let FilterClass = "RISCVVSSEG"; 697fe6060f1SDimitry Andric let CppTypeName = "VSSEGPseudo"; 698fe6060f1SDimitry Andric let Fields = ["NF", "Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"]; 699fe6060f1SDimitry Andric let PrimaryKey = ["NF", "Masked", "Strided", "Log2SEW", "LMUL"]; 700fe6060f1SDimitry Andric let PrimaryKeyName = "getVSSEGPseudo"; 701fe6060f1SDimitry Andric} 702fe6060f1SDimitry Andric 703fe6060f1SDimitry Andricclass RISCVVSXSEG<bits<4> N, bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> { 704fe6060f1SDimitry Andric bits<4> NF = N; 705fe6060f1SDimitry Andric bits<1> Masked = M; 706fe6060f1SDimitry Andric bits<1> Ordered = O; 707fe6060f1SDimitry Andric bits<3> Log2SEW = S; 708fe6060f1SDimitry Andric bits<3> LMUL = L; 709fe6060f1SDimitry Andric bits<3> IndexLMUL = IL; 710fe6060f1SDimitry Andric Pseudo Pseudo = !cast<Pseudo>(NAME); 711fe6060f1SDimitry Andric} 712fe6060f1SDimitry Andric 713fe6060f1SDimitry Andricdef RISCVVSXSEGTable : GenericTable { 714fe6060f1SDimitry Andric let FilterClass = "RISCVVSXSEG"; 715fe6060f1SDimitry Andric let CppTypeName = "VSXSEGPseudo"; 716fe6060f1SDimitry Andric let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"]; 717fe6060f1SDimitry Andric let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"]; 718fe6060f1SDimitry Andric let PrimaryKeyName = "getVSXSEGPseudo"; 719e8d8bef9SDimitry Andric} 720e8d8bef9SDimitry Andric 721e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 722e8d8bef9SDimitry Andric// Helpers to define the different pseudo instructions. 723e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 724e8d8bef9SDimitry Andric 725e8d8bef9SDimitry Andric// The destination vector register group for a masked vector instruction cannot 726e8d8bef9SDimitry Andric// overlap the source mask register (v0), unless the destination vector register 727e8d8bef9SDimitry Andric// is being written with a mask value (e.g., comparisons) or the scalar result 728e8d8bef9SDimitry Andric// of a reduction. 729e8d8bef9SDimitry Andricclass GetVRegNoV0<VReg VRegClass> { 730e8d8bef9SDimitry Andric VReg R = !cond(!eq(VRegClass, VR) : VRNoV0, 731e8d8bef9SDimitry Andric !eq(VRegClass, VRM2) : VRM2NoV0, 732e8d8bef9SDimitry Andric !eq(VRegClass, VRM4) : VRM4NoV0, 733e8d8bef9SDimitry Andric !eq(VRegClass, VRM8) : VRM8NoV0, 734fe6060f1SDimitry Andric !eq(VRegClass, VRN2M1) : VRN2M1NoV0, 735fe6060f1SDimitry Andric !eq(VRegClass, VRN2M2) : VRN2M2NoV0, 736fe6060f1SDimitry Andric !eq(VRegClass, VRN2M4) : VRN2M4NoV0, 737fe6060f1SDimitry Andric !eq(VRegClass, VRN3M1) : VRN3M1NoV0, 738fe6060f1SDimitry Andric !eq(VRegClass, VRN3M2) : VRN3M2NoV0, 739fe6060f1SDimitry Andric !eq(VRegClass, VRN4M1) : VRN4M1NoV0, 740fe6060f1SDimitry Andric !eq(VRegClass, VRN4M2) : VRN4M2NoV0, 741fe6060f1SDimitry Andric !eq(VRegClass, VRN5M1) : VRN5M1NoV0, 742fe6060f1SDimitry Andric !eq(VRegClass, VRN6M1) : VRN6M1NoV0, 743fe6060f1SDimitry Andric !eq(VRegClass, VRN7M1) : VRN7M1NoV0, 744fe6060f1SDimitry Andric !eq(VRegClass, VRN8M1) : VRN8M1NoV0, 745fe6060f1SDimitry Andric true : VRegClass); 746e8d8bef9SDimitry Andric} 747e8d8bef9SDimitry Andric 74806c3fb27SDimitry Andricclass VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins, int sew = 0> : 749e8d8bef9SDimitry Andric Pseudo<outs, ins, []>, RISCVVPseudo { 750e8d8bef9SDimitry Andric let BaseInstr = instr; 751e8d8bef9SDimitry Andric let VLMul = m.value; 75206c3fb27SDimitry Andric let SEW = sew; 753e8d8bef9SDimitry Andric} 754e8d8bef9SDimitry Andric 75506c3fb27SDimitry Andricclass GetVTypePredicates<VTypeInfo vti> { 75606c3fb27SDimitry Andric list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16], 7575f757f3fSDimitry Andric !eq(vti.Scalar, bf16) : [HasVInstructionsBF16], 75806c3fb27SDimitry Andric !eq(vti.Scalar, f32) : [HasVInstructionsAnyF], 75906c3fb27SDimitry Andric !eq(vti.Scalar, f64) : [HasVInstructionsF64], 76006c3fb27SDimitry Andric !eq(vti.SEW, 64) : [HasVInstructionsI64], 76106c3fb27SDimitry Andric true : [HasVInstructions]); 76206c3fb27SDimitry Andric} 76306c3fb27SDimitry Andric 7645f757f3fSDimitry Andricclass VPseudoUSLoadNoMask<VReg RetClass, 7655f757f3fSDimitry Andric int EEW> : 766e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 76706c3fb27SDimitry Andric (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew, 76806c3fb27SDimitry Andric ixlenimm:$policy), []>, 769fe6060f1SDimitry Andric RISCVVPseudo, 77006c3fb27SDimitry Andric RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> { 771e8d8bef9SDimitry Andric let mayLoad = 1; 772e8d8bef9SDimitry Andric let mayStore = 0; 773e8d8bef9SDimitry Andric let hasSideEffects = 0; 774e8d8bef9SDimitry Andric let HasVLOp = 1; 775e8d8bef9SDimitry Andric let HasSEWOp = 1; 77606c3fb27SDimitry Andric let HasVecPolicyOp = 1; 77704eeddc0SDimitry Andric let Constraints = "$rd = $dest"; 77804eeddc0SDimitry Andric} 77904eeddc0SDimitry Andric 7805f757f3fSDimitry Andricclass VPseudoUSLoadMask<VReg RetClass, 7815f757f3fSDimitry Andric int EEW> : 782e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 783e8d8bef9SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 784bdd1243dSDimitry Andric GPRMem:$rs1, 785349cc55cSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 786fe6060f1SDimitry Andric RISCVVPseudo, 78706c3fb27SDimitry Andric RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> { 788e8d8bef9SDimitry Andric let mayLoad = 1; 789e8d8bef9SDimitry Andric let mayStore = 0; 790e8d8bef9SDimitry Andric let hasSideEffects = 0; 791e8d8bef9SDimitry Andric let Constraints = "$rd = $merge"; 792e8d8bef9SDimitry Andric let HasVLOp = 1; 793e8d8bef9SDimitry Andric let HasSEWOp = 1; 794349cc55cSDimitry Andric let HasVecPolicyOp = 1; 79581ad6265SDimitry Andric let UsesMaskPolicy = 1; 79681ad6265SDimitry Andric} 79781ad6265SDimitry Andric 7985f757f3fSDimitry Andricclass VPseudoUSLoadFFNoMask<VReg RetClass, 7995f757f3fSDimitry Andric int EEW> : 80081ad6265SDimitry Andric Pseudo<(outs RetClass:$rd, GPR:$vl), 80106c3fb27SDimitry Andric (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, 80206c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 80381ad6265SDimitry Andric RISCVVPseudo, 80406c3fb27SDimitry Andric RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> { 80581ad6265SDimitry Andric let mayLoad = 1; 80681ad6265SDimitry Andric let mayStore = 0; 80781ad6265SDimitry Andric let hasSideEffects = 0; 80881ad6265SDimitry Andric let HasVLOp = 1; 80981ad6265SDimitry Andric let HasSEWOp = 1; 81006c3fb27SDimitry Andric let HasVecPolicyOp = 1; 81181ad6265SDimitry Andric let Constraints = "$rd = $dest"; 81281ad6265SDimitry Andric} 81381ad6265SDimitry Andric 8145f757f3fSDimitry Andricclass VPseudoUSLoadFFMask<VReg RetClass, 8155f757f3fSDimitry Andric int EEW> : 81681ad6265SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl), 81781ad6265SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 818bdd1243dSDimitry Andric GPRMem:$rs1, 81981ad6265SDimitry Andric VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>, 82081ad6265SDimitry Andric RISCVVPseudo, 82106c3fb27SDimitry Andric RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> { 82281ad6265SDimitry Andric let mayLoad = 1; 82381ad6265SDimitry Andric let mayStore = 0; 82481ad6265SDimitry Andric let hasSideEffects = 0; 82581ad6265SDimitry Andric let Constraints = "$rd = $merge"; 82681ad6265SDimitry Andric let HasVLOp = 1; 82781ad6265SDimitry Andric let HasSEWOp = 1; 82881ad6265SDimitry Andric let HasVecPolicyOp = 1; 82981ad6265SDimitry Andric let UsesMaskPolicy = 1; 830e8d8bef9SDimitry Andric} 831e8d8bef9SDimitry Andric 8325f757f3fSDimitry Andricclass VPseudoSLoadNoMask<VReg RetClass, 8335f757f3fSDimitry Andric int EEW> : 834e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 83506c3fb27SDimitry Andric (ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl, 83606c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 837fe6060f1SDimitry Andric RISCVVPseudo, 83806c3fb27SDimitry Andric RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> { 839e8d8bef9SDimitry Andric let mayLoad = 1; 840e8d8bef9SDimitry Andric let mayStore = 0; 841e8d8bef9SDimitry Andric let hasSideEffects = 0; 842e8d8bef9SDimitry Andric let HasVLOp = 1; 843e8d8bef9SDimitry Andric let HasSEWOp = 1; 84406c3fb27SDimitry Andric let HasVecPolicyOp = 1; 84504eeddc0SDimitry Andric let Constraints = "$rd = $dest"; 84604eeddc0SDimitry Andric} 84704eeddc0SDimitry Andric 8485f757f3fSDimitry Andricclass VPseudoSLoadMask<VReg RetClass, 8495f757f3fSDimitry Andric int EEW> : 850e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 851e8d8bef9SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 852bdd1243dSDimitry Andric GPRMem:$rs1, GPR:$rs2, 853349cc55cSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 854fe6060f1SDimitry Andric RISCVVPseudo, 85506c3fb27SDimitry Andric RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> { 856e8d8bef9SDimitry Andric let mayLoad = 1; 857e8d8bef9SDimitry Andric let mayStore = 0; 858e8d8bef9SDimitry Andric let hasSideEffects = 0; 859e8d8bef9SDimitry Andric let Constraints = "$rd = $merge"; 860e8d8bef9SDimitry Andric let HasVLOp = 1; 861e8d8bef9SDimitry Andric let HasSEWOp = 1; 862349cc55cSDimitry Andric let HasVecPolicyOp = 1; 86381ad6265SDimitry Andric let UsesMaskPolicy = 1; 864e8d8bef9SDimitry Andric} 865e8d8bef9SDimitry Andric 8665f757f3fSDimitry Andricclass VPseudoILoadNoMask<VReg RetClass, 8675f757f3fSDimitry Andric VReg IdxClass, 8685f757f3fSDimitry Andric int EEW, 8695f757f3fSDimitry Andric bits<3> LMUL, 8705f757f3fSDimitry Andric bit Ordered, 8715f757f3fSDimitry Andric bit EarlyClobber, 8725f757f3fSDimitry Andric int TargetConstraintType = 1> : 873e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 874bdd1243dSDimitry Andric (ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, 87506c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 87604eeddc0SDimitry Andric RISCVVPseudo, 87706c3fb27SDimitry Andric RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> { 87804eeddc0SDimitry Andric let mayLoad = 1; 87904eeddc0SDimitry Andric let mayStore = 0; 88004eeddc0SDimitry Andric let hasSideEffects = 0; 88104eeddc0SDimitry Andric let HasVLOp = 1; 88204eeddc0SDimitry Andric let HasSEWOp = 1; 88306c3fb27SDimitry Andric let HasVecPolicyOp = 1; 88404eeddc0SDimitry Andric let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest"); 8855f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 88604eeddc0SDimitry Andric} 88704eeddc0SDimitry Andric 8885f757f3fSDimitry Andricclass VPseudoILoadMask<VReg RetClass, 8895f757f3fSDimitry Andric VReg IdxClass, 8905f757f3fSDimitry Andric int EEW, 8915f757f3fSDimitry Andric bits<3> LMUL, 8925f757f3fSDimitry Andric bit Ordered, 8935f757f3fSDimitry Andric bit EarlyClobber, 8945f757f3fSDimitry Andric int TargetConstraintType = 1> : 895e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 896e8d8bef9SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 897bdd1243dSDimitry Andric GPRMem:$rs1, IdxClass:$rs2, 898349cc55cSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 899fe6060f1SDimitry Andric RISCVVPseudo, 90006c3fb27SDimitry Andric RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> { 901e8d8bef9SDimitry Andric let mayLoad = 1; 902e8d8bef9SDimitry Andric let mayStore = 0; 903e8d8bef9SDimitry Andric let hasSideEffects = 0; 904fe6060f1SDimitry Andric let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge"); 9055f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 906e8d8bef9SDimitry Andric let HasVLOp = 1; 907e8d8bef9SDimitry Andric let HasSEWOp = 1; 908349cc55cSDimitry Andric let HasVecPolicyOp = 1; 90981ad6265SDimitry Andric let UsesMaskPolicy = 1; 910e8d8bef9SDimitry Andric} 911e8d8bef9SDimitry Andric 9125f757f3fSDimitry Andricclass VPseudoUSStoreNoMask<VReg StClass, 9135f757f3fSDimitry Andric int EEW> : 914e8d8bef9SDimitry Andric Pseudo<(outs), 915bdd1243dSDimitry Andric (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>, 916fe6060f1SDimitry Andric RISCVVPseudo, 91706c3fb27SDimitry Andric RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> { 918e8d8bef9SDimitry Andric let mayLoad = 0; 919e8d8bef9SDimitry Andric let mayStore = 1; 920e8d8bef9SDimitry Andric let hasSideEffects = 0; 921e8d8bef9SDimitry Andric let HasVLOp = 1; 922e8d8bef9SDimitry Andric let HasSEWOp = 1; 923e8d8bef9SDimitry Andric} 924e8d8bef9SDimitry Andric 9255f757f3fSDimitry Andricclass VPseudoUSStoreMask<VReg StClass, 9265f757f3fSDimitry Andric int EEW> : 927e8d8bef9SDimitry Andric Pseudo<(outs), 9285f757f3fSDimitry Andric (ins StClass:$rd, GPRMem:$rs1, 9295f757f3fSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 930fe6060f1SDimitry Andric RISCVVPseudo, 93106c3fb27SDimitry Andric RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> { 932e8d8bef9SDimitry Andric let mayLoad = 0; 933e8d8bef9SDimitry Andric let mayStore = 1; 934e8d8bef9SDimitry Andric let hasSideEffects = 0; 935e8d8bef9SDimitry Andric let HasVLOp = 1; 936e8d8bef9SDimitry Andric let HasSEWOp = 1; 937e8d8bef9SDimitry Andric} 938e8d8bef9SDimitry Andric 9395f757f3fSDimitry Andricclass VPseudoSStoreNoMask<VReg StClass, 9405f757f3fSDimitry Andric int EEW> : 941e8d8bef9SDimitry Andric Pseudo<(outs), 9425f757f3fSDimitry Andric (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, 9435f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew), []>, 944fe6060f1SDimitry Andric RISCVVPseudo, 94506c3fb27SDimitry Andric RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> { 946e8d8bef9SDimitry Andric let mayLoad = 0; 947e8d8bef9SDimitry Andric let mayStore = 1; 948e8d8bef9SDimitry Andric let hasSideEffects = 0; 949e8d8bef9SDimitry Andric let HasVLOp = 1; 950e8d8bef9SDimitry Andric let HasSEWOp = 1; 951e8d8bef9SDimitry Andric} 952e8d8bef9SDimitry Andric 9535f757f3fSDimitry Andricclass VPseudoSStoreMask<VReg StClass, 9545f757f3fSDimitry Andric int EEW> : 955e8d8bef9SDimitry Andric Pseudo<(outs), 9565f757f3fSDimitry Andric (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, 9575f757f3fSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 958fe6060f1SDimitry Andric RISCVVPseudo, 95906c3fb27SDimitry Andric RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> { 960e8d8bef9SDimitry Andric let mayLoad = 0; 961e8d8bef9SDimitry Andric let mayStore = 1; 962e8d8bef9SDimitry Andric let hasSideEffects = 0; 963e8d8bef9SDimitry Andric let HasVLOp = 1; 964e8d8bef9SDimitry Andric let HasSEWOp = 1; 965e8d8bef9SDimitry Andric} 966e8d8bef9SDimitry Andric 967e8d8bef9SDimitry Andricclass VPseudoNullaryNoMask<VReg RegClass> : 968e8d8bef9SDimitry Andric Pseudo<(outs RegClass:$rd), 9695f757f3fSDimitry Andric (ins RegClass:$merge, 9705f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 9715f757f3fSDimitry Andric RISCVVPseudo { 97281ad6265SDimitry Andric let mayLoad = 0; 97381ad6265SDimitry Andric let mayStore = 0; 97481ad6265SDimitry Andric let hasSideEffects = 0; 97581ad6265SDimitry Andric let Constraints = "$rd = $merge"; 97681ad6265SDimitry Andric let HasVLOp = 1; 97781ad6265SDimitry Andric let HasSEWOp = 1; 97806c3fb27SDimitry Andric let HasVecPolicyOp = 1; 979e8d8bef9SDimitry Andric} 980e8d8bef9SDimitry Andric 981e8d8bef9SDimitry Andricclass VPseudoNullaryMask<VReg RegClass> : 982e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd), 9835f757f3fSDimitry Andric (ins GetVRegNoV0<RegClass>.R:$merge, 9845f757f3fSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 9855f757f3fSDimitry Andric RISCVVPseudo { 986e8d8bef9SDimitry Andric let mayLoad = 0; 987e8d8bef9SDimitry Andric let mayStore = 0; 988e8d8bef9SDimitry Andric let hasSideEffects = 0; 989e8d8bef9SDimitry Andric let Constraints ="$rd = $merge"; 990e8d8bef9SDimitry Andric let HasVLOp = 1; 991e8d8bef9SDimitry Andric let HasSEWOp = 1; 99281ad6265SDimitry Andric let UsesMaskPolicy = 1; 99381ad6265SDimitry Andric let HasVecPolicyOp = 1; 994e8d8bef9SDimitry Andric} 995e8d8bef9SDimitry Andric 996e8d8bef9SDimitry Andric// Nullary for pseudo instructions. They are expanded in 997e8d8bef9SDimitry Andric// RISCVExpandPseudoInsts pass. 9985f757f3fSDimitry Andricclass VPseudoNullaryPseudoM<string BaseInst> : 9995f757f3fSDimitry Andric Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>, 1000e8d8bef9SDimitry Andric RISCVVPseudo { 1001e8d8bef9SDimitry Andric let mayLoad = 0; 1002e8d8bef9SDimitry Andric let mayStore = 0; 1003e8d8bef9SDimitry Andric let hasSideEffects = 0; 1004e8d8bef9SDimitry Andric let HasVLOp = 1; 1005e8d8bef9SDimitry Andric let HasSEWOp = 1; 1006e8d8bef9SDimitry Andric // BaseInstr is not used in RISCVExpandPseudoInsts pass. 1007e8d8bef9SDimitry Andric // Just fill a corresponding real v-inst to pass tablegen check. 1008e8d8bef9SDimitry Andric let BaseInstr = !cast<Instruction>(BaseInst); 10095f757f3fSDimitry Andric // We exclude them from RISCVVPseudoTable. 10105f757f3fSDimitry Andric let NeedBeInPseudoTable = 0; 1011e8d8bef9SDimitry Andric} 1012e8d8bef9SDimitry Andric 10135f757f3fSDimitry Andricclass VPseudoUnaryNoMask<DAGOperand RetClass, 10145f757f3fSDimitry Andric DAGOperand OpClass, 10155f757f3fSDimitry Andric string Constraint = "", 10165f757f3fSDimitry Andric int TargetConstraintType = 1> : 1017e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 10185f757f3fSDimitry Andric (ins RetClass:$merge, OpClass:$rs2, 10195f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 1020e8d8bef9SDimitry Andric RISCVVPseudo { 1021e8d8bef9SDimitry Andric let mayLoad = 0; 1022e8d8bef9SDimitry Andric let mayStore = 0; 1023e8d8bef9SDimitry Andric let hasSideEffects = 0; 102406c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 10255f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1026e8d8bef9SDimitry Andric let HasVLOp = 1; 1027e8d8bef9SDimitry Andric let HasSEWOp = 1; 102806c3fb27SDimitry Andric let HasVecPolicyOp = 1; 102981ad6265SDimitry Andric} 103081ad6265SDimitry Andric 10315f757f3fSDimitry Andricclass VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass, 10325f757f3fSDimitry Andric DAGOperand OpClass, 10335f757f3fSDimitry Andric string Constraint = "", 10345f757f3fSDimitry Andric int TargetConstraintType = 1> : 103581ad6265SDimitry Andric Pseudo<(outs RetClass:$rd), 10365f757f3fSDimitry Andric (ins RetClass:$merge, OpClass:$rs2, ixlenimm:$rm, 10375f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 103881ad6265SDimitry Andric RISCVVPseudo { 103981ad6265SDimitry Andric let mayLoad = 0; 104081ad6265SDimitry Andric let mayStore = 0; 104181ad6265SDimitry Andric let hasSideEffects = 0; 104206c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 10435f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 104481ad6265SDimitry Andric let HasVLOp = 1; 104581ad6265SDimitry Andric let HasSEWOp = 1; 104606c3fb27SDimitry Andric let HasVecPolicyOp = 1; 104706c3fb27SDimitry Andric let HasRoundModeOp = 1; 104806c3fb27SDimitry Andric let UsesVXRM = 0; 1049e8d8bef9SDimitry Andric} 1050e8d8bef9SDimitry Andric 10515f757f3fSDimitry Andricclass VPseudoUnaryMask<VReg RetClass, 10525f757f3fSDimitry Andric VReg OpClass, 10535f757f3fSDimitry Andric string Constraint = "", 10545f757f3fSDimitry Andric int TargetConstraintType = 1> : 1055e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1056e8d8bef9SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, 1057349cc55cSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 1058349cc55cSDimitry Andric RISCVVPseudo { 1059349cc55cSDimitry Andric let mayLoad = 0; 1060349cc55cSDimitry Andric let mayStore = 0; 1061349cc55cSDimitry Andric let hasSideEffects = 0; 106206c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 10635f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1064349cc55cSDimitry Andric let HasVLOp = 1; 1065349cc55cSDimitry Andric let HasSEWOp = 1; 1066349cc55cSDimitry Andric let HasVecPolicyOp = 1; 106781ad6265SDimitry Andric let UsesMaskPolicy = 1; 1068349cc55cSDimitry Andric} 1069349cc55cSDimitry Andric 10705f757f3fSDimitry Andricclass VPseudoUnaryMaskRoundingMode<VReg RetClass, 10715f757f3fSDimitry Andric VReg OpClass, 1072647cbc5dSDimitry Andric string Constraint = "", 1073647cbc5dSDimitry Andric int TargetConstraintType = 1> : 107406c3fb27SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 107506c3fb27SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, 107606c3fb27SDimitry Andric VMaskOp:$vm, ixlenimm:$rm, 107706c3fb27SDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 107806c3fb27SDimitry Andric RISCVVPseudo { 107906c3fb27SDimitry Andric let mayLoad = 0; 108006c3fb27SDimitry Andric let mayStore = 0; 108106c3fb27SDimitry Andric let hasSideEffects = 0; 108206c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 1083647cbc5dSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 108406c3fb27SDimitry Andric let HasVLOp = 1; 108506c3fb27SDimitry Andric let HasSEWOp = 1; 108606c3fb27SDimitry Andric let HasVecPolicyOp = 1; 108706c3fb27SDimitry Andric let UsesMaskPolicy = 1; 108806c3fb27SDimitry Andric let HasRoundModeOp = 1; 108906c3fb27SDimitry Andric let UsesVXRM = 0; 109006c3fb27SDimitry Andric} 109106c3fb27SDimitry Andric 10925f757f3fSDimitry Andricclass VPseudoUnaryMask_NoExcept<VReg RetClass, 10935f757f3fSDimitry Andric VReg OpClass, 10945f757f3fSDimitry Andric string Constraint = ""> : 1095bdd1243dSDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1096bdd1243dSDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, 10975f757f3fSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> { 1098bdd1243dSDimitry Andric let mayLoad = 0; 1099bdd1243dSDimitry Andric let mayStore = 0; 1100bdd1243dSDimitry Andric let hasSideEffects = 0; 110106c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 1102bdd1243dSDimitry Andric let HasVLOp = 1; 1103bdd1243dSDimitry Andric let HasSEWOp = 1; 1104bdd1243dSDimitry Andric let HasVecPolicyOp = 1; 1105bdd1243dSDimitry Andric let UsesMaskPolicy = 1; 1106bdd1243dSDimitry Andric let usesCustomInserter = 1; 1107bdd1243dSDimitry Andric} 1108bdd1243dSDimitry Andric 11095f757f3fSDimitry Andricclass VPseudoUnaryNoMask_FRM<VReg RetClass, 11105f757f3fSDimitry Andric VReg OpClass, 1111647cbc5dSDimitry Andric string Constraint = "", 1112647cbc5dSDimitry Andric int TargetConstraintType = 1> : 11135f757f3fSDimitry Andric Pseudo<(outs RetClass:$rd), 11145f757f3fSDimitry Andric (ins RetClass:$merge, OpClass:$rs2, ixlenimm:$frm, 11155f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 11165f757f3fSDimitry Andric RISCVVPseudo { 11175f757f3fSDimitry Andric let mayLoad = 0; 11185f757f3fSDimitry Andric let mayStore = 0; 11195f757f3fSDimitry Andric let hasSideEffects = 0; 11205f757f3fSDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 1121647cbc5dSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 11225f757f3fSDimitry Andric let HasVLOp = 1; 11235f757f3fSDimitry Andric let HasSEWOp = 1; 11245f757f3fSDimitry Andric let HasVecPolicyOp = 1; 11255f757f3fSDimitry Andric let HasRoundModeOp = 1; 11265f757f3fSDimitry Andric} 11275f757f3fSDimitry Andric 11285f757f3fSDimitry Andricclass VPseudoUnaryMask_FRM<VReg RetClass, 11295f757f3fSDimitry Andric VReg OpClass, 1130647cbc5dSDimitry Andric string Constraint = "", 1131647cbc5dSDimitry Andric int TargetConstraintType = 1> : 11325f757f3fSDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 11335f757f3fSDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, 11345f757f3fSDimitry Andric VMaskOp:$vm, ixlenimm:$frm, 11355f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 11365f757f3fSDimitry Andric RISCVVPseudo { 11375f757f3fSDimitry Andric let mayLoad = 0; 11385f757f3fSDimitry Andric let mayStore = 0; 11395f757f3fSDimitry Andric let hasSideEffects = 0; 11405f757f3fSDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 1141647cbc5dSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 11425f757f3fSDimitry Andric let HasVLOp = 1; 11435f757f3fSDimitry Andric let HasSEWOp = 1; 11445f757f3fSDimitry Andric let HasVecPolicyOp = 1; 11455f757f3fSDimitry Andric let UsesMaskPolicy = 1; 11465f757f3fSDimitry Andric let HasRoundModeOp = 1; 11475f757f3fSDimitry Andric} 11485f757f3fSDimitry Andric 114906c3fb27SDimitry Andricclass VPseudoUnaryNoMaskGPROut : 115006c3fb27SDimitry Andric Pseudo<(outs GPR:$rd), 115106c3fb27SDimitry Andric (ins VR:$rs2, AVL:$vl, ixlenimm:$sew), []>, 115206c3fb27SDimitry Andric RISCVVPseudo { 115306c3fb27SDimitry Andric let mayLoad = 0; 115406c3fb27SDimitry Andric let mayStore = 0; 115506c3fb27SDimitry Andric let hasSideEffects = 0; 115606c3fb27SDimitry Andric let HasVLOp = 1; 115706c3fb27SDimitry Andric let HasSEWOp = 1; 115806c3fb27SDimitry Andric} 115906c3fb27SDimitry Andric 116006c3fb27SDimitry Andricclass VPseudoUnaryMaskGPROut : 1161e8d8bef9SDimitry Andric Pseudo<(outs GPR:$rd), 1162fe6060f1SDimitry Andric (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 1163e8d8bef9SDimitry Andric RISCVVPseudo { 1164e8d8bef9SDimitry Andric let mayLoad = 0; 1165e8d8bef9SDimitry Andric let mayStore = 0; 1166e8d8bef9SDimitry Andric let hasSideEffects = 0; 1167e8d8bef9SDimitry Andric let HasVLOp = 1; 1168e8d8bef9SDimitry Andric let HasSEWOp = 1; 1169e8d8bef9SDimitry Andric} 1170e8d8bef9SDimitry Andric 1171e8d8bef9SDimitry Andric// Mask can be V0~V31 1172e8d8bef9SDimitry Andricclass VPseudoUnaryAnyMask<VReg RetClass, 1173e8d8bef9SDimitry Andric VReg Op1Class> : 1174e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 11755f757f3fSDimitry Andric (ins RetClass:$merge, Op1Class:$rs2, 11765f757f3fSDimitry Andric VR:$vm, AVL:$vl, ixlenimm:$sew), []>, 1177e8d8bef9SDimitry Andric RISCVVPseudo { 1178e8d8bef9SDimitry Andric let mayLoad = 0; 1179e8d8bef9SDimitry Andric let mayStore = 0; 1180e8d8bef9SDimitry Andric let hasSideEffects = 0; 1181e8d8bef9SDimitry Andric let Constraints = "@earlyclobber $rd, $rd = $merge"; 1182e8d8bef9SDimitry Andric let HasVLOp = 1; 1183e8d8bef9SDimitry Andric let HasSEWOp = 1; 1184e8d8bef9SDimitry Andric} 1185e8d8bef9SDimitry Andric 1186e8d8bef9SDimitry Andricclass VPseudoBinaryNoMask<VReg RetClass, 1187e8d8bef9SDimitry Andric VReg Op1Class, 1188e8d8bef9SDimitry Andric DAGOperand Op2Class, 11895f757f3fSDimitry Andric string Constraint, 11905f757f3fSDimitry Andric int TargetConstraintType = 1> : 1191e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 1192fe6060f1SDimitry Andric (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>, 1193e8d8bef9SDimitry Andric RISCVVPseudo { 1194e8d8bef9SDimitry Andric let mayLoad = 0; 1195e8d8bef9SDimitry Andric let mayStore = 0; 1196e8d8bef9SDimitry Andric let hasSideEffects = 0; 1197e8d8bef9SDimitry Andric let Constraints = Constraint; 11985f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1199e8d8bef9SDimitry Andric let HasVLOp = 1; 1200e8d8bef9SDimitry Andric let HasSEWOp = 1; 120181ad6265SDimitry Andric} 120281ad6265SDimitry Andric 120381ad6265SDimitry Andricclass VPseudoBinaryNoMaskTU<VReg RetClass, 120481ad6265SDimitry Andric VReg Op1Class, 120581ad6265SDimitry Andric DAGOperand Op2Class, 12065f757f3fSDimitry Andric string Constraint, 12075f757f3fSDimitry Andric int TargetConstraintType = 1> : 120881ad6265SDimitry Andric Pseudo<(outs RetClass:$rd), 120906c3fb27SDimitry Andric (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, 121006c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 121181ad6265SDimitry Andric RISCVVPseudo { 121281ad6265SDimitry Andric let mayLoad = 0; 121381ad6265SDimitry Andric let mayStore = 0; 121481ad6265SDimitry Andric let hasSideEffects = 0; 121506c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 12165f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 121781ad6265SDimitry Andric let HasVLOp = 1; 121881ad6265SDimitry Andric let HasSEWOp = 1; 121906c3fb27SDimitry Andric let HasVecPolicyOp = 1; 122006c3fb27SDimitry Andric} 122106c3fb27SDimitry Andric 122206c3fb27SDimitry Andricclass VPseudoBinaryNoMaskRoundingMode<VReg RetClass, 122306c3fb27SDimitry Andric VReg Op1Class, 122406c3fb27SDimitry Andric DAGOperand Op2Class, 122506c3fb27SDimitry Andric string Constraint, 12265f757f3fSDimitry Andric int UsesVXRM_ = 1, 12275f757f3fSDimitry Andric int TargetConstraintType = 1> : 122806c3fb27SDimitry Andric Pseudo<(outs RetClass:$rd), 122906c3fb27SDimitry Andric (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm, 123006c3fb27SDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 123106c3fb27SDimitry Andric RISCVVPseudo { 123206c3fb27SDimitry Andric let mayLoad = 0; 123306c3fb27SDimitry Andric let mayStore = 0; 123406c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 12355f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 123606c3fb27SDimitry Andric let HasVLOp = 1; 123706c3fb27SDimitry Andric let HasSEWOp = 1; 123806c3fb27SDimitry Andric let HasVecPolicyOp = 1; 123906c3fb27SDimitry Andric let HasRoundModeOp = 1; 124006c3fb27SDimitry Andric let UsesVXRM = UsesVXRM_; 124106c3fb27SDimitry Andric} 124206c3fb27SDimitry Andric 124306c3fb27SDimitry Andricclass VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass, 124406c3fb27SDimitry Andric RegisterClass Op1Class, 124506c3fb27SDimitry Andric DAGOperand Op2Class, 124606c3fb27SDimitry Andric string Constraint, 12475f757f3fSDimitry Andric int UsesVXRM_, 12485f757f3fSDimitry Andric int TargetConstraintType = 1> : 124906c3fb27SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 125006c3fb27SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 125106c3fb27SDimitry Andric Op1Class:$rs2, Op2Class:$rs1, 125206c3fb27SDimitry Andric VMaskOp:$vm, ixlenimm:$rm, AVL:$vl, 125306c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 125406c3fb27SDimitry Andric RISCVVPseudo { 125506c3fb27SDimitry Andric let mayLoad = 0; 125606c3fb27SDimitry Andric let mayStore = 0; 125706c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 12585f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 125906c3fb27SDimitry Andric let HasVLOp = 1; 126006c3fb27SDimitry Andric let HasSEWOp = 1; 126106c3fb27SDimitry Andric let HasVecPolicyOp = 1; 126206c3fb27SDimitry Andric let UsesMaskPolicy = 1; 126306c3fb27SDimitry Andric let HasRoundModeOp = 1; 126406c3fb27SDimitry Andric let UsesVXRM = UsesVXRM_; 1265e8d8bef9SDimitry Andric} 1266e8d8bef9SDimitry Andric 126704eeddc0SDimitry Andric// Special version of VPseudoBinaryNoMask where we pretend the first source is 126804eeddc0SDimitry Andric// tied to the destination. 126904eeddc0SDimitry Andric// This allows maskedoff and rs2 to be the same register. 1270fe6060f1SDimitry Andricclass VPseudoTiedBinaryNoMask<VReg RetClass, 1271fe6060f1SDimitry Andric DAGOperand Op2Class, 12725f757f3fSDimitry Andric string Constraint, 12735f757f3fSDimitry Andric int TargetConstraintType = 1> : 1274fe6060f1SDimitry Andric Pseudo<(outs RetClass:$rd), 127581ad6265SDimitry Andric (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew, 127681ad6265SDimitry Andric ixlenimm:$policy), []>, 1277e8d8bef9SDimitry Andric RISCVVPseudo { 1278e8d8bef9SDimitry Andric let mayLoad = 0; 1279fe6060f1SDimitry Andric let mayStore = 0; 1280fe6060f1SDimitry Andric let hasSideEffects = 0; 128106c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $rs2"], ","); 12825f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1283fe6060f1SDimitry Andric let HasVLOp = 1; 1284fe6060f1SDimitry Andric let HasSEWOp = 1; 128581ad6265SDimitry Andric let HasVecPolicyOp = 1; 1286fe6060f1SDimitry Andric let isConvertibleToThreeAddress = 1; 128706c3fb27SDimitry Andric let IsTiedPseudo = 1; 128806c3fb27SDimitry Andric} 128906c3fb27SDimitry Andric 129006c3fb27SDimitry Andricclass VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass, 129106c3fb27SDimitry Andric DAGOperand Op2Class, 12925f757f3fSDimitry Andric string Constraint, 12935f757f3fSDimitry Andric int TargetConstraintType = 1> : 129406c3fb27SDimitry Andric Pseudo<(outs RetClass:$rd), 129506c3fb27SDimitry Andric (ins RetClass:$rs2, Op2Class:$rs1, 129606c3fb27SDimitry Andric ixlenimm:$rm, 129706c3fb27SDimitry Andric AVL:$vl, ixlenimm:$sew, 129806c3fb27SDimitry Andric ixlenimm:$policy), []>, 129906c3fb27SDimitry Andric RISCVVPseudo { 130006c3fb27SDimitry Andric let mayLoad = 0; 130106c3fb27SDimitry Andric let mayStore = 0; 130206c3fb27SDimitry Andric let hasSideEffects = 0; 130306c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $rs2"], ","); 13045f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 130506c3fb27SDimitry Andric let HasVLOp = 1; 130606c3fb27SDimitry Andric let HasSEWOp = 1; 130706c3fb27SDimitry Andric let HasVecPolicyOp = 1; 130806c3fb27SDimitry Andric let isConvertibleToThreeAddress = 1; 130906c3fb27SDimitry Andric let IsTiedPseudo = 1; 131006c3fb27SDimitry Andric let HasRoundModeOp = 1; 131106c3fb27SDimitry Andric let UsesVXRM = 0; 1312fe6060f1SDimitry Andric} 1313fe6060f1SDimitry Andric 1314fe6060f1SDimitry Andricclass VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL, 1315fe6060f1SDimitry Andric bit Ordered>: 1316fe6060f1SDimitry Andric Pseudo<(outs), 13175f757f3fSDimitry Andric (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, 13185f757f3fSDimitry Andric ixlenimm:$sew),[]>, 1319fe6060f1SDimitry Andric RISCVVPseudo, 132006c3fb27SDimitry Andric RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> { 1321fe6060f1SDimitry Andric let mayLoad = 0; 1322e8d8bef9SDimitry Andric let mayStore = 1; 1323e8d8bef9SDimitry Andric let hasSideEffects = 0; 1324e8d8bef9SDimitry Andric let HasVLOp = 1; 1325e8d8bef9SDimitry Andric let HasSEWOp = 1; 1326e8d8bef9SDimitry Andric} 1327e8d8bef9SDimitry Andric 1328fe6060f1SDimitry Andricclass VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL, 1329fe6060f1SDimitry Andric bit Ordered>: 1330e8d8bef9SDimitry Andric Pseudo<(outs), 13315f757f3fSDimitry Andric (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, 13325f757f3fSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, 1333fe6060f1SDimitry Andric RISCVVPseudo, 133406c3fb27SDimitry Andric RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> { 1335e8d8bef9SDimitry Andric let mayLoad = 0; 1336e8d8bef9SDimitry Andric let mayStore = 1; 1337e8d8bef9SDimitry Andric let hasSideEffects = 0; 1338e8d8bef9SDimitry Andric let HasVLOp = 1; 1339e8d8bef9SDimitry Andric let HasSEWOp = 1; 1340e8d8bef9SDimitry Andric} 1341e8d8bef9SDimitry Andric 1342e8d8bef9SDimitry Andricclass VPseudoBinaryMask<VReg RetClass, 1343fe6060f1SDimitry Andric RegisterClass Op1Class, 1344e8d8bef9SDimitry Andric DAGOperand Op2Class, 1345e8d8bef9SDimitry Andric string Constraint> : 1346e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1347e8d8bef9SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 1348e8d8bef9SDimitry Andric Op1Class:$rs2, Op2Class:$rs1, 1349fe6060f1SDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 1350e8d8bef9SDimitry Andric RISCVVPseudo { 1351e8d8bef9SDimitry Andric let mayLoad = 0; 1352e8d8bef9SDimitry Andric let mayStore = 0; 1353e8d8bef9SDimitry Andric let hasSideEffects = 0; 135406c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 1355e8d8bef9SDimitry Andric let HasVLOp = 1; 1356e8d8bef9SDimitry Andric let HasSEWOp = 1; 1357e8d8bef9SDimitry Andric} 1358e8d8bef9SDimitry Andric 135981ad6265SDimitry Andricclass VPseudoBinaryMaskPolicy<VReg RetClass, 1360349cc55cSDimitry Andric RegisterClass Op1Class, 1361349cc55cSDimitry Andric DAGOperand Op2Class, 13625f757f3fSDimitry Andric string Constraint, 13635f757f3fSDimitry Andric int TargetConstraintType = 1> : 1364349cc55cSDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1365349cc55cSDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 1366349cc55cSDimitry Andric Op1Class:$rs2, Op2Class:$rs1, 1367349cc55cSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 1368349cc55cSDimitry Andric RISCVVPseudo { 1369349cc55cSDimitry Andric let mayLoad = 0; 1370349cc55cSDimitry Andric let mayStore = 0; 1371349cc55cSDimitry Andric let hasSideEffects = 0; 137206c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 13735f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1374349cc55cSDimitry Andric let HasVLOp = 1; 1375349cc55cSDimitry Andric let HasSEWOp = 1; 1376349cc55cSDimitry Andric let HasVecPolicyOp = 1; 137781ad6265SDimitry Andric let UsesMaskPolicy = 1; 1378349cc55cSDimitry Andric} 1379349cc55cSDimitry Andric 138006c3fb27SDimitry Andricclass VPseudoTernaryMaskPolicy<VReg RetClass, 138106c3fb27SDimitry Andric RegisterClass Op1Class, 138206c3fb27SDimitry Andric DAGOperand Op2Class, 138306c3fb27SDimitry Andric string Constraint> : 138406c3fb27SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 138506c3fb27SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 138606c3fb27SDimitry Andric Op1Class:$rs2, Op2Class:$rs1, 138706c3fb27SDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 138806c3fb27SDimitry Andric RISCVVPseudo { 138906c3fb27SDimitry Andric let mayLoad = 0; 139006c3fb27SDimitry Andric let mayStore = 0; 139106c3fb27SDimitry Andric let hasSideEffects = 0; 139206c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 139306c3fb27SDimitry Andric let HasVLOp = 1; 139406c3fb27SDimitry Andric let HasSEWOp = 1; 139506c3fb27SDimitry Andric let HasVecPolicyOp = 1; 139606c3fb27SDimitry Andric} 139706c3fb27SDimitry Andric 139806c3fb27SDimitry Andricclass VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass, 139906c3fb27SDimitry Andric RegisterClass Op1Class, 140006c3fb27SDimitry Andric DAGOperand Op2Class, 140106c3fb27SDimitry Andric string Constraint> : 140206c3fb27SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 140306c3fb27SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 140406c3fb27SDimitry Andric Op1Class:$rs2, Op2Class:$rs1, 140506c3fb27SDimitry Andric VMaskOp:$vm, 140606c3fb27SDimitry Andric ixlenimm:$rm, 140706c3fb27SDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 140806c3fb27SDimitry Andric RISCVVPseudo { 140906c3fb27SDimitry Andric let mayLoad = 0; 141006c3fb27SDimitry Andric let mayStore = 0; 141106c3fb27SDimitry Andric let hasSideEffects = 0; 141206c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 141306c3fb27SDimitry Andric let HasVLOp = 1; 141406c3fb27SDimitry Andric let HasSEWOp = 1; 141506c3fb27SDimitry Andric let HasVecPolicyOp = 1; 141606c3fb27SDimitry Andric let HasRoundModeOp = 1; 141706c3fb27SDimitry Andric let UsesVXRM = 0; 141806c3fb27SDimitry Andric} 141906c3fb27SDimitry Andric 142006c3fb27SDimitry Andric// Like VPseudoBinaryNoMask, but output can be V0. 142106c3fb27SDimitry Andricclass VPseudoBinaryMOutNoMask<VReg RetClass, 142206c3fb27SDimitry Andric VReg Op1Class, 142306c3fb27SDimitry Andric DAGOperand Op2Class, 14245f757f3fSDimitry Andric string Constraint, 14255f757f3fSDimitry Andric int TargetConstraintType = 1> : 142606c3fb27SDimitry Andric Pseudo<(outs RetClass:$rd), 142706c3fb27SDimitry Andric (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>, 142806c3fb27SDimitry Andric RISCVVPseudo { 142906c3fb27SDimitry Andric let mayLoad = 0; 143006c3fb27SDimitry Andric let mayStore = 0; 143106c3fb27SDimitry Andric let hasSideEffects = 0; 143206c3fb27SDimitry Andric let Constraints = Constraint; 14335f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 143406c3fb27SDimitry Andric let HasVLOp = 1; 143506c3fb27SDimitry Andric let HasSEWOp = 1; 143606c3fb27SDimitry Andric} 143706c3fb27SDimitry Andric 1438fe6060f1SDimitry Andric// Like VPseudoBinaryMask, but output can be V0. 1439fe6060f1SDimitry Andricclass VPseudoBinaryMOutMask<VReg RetClass, 1440fe6060f1SDimitry Andric RegisterClass Op1Class, 1441fe6060f1SDimitry Andric DAGOperand Op2Class, 14425f757f3fSDimitry Andric string Constraint, 14435f757f3fSDimitry Andric int TargetConstraintType = 1> : 1444fe6060f1SDimitry Andric Pseudo<(outs RetClass:$rd), 1445fe6060f1SDimitry Andric (ins RetClass:$merge, 1446fe6060f1SDimitry Andric Op1Class:$rs2, Op2Class:$rs1, 1447fe6060f1SDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 1448fe6060f1SDimitry Andric RISCVVPseudo { 1449fe6060f1SDimitry Andric let mayLoad = 0; 1450fe6060f1SDimitry Andric let mayStore = 0; 1451fe6060f1SDimitry Andric let hasSideEffects = 0; 145206c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 14535f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1454fe6060f1SDimitry Andric let HasVLOp = 1; 1455fe6060f1SDimitry Andric let HasSEWOp = 1; 145681ad6265SDimitry Andric let UsesMaskPolicy = 1; 1457fe6060f1SDimitry Andric} 1458fe6060f1SDimitry Andric 1459fe6060f1SDimitry Andric// Special version of VPseudoBinaryMask where we pretend the first source is 1460fe6060f1SDimitry Andric// tied to the destination so we can workaround the earlyclobber constraint. 1461fe6060f1SDimitry Andric// This allows maskedoff and rs2 to be the same register. 1462fe6060f1SDimitry Andricclass VPseudoTiedBinaryMask<VReg RetClass, 1463fe6060f1SDimitry Andric DAGOperand Op2Class, 14645f757f3fSDimitry Andric string Constraint, 14655f757f3fSDimitry Andric int TargetConstraintType = 1> : 1466fe6060f1SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1467fe6060f1SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 1468fe6060f1SDimitry Andric Op2Class:$rs1, 1469349cc55cSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 1470fe6060f1SDimitry Andric RISCVVPseudo { 1471fe6060f1SDimitry Andric let mayLoad = 0; 1472fe6060f1SDimitry Andric let mayStore = 0; 1473fe6060f1SDimitry Andric let hasSideEffects = 0; 147406c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 14755f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1476fe6060f1SDimitry Andric let HasVLOp = 1; 1477fe6060f1SDimitry Andric let HasSEWOp = 1; 1478349cc55cSDimitry Andric let HasVecPolicyOp = 1; 147981ad6265SDimitry Andric let UsesMaskPolicy = 1; 148006c3fb27SDimitry Andric let IsTiedPseudo = 1; 148106c3fb27SDimitry Andric} 148206c3fb27SDimitry Andric 148306c3fb27SDimitry Andricclass VPseudoTiedBinaryMaskRoundingMode<VReg RetClass, 148406c3fb27SDimitry Andric DAGOperand Op2Class, 14855f757f3fSDimitry Andric string Constraint, 14865f757f3fSDimitry Andric int TargetConstraintType = 1> : 148706c3fb27SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 148806c3fb27SDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, 148906c3fb27SDimitry Andric Op2Class:$rs1, 149006c3fb27SDimitry Andric VMaskOp:$vm, 149106c3fb27SDimitry Andric ixlenimm:$rm, 149206c3fb27SDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 149306c3fb27SDimitry Andric RISCVVPseudo { 149406c3fb27SDimitry Andric let mayLoad = 0; 149506c3fb27SDimitry Andric let mayStore = 0; 149606c3fb27SDimitry Andric let hasSideEffects = 0; 149706c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 14985f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 149906c3fb27SDimitry Andric let HasVLOp = 1; 150006c3fb27SDimitry Andric let HasSEWOp = 1; 150106c3fb27SDimitry Andric let HasVecPolicyOp = 1; 150206c3fb27SDimitry Andric let UsesMaskPolicy = 1; 150306c3fb27SDimitry Andric let IsTiedPseudo = 1; 150406c3fb27SDimitry Andric let HasRoundModeOp = 1; 150506c3fb27SDimitry Andric let UsesVXRM = 0; 1506fe6060f1SDimitry Andric} 1507fe6060f1SDimitry Andric 1508e8d8bef9SDimitry Andricclass VPseudoBinaryCarryIn<VReg RetClass, 1509e8d8bef9SDimitry Andric VReg Op1Class, 1510e8d8bef9SDimitry Andric DAGOperand Op2Class, 1511e8d8bef9SDimitry Andric LMULInfo MInfo, 1512e8d8bef9SDimitry Andric bit CarryIn, 15135f757f3fSDimitry Andric string Constraint, 15145f757f3fSDimitry Andric int TargetConstraintType = 1> : 1515e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 1516e8d8bef9SDimitry Andric !if(CarryIn, 15175f757f3fSDimitry Andric (ins Op1Class:$rs2, Op2Class:$rs1, 15185f757f3fSDimitry Andric VMV0:$carry, AVL:$vl, ixlenimm:$sew), 15195f757f3fSDimitry Andric (ins Op1Class:$rs2, Op2Class:$rs1, 15205f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew)), []>, 1521e8d8bef9SDimitry Andric RISCVVPseudo { 1522e8d8bef9SDimitry Andric let mayLoad = 0; 1523e8d8bef9SDimitry Andric let mayStore = 0; 1524e8d8bef9SDimitry Andric let hasSideEffects = 0; 1525e8d8bef9SDimitry Andric let Constraints = Constraint; 15265f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1527e8d8bef9SDimitry Andric let HasVLOp = 1; 1528e8d8bef9SDimitry Andric let HasSEWOp = 1; 1529e8d8bef9SDimitry Andric let VLMul = MInfo.value; 1530e8d8bef9SDimitry Andric} 1531e8d8bef9SDimitry Andric 153204eeddc0SDimitry Andricclass VPseudoTiedBinaryCarryIn<VReg RetClass, 153304eeddc0SDimitry Andric VReg Op1Class, 153404eeddc0SDimitry Andric DAGOperand Op2Class, 153504eeddc0SDimitry Andric LMULInfo MInfo, 153604eeddc0SDimitry Andric bit CarryIn, 1537647cbc5dSDimitry Andric string Constraint, 1538647cbc5dSDimitry Andric int TargetConstraintType = 1> : 153904eeddc0SDimitry Andric Pseudo<(outs RetClass:$rd), 154004eeddc0SDimitry Andric !if(CarryIn, 15415f757f3fSDimitry Andric (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, 15425f757f3fSDimitry Andric VMV0:$carry, AVL:$vl, ixlenimm:$sew), 15435f757f3fSDimitry Andric (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, 15445f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew)), []>, 154504eeddc0SDimitry Andric RISCVVPseudo { 154604eeddc0SDimitry Andric let mayLoad = 0; 154704eeddc0SDimitry Andric let mayStore = 0; 154804eeddc0SDimitry Andric let hasSideEffects = 0; 154906c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $merge"], ","); 1550647cbc5dSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 155104eeddc0SDimitry Andric let HasVLOp = 1; 155204eeddc0SDimitry Andric let HasSEWOp = 1; 155304eeddc0SDimitry Andric let HasVecPolicyOp = 0; 155404eeddc0SDimitry Andric let VLMul = MInfo.value; 155504eeddc0SDimitry Andric} 155604eeddc0SDimitry Andric 1557e8d8bef9SDimitry Andricclass VPseudoTernaryNoMask<VReg RetClass, 1558fe6060f1SDimitry Andric RegisterClass Op1Class, 1559e8d8bef9SDimitry Andric DAGOperand Op2Class, 1560e8d8bef9SDimitry Andric string Constraint> : 1561e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 1562e8d8bef9SDimitry Andric (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, 15635f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew), []>, 1564e8d8bef9SDimitry Andric RISCVVPseudo { 1565e8d8bef9SDimitry Andric let mayLoad = 0; 1566e8d8bef9SDimitry Andric let mayStore = 0; 1567e8d8bef9SDimitry Andric let hasSideEffects = 0; 156806c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $rs3"], ","); 1569e8d8bef9SDimitry Andric let HasVLOp = 1; 1570e8d8bef9SDimitry Andric let HasSEWOp = 1; 1571e8d8bef9SDimitry Andric} 1572e8d8bef9SDimitry Andric 1573349cc55cSDimitry Andricclass VPseudoTernaryNoMaskWithPolicy<VReg RetClass, 1574349cc55cSDimitry Andric RegisterClass Op1Class, 1575349cc55cSDimitry Andric DAGOperand Op2Class, 15765f757f3fSDimitry Andric string Constraint, 15775f757f3fSDimitry Andric int TargetConstraintType = 1> : 1578349cc55cSDimitry Andric Pseudo<(outs RetClass:$rd), 1579349cc55cSDimitry Andric (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, 15805f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 1581349cc55cSDimitry Andric RISCVVPseudo { 1582349cc55cSDimitry Andric let mayLoad = 0; 1583349cc55cSDimitry Andric let mayStore = 0; 1584349cc55cSDimitry Andric let hasSideEffects = 0; 158506c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $rs3"], ","); 15865f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 1587349cc55cSDimitry Andric let HasVecPolicyOp = 1; 1588349cc55cSDimitry Andric let HasVLOp = 1; 1589349cc55cSDimitry Andric let HasSEWOp = 1; 159006c3fb27SDimitry Andric} 159106c3fb27SDimitry Andric 159206c3fb27SDimitry Andricclass VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass, 159306c3fb27SDimitry Andric RegisterClass Op1Class, 159406c3fb27SDimitry Andric DAGOperand Op2Class, 15955f757f3fSDimitry Andric string Constraint, 15965f757f3fSDimitry Andric int TargetConstraintType = 1> : 159706c3fb27SDimitry Andric Pseudo<(outs RetClass:$rd), 159806c3fb27SDimitry Andric (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, 15995f757f3fSDimitry Andric ixlenimm:$rm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 160006c3fb27SDimitry Andric RISCVVPseudo { 160106c3fb27SDimitry Andric let mayLoad = 0; 160206c3fb27SDimitry Andric let mayStore = 0; 160306c3fb27SDimitry Andric let hasSideEffects = 0; 160406c3fb27SDimitry Andric let Constraints = !interleave([Constraint, "$rd = $rs3"], ","); 16055f757f3fSDimitry Andric let TargetOverlapConstraintType = TargetConstraintType; 160606c3fb27SDimitry Andric let HasVecPolicyOp = 1; 160706c3fb27SDimitry Andric let HasVLOp = 1; 160806c3fb27SDimitry Andric let HasSEWOp = 1; 160906c3fb27SDimitry Andric let HasRoundModeOp = 1; 161006c3fb27SDimitry Andric let UsesVXRM = 0; 1611349cc55cSDimitry Andric} 1612349cc55cSDimitry Andric 16135f757f3fSDimitry Andricclass VPseudoUSSegLoadNoMask<VReg RetClass, 16145f757f3fSDimitry Andric int EEW, 16155f757f3fSDimitry Andric bits<4> NF> : 1616e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 161706c3fb27SDimitry Andric (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, 161806c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 1619e8d8bef9SDimitry Andric RISCVVPseudo, 162006c3fb27SDimitry Andric RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> { 1621e8d8bef9SDimitry Andric let mayLoad = 1; 1622e8d8bef9SDimitry Andric let mayStore = 0; 1623e8d8bef9SDimitry Andric let hasSideEffects = 0; 1624e8d8bef9SDimitry Andric let HasVLOp = 1; 1625e8d8bef9SDimitry Andric let HasSEWOp = 1; 162606c3fb27SDimitry Andric let HasVecPolicyOp = 1; 162781ad6265SDimitry Andric let Constraints = "$rd = $dest"; 162881ad6265SDimitry Andric} 162981ad6265SDimitry Andric 16305f757f3fSDimitry Andricclass VPseudoUSSegLoadMask<VReg RetClass, 16315f757f3fSDimitry Andric int EEW, 16325f757f3fSDimitry Andric bits<4> NF> : 1633e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1634bdd1243dSDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1, 1635349cc55cSDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, 1636e8d8bef9SDimitry Andric RISCVVPseudo, 163706c3fb27SDimitry Andric RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> { 1638e8d8bef9SDimitry Andric let mayLoad = 1; 1639e8d8bef9SDimitry Andric let mayStore = 0; 1640e8d8bef9SDimitry Andric let hasSideEffects = 0; 1641e8d8bef9SDimitry Andric let Constraints = "$rd = $merge"; 1642e8d8bef9SDimitry Andric let HasVLOp = 1; 1643e8d8bef9SDimitry Andric let HasSEWOp = 1; 1644349cc55cSDimitry Andric let HasVecPolicyOp = 1; 164581ad6265SDimitry Andric let UsesMaskPolicy = 1; 164681ad6265SDimitry Andric} 164781ad6265SDimitry Andric 16485f757f3fSDimitry Andricclass VPseudoUSSegLoadFFNoMask<VReg RetClass, 16495f757f3fSDimitry Andric int EEW, 16505f757f3fSDimitry Andric bits<4> NF> : 165181ad6265SDimitry Andric Pseudo<(outs RetClass:$rd, GPR:$vl), 165206c3fb27SDimitry Andric (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, 165306c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 165481ad6265SDimitry Andric RISCVVPseudo, 165506c3fb27SDimitry Andric RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> { 165681ad6265SDimitry Andric let mayLoad = 1; 165781ad6265SDimitry Andric let mayStore = 0; 165881ad6265SDimitry Andric let hasSideEffects = 0; 165981ad6265SDimitry Andric let HasVLOp = 1; 166081ad6265SDimitry Andric let HasSEWOp = 1; 166106c3fb27SDimitry Andric let HasVecPolicyOp = 1; 166281ad6265SDimitry Andric let Constraints = "$rd = $dest"; 166381ad6265SDimitry Andric} 166481ad6265SDimitry Andric 16655f757f3fSDimitry Andricclass VPseudoUSSegLoadFFMask<VReg RetClass, 16665f757f3fSDimitry Andric int EEW, 16675f757f3fSDimitry Andric bits<4> NF> : 166881ad6265SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl), 1669bdd1243dSDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1, 167081ad6265SDimitry Andric VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>, 167181ad6265SDimitry Andric RISCVVPseudo, 167206c3fb27SDimitry Andric RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> { 167381ad6265SDimitry Andric let mayLoad = 1; 167481ad6265SDimitry Andric let mayStore = 0; 167581ad6265SDimitry Andric let hasSideEffects = 0; 167681ad6265SDimitry Andric let Constraints = "$rd = $merge"; 167781ad6265SDimitry Andric let HasVLOp = 1; 167881ad6265SDimitry Andric let HasSEWOp = 1; 167981ad6265SDimitry Andric let HasVecPolicyOp = 1; 168081ad6265SDimitry Andric let UsesMaskPolicy = 1; 1681e8d8bef9SDimitry Andric} 1682e8d8bef9SDimitry Andric 16835f757f3fSDimitry Andricclass VPseudoSSegLoadNoMask<VReg RetClass, 16845f757f3fSDimitry Andric int EEW, 16855f757f3fSDimitry Andric bits<4> NF> : 1686e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 168706c3fb27SDimitry Andric (ins RetClass:$merge, GPRMem:$rs1, GPR:$offset, AVL:$vl, 168806c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 1689e8d8bef9SDimitry Andric RISCVVPseudo, 169006c3fb27SDimitry Andric RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> { 1691fe6060f1SDimitry Andric let mayLoad = 1; 1692e8d8bef9SDimitry Andric let mayStore = 0; 1693e8d8bef9SDimitry Andric let hasSideEffects = 0; 1694e8d8bef9SDimitry Andric let HasVLOp = 1; 1695e8d8bef9SDimitry Andric let HasSEWOp = 1; 169606c3fb27SDimitry Andric let HasVecPolicyOp = 1; 169781ad6265SDimitry Andric let Constraints = "$rd = $merge"; 1698e8d8bef9SDimitry Andric} 1699e8d8bef9SDimitry Andric 17005f757f3fSDimitry Andricclass VPseudoSSegLoadMask<VReg RetClass, 17015f757f3fSDimitry Andric int EEW, 17025f757f3fSDimitry Andric bits<4> NF> : 1703e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1704bdd1243dSDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1, 1705349cc55cSDimitry Andric GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, 1706349cc55cSDimitry Andric ixlenimm:$policy), []>, 1707e8d8bef9SDimitry Andric RISCVVPseudo, 170806c3fb27SDimitry Andric RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> { 1709e8d8bef9SDimitry Andric let mayLoad = 1; 1710e8d8bef9SDimitry Andric let mayStore = 0; 1711e8d8bef9SDimitry Andric let hasSideEffects = 0; 1712e8d8bef9SDimitry Andric let Constraints = "$rd = $merge"; 1713e8d8bef9SDimitry Andric let HasVLOp = 1; 1714e8d8bef9SDimitry Andric let HasSEWOp = 1; 1715349cc55cSDimitry Andric let HasVecPolicyOp = 1; 171681ad6265SDimitry Andric let UsesMaskPolicy = 1; 1717e8d8bef9SDimitry Andric} 1718e8d8bef9SDimitry Andric 17195f757f3fSDimitry Andricclass VPseudoISegLoadNoMask<VReg RetClass, 17205f757f3fSDimitry Andric VReg IdxClass, 17215f757f3fSDimitry Andric int EEW, 17225f757f3fSDimitry Andric bits<3> LMUL, 17235f757f3fSDimitry Andric bits<4> NF, 17245f757f3fSDimitry Andric bit Ordered> : 1725e8d8bef9SDimitry Andric Pseudo<(outs RetClass:$rd), 172606c3fb27SDimitry Andric (ins RetClass:$merge, GPRMem:$rs1, IdxClass:$offset, AVL:$vl, 172706c3fb27SDimitry Andric ixlenimm:$sew, ixlenimm:$policy), []>, 1728e8d8bef9SDimitry Andric RISCVVPseudo, 172906c3fb27SDimitry Andric RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> { 173081ad6265SDimitry Andric let mayLoad = 1; 173181ad6265SDimitry Andric let mayStore = 0; 173281ad6265SDimitry Andric let hasSideEffects = 0; 173381ad6265SDimitry Andric // For vector indexed segment loads, the destination vector register groups 173481ad6265SDimitry Andric // cannot overlap the source vector register group 173581ad6265SDimitry Andric let Constraints = "@earlyclobber $rd, $rd = $merge"; 173681ad6265SDimitry Andric let HasVLOp = 1; 173781ad6265SDimitry Andric let HasSEWOp = 1; 173806c3fb27SDimitry Andric let HasVecPolicyOp = 1; 1739e8d8bef9SDimitry Andric} 1740e8d8bef9SDimitry Andric 17415f757f3fSDimitry Andricclass VPseudoISegLoadMask<VReg RetClass, 17425f757f3fSDimitry Andric VReg IdxClass, 17435f757f3fSDimitry Andric int EEW, 17445f757f3fSDimitry Andric bits<3> LMUL, 17455f757f3fSDimitry Andric bits<4> NF, 17465f757f3fSDimitry Andric bit Ordered> : 1747e8d8bef9SDimitry Andric Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), 1748bdd1243dSDimitry Andric (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1, 1749349cc55cSDimitry Andric IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, 1750349cc55cSDimitry Andric ixlenimm:$policy), []>, 1751e8d8bef9SDimitry Andric RISCVVPseudo, 175206c3fb27SDimitry Andric RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> { 1753e8d8bef9SDimitry Andric let mayLoad = 1; 1754e8d8bef9SDimitry Andric let mayStore = 0; 1755e8d8bef9SDimitry Andric let hasSideEffects = 0; 1756e8d8bef9SDimitry Andric // For vector indexed segment loads, the destination vector register groups 1757e8d8bef9SDimitry Andric // cannot overlap the source vector register group 1758e8d8bef9SDimitry Andric let Constraints = "@earlyclobber $rd, $rd = $merge"; 1759e8d8bef9SDimitry Andric let HasVLOp = 1; 1760e8d8bef9SDimitry Andric let HasSEWOp = 1; 1761349cc55cSDimitry Andric let HasVecPolicyOp = 1; 176281ad6265SDimitry Andric let UsesMaskPolicy = 1; 1763e8d8bef9SDimitry Andric} 1764e8d8bef9SDimitry Andric 17655f757f3fSDimitry Andricclass VPseudoUSSegStoreNoMask<VReg ValClass, 17665f757f3fSDimitry Andric int EEW, 17675f757f3fSDimitry Andric bits<4> NF> : 1768e8d8bef9SDimitry Andric Pseudo<(outs), 1769bdd1243dSDimitry Andric (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>, 1770e8d8bef9SDimitry Andric RISCVVPseudo, 177106c3fb27SDimitry Andric RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> { 1772e8d8bef9SDimitry Andric let mayLoad = 0; 1773e8d8bef9SDimitry Andric let mayStore = 1; 1774e8d8bef9SDimitry Andric let hasSideEffects = 0; 1775e8d8bef9SDimitry Andric let HasVLOp = 1; 1776e8d8bef9SDimitry Andric let HasSEWOp = 1; 1777e8d8bef9SDimitry Andric} 1778e8d8bef9SDimitry Andric 17795f757f3fSDimitry Andricclass VPseudoUSSegStoreMask<VReg ValClass, 17805f757f3fSDimitry Andric int EEW, 17815f757f3fSDimitry Andric bits<4> NF> : 1782e8d8bef9SDimitry Andric Pseudo<(outs), 1783bdd1243dSDimitry Andric (ins ValClass:$rd, GPRMem:$rs1, 1784fe6060f1SDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 1785e8d8bef9SDimitry Andric RISCVVPseudo, 178606c3fb27SDimitry Andric RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> { 1787e8d8bef9SDimitry Andric let mayLoad = 0; 1788e8d8bef9SDimitry Andric let mayStore = 1; 1789e8d8bef9SDimitry Andric let hasSideEffects = 0; 1790e8d8bef9SDimitry Andric let HasVLOp = 1; 1791e8d8bef9SDimitry Andric let HasSEWOp = 1; 1792e8d8bef9SDimitry Andric} 1793e8d8bef9SDimitry Andric 17945f757f3fSDimitry Andricclass VPseudoSSegStoreNoMask<VReg ValClass, 17955f757f3fSDimitry Andric int EEW, 17965f757f3fSDimitry Andric bits<4> NF> : 1797e8d8bef9SDimitry Andric Pseudo<(outs), 17985f757f3fSDimitry Andric (ins ValClass:$rd, GPRMem:$rs1, GPR:$offset, 17995f757f3fSDimitry Andric AVL:$vl, ixlenimm:$sew), []>, 1800e8d8bef9SDimitry Andric RISCVVPseudo, 180106c3fb27SDimitry Andric RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> { 1802e8d8bef9SDimitry Andric let mayLoad = 0; 1803e8d8bef9SDimitry Andric let mayStore = 1; 1804e8d8bef9SDimitry Andric let hasSideEffects = 0; 1805e8d8bef9SDimitry Andric let HasVLOp = 1; 1806e8d8bef9SDimitry Andric let HasSEWOp = 1; 1807e8d8bef9SDimitry Andric} 1808e8d8bef9SDimitry Andric 18095f757f3fSDimitry Andricclass VPseudoSSegStoreMask<VReg ValClass, 18105f757f3fSDimitry Andric int EEW, 18115f757f3fSDimitry Andric bits<4> NF> : 1812e8d8bef9SDimitry Andric Pseudo<(outs), 1813bdd1243dSDimitry Andric (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset, 1814fe6060f1SDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 1815e8d8bef9SDimitry Andric RISCVVPseudo, 181606c3fb27SDimitry Andric RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> { 1817e8d8bef9SDimitry Andric let mayLoad = 0; 1818e8d8bef9SDimitry Andric let mayStore = 1; 1819e8d8bef9SDimitry Andric let hasSideEffects = 0; 1820e8d8bef9SDimitry Andric let HasVLOp = 1; 1821e8d8bef9SDimitry Andric let HasSEWOp = 1; 1822e8d8bef9SDimitry Andric} 1823e8d8bef9SDimitry Andric 18245f757f3fSDimitry Andricclass VPseudoISegStoreNoMask<VReg ValClass, 18255f757f3fSDimitry Andric VReg IdxClass, 18265f757f3fSDimitry Andric int EEW, 18275f757f3fSDimitry Andric bits<3> LMUL, 18285f757f3fSDimitry Andric bits<4> NF, 18295f757f3fSDimitry Andric bit Ordered> : 1830e8d8bef9SDimitry Andric Pseudo<(outs), 1831bdd1243dSDimitry Andric (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, 1832fe6060f1SDimitry Andric AVL:$vl, ixlenimm:$sew), []>, 1833e8d8bef9SDimitry Andric RISCVVPseudo, 183406c3fb27SDimitry Andric RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> { 1835e8d8bef9SDimitry Andric let mayLoad = 0; 1836e8d8bef9SDimitry Andric let mayStore = 1; 1837e8d8bef9SDimitry Andric let hasSideEffects = 0; 1838e8d8bef9SDimitry Andric let HasVLOp = 1; 1839e8d8bef9SDimitry Andric let HasSEWOp = 1; 1840e8d8bef9SDimitry Andric} 1841e8d8bef9SDimitry Andric 18425f757f3fSDimitry Andricclass VPseudoISegStoreMask<VReg ValClass, 18435f757f3fSDimitry Andric VReg IdxClass, 18445f757f3fSDimitry Andric int EEW, 18455f757f3fSDimitry Andric bits<3> LMUL, 18465f757f3fSDimitry Andric bits<4> NF, 18475f757f3fSDimitry Andric bit Ordered> : 1848e8d8bef9SDimitry Andric Pseudo<(outs), 1849bdd1243dSDimitry Andric (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, 1850fe6060f1SDimitry Andric VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, 1851e8d8bef9SDimitry Andric RISCVVPseudo, 185206c3fb27SDimitry Andric RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> { 1853e8d8bef9SDimitry Andric let mayLoad = 0; 1854e8d8bef9SDimitry Andric let mayStore = 1; 1855e8d8bef9SDimitry Andric let hasSideEffects = 0; 1856e8d8bef9SDimitry Andric let HasVLOp = 1; 1857e8d8bef9SDimitry Andric let HasSEWOp = 1; 1858e8d8bef9SDimitry Andric} 1859e8d8bef9SDimitry Andric 18600eae32dcSDimitry Andricmulticlass VPseudoUSLoad { 1861fe6060f1SDimitry Andric foreach eew = EEWList in { 1862fe6060f1SDimitry Andric foreach lmul = MxSet<eew>.m in { 1863e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 1864e8d8bef9SDimitry Andric defvar vreg = lmul.vrclass; 186506c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 18660eae32dcSDimitry Andric def "E" # eew # "_V_" # LInfo : 186781ad6265SDimitry Andric VPseudoUSLoadNoMask<vreg, eew>, 1868bdd1243dSDimitry Andric VLESched<LInfo>; 18690eae32dcSDimitry Andric def "E" # eew # "_V_" # LInfo # "_MASK" : 187081ad6265SDimitry Andric VPseudoUSLoadMask<vreg, eew>, 187106c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>, 1872bdd1243dSDimitry Andric VLESched<LInfo>; 18730eae32dcSDimitry Andric } 18740eae32dcSDimitry Andric } 18750eae32dcSDimitry Andric } 18760eae32dcSDimitry Andric} 18770eae32dcSDimitry Andric 18780eae32dcSDimitry Andricmulticlass VPseudoFFLoad { 18790eae32dcSDimitry Andric foreach eew = EEWList in { 18800eae32dcSDimitry Andric foreach lmul = MxSet<eew>.m in { 18810eae32dcSDimitry Andric defvar LInfo = lmul.MX; 18820eae32dcSDimitry Andric defvar vreg = lmul.vrclass; 188306c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 18840eae32dcSDimitry Andric def "E" # eew # "FF_V_" # LInfo: 188581ad6265SDimitry Andric VPseudoUSLoadFFNoMask<vreg, eew>, 1886bdd1243dSDimitry Andric VLFSched<LInfo>; 18870eae32dcSDimitry Andric def "E" # eew # "FF_V_" # LInfo # "_MASK": 188881ad6265SDimitry Andric VPseudoUSLoadFFMask<vreg, eew>, 188906c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>, 1890bdd1243dSDimitry Andric VLFSched<LInfo>; 1891fe6060f1SDimitry Andric } 1892e8d8bef9SDimitry Andric } 1893e8d8bef9SDimitry Andric } 1894e8d8bef9SDimitry Andric} 1895e8d8bef9SDimitry Andric 1896d409305fSDimitry Andricmulticlass VPseudoLoadMask { 1897d409305fSDimitry Andric foreach mti = AllMasks in { 1898bdd1243dSDimitry Andric defvar mx = mti.LMul.MX; 1899bdd1243dSDimitry Andric defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx); 1900d409305fSDimitry Andric let VLMul = mti.LMul.value in { 190106c3fb27SDimitry Andric def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1>, 190206c3fb27SDimitry Andric Sched<[WriteVLDM_MX, ReadVLDX]>; 1903d409305fSDimitry Andric } 1904d409305fSDimitry Andric } 1905d409305fSDimitry Andric} 1906d409305fSDimitry Andric 1907e8d8bef9SDimitry Andricmulticlass VPseudoSLoad { 1908fe6060f1SDimitry Andric foreach eew = EEWList in { 1909fe6060f1SDimitry Andric foreach lmul = MxSet<eew>.m in { 1910e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 1911e8d8bef9SDimitry Andric defvar vreg = lmul.vrclass; 191206c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 19130eae32dcSDimitry Andric def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>, 1914bdd1243dSDimitry Andric VLSSched<eew, LInfo>; 1915bdd1243dSDimitry Andric def "E" # eew # "_V_" # LInfo # "_MASK" : 1916bdd1243dSDimitry Andric VPseudoSLoadMask<vreg, eew>, 191706c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>, 1918bdd1243dSDimitry Andric VLSSched<eew, LInfo>; 1919fe6060f1SDimitry Andric } 1920e8d8bef9SDimitry Andric } 1921e8d8bef9SDimitry Andric } 1922e8d8bef9SDimitry Andric} 1923e8d8bef9SDimitry Andric 1924fe6060f1SDimitry Andricmulticlass VPseudoILoad<bit Ordered> { 192506c3fb27SDimitry Andric foreach idxEEW = EEWList in { 192606c3fb27SDimitry Andric foreach dataEEW = EEWList in { 192706c3fb27SDimitry Andric foreach dataEMUL = MxSet<dataEEW>.m in { 192806c3fb27SDimitry Andric defvar dataEMULOctuple = dataEMUL.octuple; 1929fe6060f1SDimitry Andric // Calculate emul = eew * lmul / sew 193006c3fb27SDimitry Andric defvar idxEMULOctuple = 193106c3fb27SDimitry Andric !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW)); 193206c3fb27SDimitry Andric if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then { 193306c3fb27SDimitry Andric defvar DataLInfo = dataEMUL.MX; 193406c3fb27SDimitry Andric defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret; 193506c3fb27SDimitry Andric defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo); 193606c3fb27SDimitry Andric defvar Vreg = dataEMUL.vrclass; 193706c3fb27SDimitry Andric defvar IdxVreg = idxEMUL.vrclass; 193806c3fb27SDimitry Andric defvar HasConstraint = !ne(dataEEW, idxEEW); 19395f757f3fSDimitry Andric defvar TypeConstraints = 19405f757f3fSDimitry Andric !if(!eq(dataEEW, idxEEW), 1, !if(!gt(dataEEW, idxEEW), !if(!ge(idxEMULOctuple, 8), 3, 1), 2)); 194106c3fb27SDimitry Andric let VLMul = dataEMUL.value in { 194206c3fb27SDimitry Andric def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo : 19435f757f3fSDimitry Andric VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>, 19445f757f3fSDimitry Andric VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>; 194506c3fb27SDimitry Andric def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" : 19465f757f3fSDimitry Andric VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>, 194706c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>, 19485f757f3fSDimitry Andric VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>; 1949fe6060f1SDimitry Andric } 1950fe6060f1SDimitry Andric } 1951fe6060f1SDimitry Andric } 1952e8d8bef9SDimitry Andric } 1953e8d8bef9SDimitry Andric } 1954e8d8bef9SDimitry Andric} 1955e8d8bef9SDimitry Andric 1956e8d8bef9SDimitry Andricmulticlass VPseudoUSStore { 1957fe6060f1SDimitry Andric foreach eew = EEWList in { 1958fe6060f1SDimitry Andric foreach lmul = MxSet<eew>.m in { 1959e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 1960e8d8bef9SDimitry Andric defvar vreg = lmul.vrclass; 196106c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 19620eae32dcSDimitry Andric def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>, 1963bdd1243dSDimitry Andric VSESched<LInfo>; 19640eae32dcSDimitry Andric def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>, 1965bdd1243dSDimitry Andric VSESched<LInfo>; 1966fe6060f1SDimitry Andric } 1967e8d8bef9SDimitry Andric } 1968e8d8bef9SDimitry Andric } 1969e8d8bef9SDimitry Andric} 1970e8d8bef9SDimitry Andric 1971d409305fSDimitry Andricmulticlass VPseudoStoreMask { 1972d409305fSDimitry Andric foreach mti = AllMasks in { 1973bdd1243dSDimitry Andric defvar mx = mti.LMul.MX; 1974bdd1243dSDimitry Andric defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx); 1975d409305fSDimitry Andric let VLMul = mti.LMul.value in { 197606c3fb27SDimitry Andric def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1>, 197706c3fb27SDimitry Andric Sched<[WriteVSTM_MX, ReadVSTX]>; 1978d409305fSDimitry Andric } 1979d409305fSDimitry Andric } 1980d409305fSDimitry Andric} 1981d409305fSDimitry Andric 1982e8d8bef9SDimitry Andricmulticlass VPseudoSStore { 1983fe6060f1SDimitry Andric foreach eew = EEWList in { 1984fe6060f1SDimitry Andric foreach lmul = MxSet<eew>.m in { 1985e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 1986e8d8bef9SDimitry Andric defvar vreg = lmul.vrclass; 198706c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 19880eae32dcSDimitry Andric def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>, 1989bdd1243dSDimitry Andric VSSSched<eew, LInfo>; 19900eae32dcSDimitry Andric def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>, 1991bdd1243dSDimitry Andric VSSSched<eew, LInfo>; 1992fe6060f1SDimitry Andric } 1993e8d8bef9SDimitry Andric } 1994e8d8bef9SDimitry Andric } 1995e8d8bef9SDimitry Andric} 1996e8d8bef9SDimitry Andric 1997fe6060f1SDimitry Andricmulticlass VPseudoIStore<bit Ordered> { 199806c3fb27SDimitry Andric foreach idxEEW = EEWList in { 199906c3fb27SDimitry Andric foreach dataEEW = EEWList in { 200006c3fb27SDimitry Andric foreach dataEMUL = MxSet<dataEEW>.m in { 200106c3fb27SDimitry Andric defvar dataEMULOctuple = dataEMUL.octuple; 2002fe6060f1SDimitry Andric // Calculate emul = eew * lmul / sew 200306c3fb27SDimitry Andric defvar idxEMULOctuple = 200406c3fb27SDimitry Andric !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW)); 200506c3fb27SDimitry Andric if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then { 200606c3fb27SDimitry Andric defvar DataLInfo = dataEMUL.MX; 200706c3fb27SDimitry Andric defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret; 200806c3fb27SDimitry Andric defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo); 200906c3fb27SDimitry Andric defvar Vreg = dataEMUL.vrclass; 201006c3fb27SDimitry Andric defvar IdxVreg = idxEMUL.vrclass; 201106c3fb27SDimitry Andric let VLMul = dataEMUL.value in { 201206c3fb27SDimitry Andric def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo : 201306c3fb27SDimitry Andric VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>, 20145f757f3fSDimitry Andric VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>; 201506c3fb27SDimitry Andric def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" : 201606c3fb27SDimitry Andric VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>, 20175f757f3fSDimitry Andric VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>; 2018fe6060f1SDimitry Andric } 2019fe6060f1SDimitry Andric } 2020fe6060f1SDimitry Andric } 2021e8d8bef9SDimitry Andric } 2022e8d8bef9SDimitry Andric } 2023e8d8bef9SDimitry Andric} 2024e8d8bef9SDimitry Andric 20250eae32dcSDimitry Andricmulticlass VPseudoVPOP_M { 202606c3fb27SDimitry Andric foreach mti = AllMasks in { 2027bdd1243dSDimitry Andric defvar mx = mti.LMul.MX; 2028e8d8bef9SDimitry Andric let VLMul = mti.LMul.value in { 202906c3fb27SDimitry Andric def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut, 20305f757f3fSDimitry Andric SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>; 203106c3fb27SDimitry Andric def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut, 20325f757f3fSDimitry Andric SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>; 2033e8d8bef9SDimitry Andric } 2034e8d8bef9SDimitry Andric } 2035e8d8bef9SDimitry Andric} 2036e8d8bef9SDimitry Andric 20370eae32dcSDimitry Andricmulticlass VPseudoV1ST_M { 203806c3fb27SDimitry Andric foreach mti = AllMasks in { 2039bdd1243dSDimitry Andric defvar mx = mti.LMul.MX; 20400eae32dcSDimitry Andric let VLMul = mti.LMul.value in { 204106c3fb27SDimitry Andric def "_M_" #mti.BX : VPseudoUnaryNoMaskGPROut, 20425f757f3fSDimitry Andric SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>; 204306c3fb27SDimitry Andric def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut, 20445f757f3fSDimitry Andric SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>; 20450eae32dcSDimitry Andric } 20460eae32dcSDimitry Andric } 20470eae32dcSDimitry Andric} 20480eae32dcSDimitry Andric 20490eae32dcSDimitry Andricmulticlass VPseudoVSFS_M { 2050e8d8bef9SDimitry Andric defvar constraint = "@earlyclobber $rd"; 205106c3fb27SDimitry Andric foreach mti = AllMasks in { 2052bdd1243dSDimitry Andric defvar mx = mti.LMul.MX; 2053e8d8bef9SDimitry Andric let VLMul = mti.LMul.value in { 20540eae32dcSDimitry Andric def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>, 20555f757f3fSDimitry Andric SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx, 20565f757f3fSDimitry Andric forceMergeOpRead=true>; 20570eae32dcSDimitry Andric def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>, 20585f757f3fSDimitry Andric SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx, 20595f757f3fSDimitry Andric forceMergeOpRead=true>; 2060e8d8bef9SDimitry Andric } 2061e8d8bef9SDimitry Andric } 2062e8d8bef9SDimitry Andric} 2063e8d8bef9SDimitry Andric 20640eae32dcSDimitry Andricmulticlass VPseudoVID_V { 206504eeddc0SDimitry Andric foreach m = MxList in { 2066bdd1243dSDimitry Andric defvar mx = m.MX; 2067e8d8bef9SDimitry Andric let VLMul = m.value in { 20685f757f3fSDimitry Andric def "_V_" # mx : VPseudoNullaryNoMask<m.vrclass>, 20695f757f3fSDimitry Andric SchedNullary<"WriteVMIdxV", mx, forceMergeOpRead=true>; 20705f757f3fSDimitry Andric def "_V_" # mx # "_MASK" : VPseudoNullaryMask<m.vrclass>, 207106c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=1>, 20725f757f3fSDimitry Andric SchedNullary<"WriteVMIdxV", mx, 20735f757f3fSDimitry Andric forceMergeOpRead=true>; 2074e8d8bef9SDimitry Andric } 2075e8d8bef9SDimitry Andric } 2076e8d8bef9SDimitry Andric} 2077e8d8bef9SDimitry Andric 2078e8d8bef9SDimitry Andricmulticlass VPseudoNullaryPseudoM <string BaseInst> { 2079e8d8bef9SDimitry Andric foreach mti = AllMasks in { 2080e8d8bef9SDimitry Andric let VLMul = mti.LMul.value in { 2081bdd1243dSDimitry Andric def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">, 20825f757f3fSDimitry Andric SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mti.LMul.MX>; 2083e8d8bef9SDimitry Andric } 2084e8d8bef9SDimitry Andric } 2085e8d8bef9SDimitry Andric} 2086e8d8bef9SDimitry Andric 20870eae32dcSDimitry Andricmulticlass VPseudoVIOT_M { 2088e8d8bef9SDimitry Andric defvar constraint = "@earlyclobber $rd"; 208904eeddc0SDimitry Andric foreach m = MxList in { 2090bdd1243dSDimitry Andric defvar mx = m.MX; 2091e8d8bef9SDimitry Andric let VLMul = m.value in { 20925f757f3fSDimitry Andric def "_" # mx : VPseudoUnaryNoMask<m.vrclass, VR, constraint>, 20935f757f3fSDimitry Andric SchedUnary<"WriteVMIotV", "ReadVMIotV", mx, 20945f757f3fSDimitry Andric forceMergeOpRead=true>; 20955f757f3fSDimitry Andric def "_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>, 20965f757f3fSDimitry Andric RISCVMaskedPseudo<MaskIdx=2, MaskAffectsRes=true>, 20975f757f3fSDimitry Andric SchedUnary<"WriteVMIotV", "ReadVMIotV", mx, 20985f757f3fSDimitry Andric forceMergeOpRead=true>; 2099e8d8bef9SDimitry Andric } 2100e8d8bef9SDimitry Andric } 2101e8d8bef9SDimitry Andric} 2102e8d8bef9SDimitry Andric 21030eae32dcSDimitry Andricmulticlass VPseudoVCPR_V { 210404eeddc0SDimitry Andric foreach m = MxList in { 2105bdd1243dSDimitry Andric defvar mx = m.MX; 210606c3fb27SDimitry Andric defvar sews = SchedSEWSet<mx>.val; 2107e8d8bef9SDimitry Andric let VLMul = m.value in 210806c3fb27SDimitry Andric foreach e = sews in { 210906c3fb27SDimitry Andric defvar suffix = "_" # m.MX # "_E" # e; 211006c3fb27SDimitry Andric let SEW = e in 21115f757f3fSDimitry Andric def _VM # suffix 21125f757f3fSDimitry Andric : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>, 21135f757f3fSDimitry Andric SchedBinary<"WriteVCompressV", "ReadVCompressV", "ReadVCompressV", 21145f757f3fSDimitry Andric mx, e>; 211506c3fb27SDimitry Andric } 2116e8d8bef9SDimitry Andric } 2117e8d8bef9SDimitry Andric} 2118e8d8bef9SDimitry Andric 2119e8d8bef9SDimitry Andricmulticlass VPseudoBinary<VReg RetClass, 2120e8d8bef9SDimitry Andric VReg Op1Class, 2121e8d8bef9SDimitry Andric DAGOperand Op2Class, 2122e8d8bef9SDimitry Andric LMULInfo MInfo, 212306c3fb27SDimitry Andric string Constraint = "", 21245f757f3fSDimitry Andric int sew = 0, 21255f757f3fSDimitry Andric int TargetConstraintType = 1> { 21265f757f3fSDimitry Andric let VLMul = MInfo.value, SEW=sew in { 21275f757f3fSDimitry Andric defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); 21285f757f3fSDimitry Andric def suffix : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class, 21295f757f3fSDimitry Andric Constraint, TargetConstraintType>; 21305f757f3fSDimitry Andric def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, 21315f757f3fSDimitry Andric Constraint, TargetConstraintType>, 21325f757f3fSDimitry Andric RISCVMaskedPseudo<MaskIdx=3>; 21335f757f3fSDimitry Andric } 21345f757f3fSDimitry Andric} 21355f757f3fSDimitry Andric 21365f757f3fSDimitry Andricmulticlass VPseudoBinaryNoMask<VReg RetClass, 21375f757f3fSDimitry Andric VReg Op1Class, 21385f757f3fSDimitry Andric DAGOperand Op2Class, 21395f757f3fSDimitry Andric LMULInfo MInfo, 21405f757f3fSDimitry Andric string Constraint = "", 214106c3fb27SDimitry Andric int sew = 0> { 214206c3fb27SDimitry Andric let VLMul = MInfo.value, SEW=sew in { 214306c3fb27SDimitry Andric defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); 214406c3fb27SDimitry Andric def suffix : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class, 2145e8d8bef9SDimitry Andric Constraint>; 2146e8d8bef9SDimitry Andric } 2147e8d8bef9SDimitry Andric} 2148e8d8bef9SDimitry Andric 214906c3fb27SDimitry Andricmulticlass VPseudoBinaryRoundingMode<VReg RetClass, 215006c3fb27SDimitry Andric VReg Op1Class, 215106c3fb27SDimitry Andric DAGOperand Op2Class, 215206c3fb27SDimitry Andric LMULInfo MInfo, 215306c3fb27SDimitry Andric string Constraint = "", 215406c3fb27SDimitry Andric int sew = 0, 21555f757f3fSDimitry Andric int UsesVXRM = 1, 21565f757f3fSDimitry Andric int TargetConstraintType = 1> { 215706c3fb27SDimitry Andric let VLMul = MInfo.value, SEW=sew in { 215806c3fb27SDimitry Andric defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); 215906c3fb27SDimitry Andric def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class, 21605f757f3fSDimitry Andric Constraint, UsesVXRM, 21615f757f3fSDimitry Andric TargetConstraintType>; 216206c3fb27SDimitry Andric def suffix # "_MASK" : VPseudoBinaryMaskPolicyRoundingMode<RetClass, 216306c3fb27SDimitry Andric Op1Class, 216406c3fb27SDimitry Andric Op2Class, 216506c3fb27SDimitry Andric Constraint, 21665f757f3fSDimitry Andric UsesVXRM, 21675f757f3fSDimitry Andric TargetConstraintType>, 216806c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>; 216906c3fb27SDimitry Andric } 217006c3fb27SDimitry Andric} 217106c3fb27SDimitry Andric 217206c3fb27SDimitry Andric 2173fe6060f1SDimitry Andricmulticlass VPseudoBinaryM<VReg RetClass, 2174fe6060f1SDimitry Andric VReg Op1Class, 2175fe6060f1SDimitry Andric DAGOperand Op2Class, 2176fe6060f1SDimitry Andric LMULInfo MInfo, 21775f757f3fSDimitry Andric string Constraint = "", 21785f757f3fSDimitry Andric int TargetConstraintType = 1> { 2179fe6060f1SDimitry Andric let VLMul = MInfo.value in { 218006c3fb27SDimitry Andric def "_" # MInfo.MX : VPseudoBinaryMOutNoMask<RetClass, Op1Class, Op2Class, 21815f757f3fSDimitry Andric Constraint, TargetConstraintType>; 2182fe6060f1SDimitry Andric let ForceTailAgnostic = true in 2183fe6060f1SDimitry Andric def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class, 21845f757f3fSDimitry Andric Op2Class, Constraint, TargetConstraintType>, 218506c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>; 2186fe6060f1SDimitry Andric } 2187fe6060f1SDimitry Andric} 2188fe6060f1SDimitry Andric 2189e8d8bef9SDimitry Andricmulticlass VPseudoBinaryEmul<VReg RetClass, 2190e8d8bef9SDimitry Andric VReg Op1Class, 2191e8d8bef9SDimitry Andric DAGOperand Op2Class, 2192e8d8bef9SDimitry Andric LMULInfo lmul, 2193e8d8bef9SDimitry Andric LMULInfo emul, 219406c3fb27SDimitry Andric string Constraint = "", 219506c3fb27SDimitry Andric int sew = 0> { 219606c3fb27SDimitry Andric let VLMul = lmul.value, SEW=sew in { 219706c3fb27SDimitry Andric defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX); 219806c3fb27SDimitry Andric def suffix # "_" # emul.MX : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class, 2199e8d8bef9SDimitry Andric Constraint>; 220006c3fb27SDimitry Andric def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, 220181ad6265SDimitry Andric Constraint>, 220206c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>; 2203e8d8bef9SDimitry Andric } 2204e8d8bef9SDimitry Andric} 2205e8d8bef9SDimitry Andric 2206fe6060f1SDimitry Andricmulticlass VPseudoTiedBinary<VReg RetClass, 2207fe6060f1SDimitry Andric DAGOperand Op2Class, 2208fe6060f1SDimitry Andric LMULInfo MInfo, 22095f757f3fSDimitry Andric string Constraint = "", 22105f757f3fSDimitry Andric int TargetConstraintType = 1> { 2211fe6060f1SDimitry Andric let VLMul = MInfo.value in { 2212fe6060f1SDimitry Andric def "_" # MInfo.MX # "_TIED": VPseudoTiedBinaryNoMask<RetClass, Op2Class, 22135f757f3fSDimitry Andric Constraint, TargetConstraintType>; 2214fe6060f1SDimitry Andric def "_" # MInfo.MX # "_MASK_TIED" : VPseudoTiedBinaryMask<RetClass, Op2Class, 22155f757f3fSDimitry Andric Constraint, TargetConstraintType>; 2216fe6060f1SDimitry Andric } 2217fe6060f1SDimitry Andric} 2218fe6060f1SDimitry Andric 221906c3fb27SDimitry Andricmulticlass VPseudoTiedBinaryRoundingMode<VReg RetClass, 222006c3fb27SDimitry Andric DAGOperand Op2Class, 222106c3fb27SDimitry Andric LMULInfo MInfo, 22225f757f3fSDimitry Andric string Constraint = "", 22235f757f3fSDimitry Andric int TargetConstraintType = 1> { 222406c3fb27SDimitry Andric let VLMul = MInfo.value in { 222506c3fb27SDimitry Andric def "_" # MInfo.MX # "_TIED": 22265f757f3fSDimitry Andric VPseudoTiedBinaryNoMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>; 222706c3fb27SDimitry Andric def "_" # MInfo.MX # "_MASK_TIED" : 22285f757f3fSDimitry Andric VPseudoTiedBinaryMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>; 222906c3fb27SDimitry Andric } 223006c3fb27SDimitry Andric} 223106c3fb27SDimitry Andric 223206c3fb27SDimitry Andric 223306c3fb27SDimitry Andricmulticlass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0> { 223406c3fb27SDimitry Andric defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew>; 223506c3fb27SDimitry Andric} 223606c3fb27SDimitry Andric 223706c3fb27SDimitry Andricmulticlass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = ""> { 223806c3fb27SDimitry Andric defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint>; 223904eeddc0SDimitry Andric} 224004eeddc0SDimitry Andric 224104eeddc0SDimitry Andric// Similar to VPseudoBinaryV_VV, but uses MxListF. 224206c3fb27SDimitry Andricmulticlass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = "", int sew = 0> { 224306c3fb27SDimitry Andric defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew>; 224406c3fb27SDimitry Andric} 224506c3fb27SDimitry Andric 224606c3fb27SDimitry Andricmulticlass VPseudoBinaryFV_VV_RM<LMULInfo m, string Constraint = "", int sew = 0> { 224706c3fb27SDimitry Andric defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, 224806c3fb27SDimitry Andric Constraint, sew, 224906c3fb27SDimitry Andric UsesVXRM=0>; 2250e8d8bef9SDimitry Andric} 2251e8d8bef9SDimitry Andric 22520eae32dcSDimitry Andricmulticlass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> { 225304eeddc0SDimitry Andric foreach m = MxList in { 2254bdd1243dSDimitry Andric defvar mx = m.MX; 2255e8d8bef9SDimitry Andric foreach sew = EEWList in { 225606c3fb27SDimitry Andric defvar dataEMULOctuple = m.octuple; 2257e8d8bef9SDimitry Andric // emul = lmul * eew / sew 225806c3fb27SDimitry Andric defvar idxEMULOctuple = !srl(!mul(dataEMULOctuple, eew), !logtwo(sew)); 225906c3fb27SDimitry Andric if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then { 226006c3fb27SDimitry Andric defvar emulMX = octuple_to_str<idxEMULOctuple>.ret; 2261e8d8bef9SDimitry Andric defvar emul = !cast<LMULInfo>("V_" # emulMX); 226206c3fb27SDimitry Andric defvar sews = SchedSEWSet<mx>.val; 226306c3fb27SDimitry Andric foreach e = sews in { 22645f757f3fSDimitry Andric defm _VV 22655f757f3fSDimitry Andric : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, 22665f757f3fSDimitry Andric Constraint, e>, 22675f757f3fSDimitry Andric SchedBinary<"WriteVRGatherVV", "ReadVRGatherVV_data", 22685f757f3fSDimitry Andric "ReadVRGatherVV_index", mx, e, forceMergeOpRead=true>; 226906c3fb27SDimitry Andric } 2270e8d8bef9SDimitry Andric } 2271e8d8bef9SDimitry Andric } 2272e8d8bef9SDimitry Andric } 2273e8d8bef9SDimitry Andric} 2274e8d8bef9SDimitry Andric 227506c3fb27SDimitry Andricmulticlass VPseudoBinaryV_VX<LMULInfo m, string Constraint = "", int sew = 0> { 227606c3fb27SDimitry Andric defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint, sew>; 227706c3fb27SDimitry Andric} 227806c3fb27SDimitry Andric 227906c3fb27SDimitry Andricmulticlass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> { 228006c3fb27SDimitry Andric defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>; 2281e8d8bef9SDimitry Andric} 2282e8d8bef9SDimitry Andric 22830eae32dcSDimitry Andricmulticlass VPseudoVSLD1_VX<string Constraint = ""> { 2284bdd1243dSDimitry Andric foreach m = MxList in { 22850eae32dcSDimitry Andric defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>, 22865f757f3fSDimitry Andric SchedBinary<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX", 22875f757f3fSDimitry Andric m.MX, forceMergeOpRead=true>; 2288bdd1243dSDimitry Andric } 22890eae32dcSDimitry Andric} 22900eae32dcSDimitry Andric 229106c3fb27SDimitry Andricmulticlass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> { 2292e8d8bef9SDimitry Andric defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass, 229306c3fb27SDimitry Andric f.fprclass, m, Constraint, sew>; 229406c3fb27SDimitry Andric} 229506c3fb27SDimitry Andric 229606c3fb27SDimitry Andricmulticlass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> { 229706c3fb27SDimitry Andric defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, 229806c3fb27SDimitry Andric f.fprclass, m, Constraint, sew, 229906c3fb27SDimitry Andric UsesVXRM=0>; 2300e8d8bef9SDimitry Andric} 2301e8d8bef9SDimitry Andric 23020eae32dcSDimitry Andricmulticlass VPseudoVSLD1_VF<string Constraint = ""> { 2303bdd1243dSDimitry Andric foreach f = FPList in { 2304bdd1243dSDimitry Andric foreach m = f.MxList in { 23055f757f3fSDimitry Andric defm "_V" #f.FX 23065f757f3fSDimitry Andric : VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>, 23075f757f3fSDimitry Andric SchedBinary<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX, 23085f757f3fSDimitry Andric forceMergeOpRead=true>; 2309bdd1243dSDimitry Andric } 2310bdd1243dSDimitry Andric } 23110eae32dcSDimitry Andric} 23120eae32dcSDimitry Andric 2313bdd1243dSDimitry Andricmulticlass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> { 2314e8d8bef9SDimitry Andric defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>; 2315e8d8bef9SDimitry Andric} 2316e8d8bef9SDimitry Andric 231706c3fb27SDimitry Andricmulticlass VPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> { 231806c3fb27SDimitry Andric defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>; 231906c3fb27SDimitry Andric} 232006c3fb27SDimitry Andric 23215f757f3fSDimitry Andricmulticlass VPseudoVALU_MM<bit Commutable = 0> { 2322bdd1243dSDimitry Andric foreach m = MxList in { 2323bdd1243dSDimitry Andric defvar mx = m.MX; 23245f757f3fSDimitry Andric let VLMul = m.value, isCommutable = Commutable in { 232506c3fb27SDimitry Andric def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "">, 23265f757f3fSDimitry Andric SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mx>; 2327bdd1243dSDimitry Andric } 2328e8d8bef9SDimitry Andric } 2329e8d8bef9SDimitry Andric} 2330e8d8bef9SDimitry Andric 2331e8d8bef9SDimitry Andric// We use earlyclobber here due to 2332e8d8bef9SDimitry Andric// * The destination EEW is smaller than the source EEW and the overlap is 2333e8d8bef9SDimitry Andric// in the lowest-numbered part of the source register group is legal. 2334e8d8bef9SDimitry Andric// Otherwise, it is illegal. 2335e8d8bef9SDimitry Andric// * The destination EEW is greater than the source EEW, the source EMUL is 2336e8d8bef9SDimitry Andric// at least 1, and the overlap is in the highest-numbered part of the 2337e8d8bef9SDimitry Andric// destination register group is legal. Otherwise, it is illegal. 2338bdd1243dSDimitry Andricmulticlass VPseudoBinaryW_VV<LMULInfo m> { 2339e8d8bef9SDimitry Andric defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m, 23405f757f3fSDimitry Andric "@earlyclobber $rd", TargetConstraintType=3>; 2341e8d8bef9SDimitry Andric} 2342e8d8bef9SDimitry Andric 234306c3fb27SDimitry Andricmulticlass VPseudoBinaryW_VV_RM<LMULInfo m> { 234406c3fb27SDimitry Andric defm _VV : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m, 23455f757f3fSDimitry Andric "@earlyclobber $rd", UsesVXRM=0, 23465f757f3fSDimitry Andric TargetConstraintType=3>; 234706c3fb27SDimitry Andric} 234806c3fb27SDimitry Andric 2349bdd1243dSDimitry Andricmulticlass VPseudoBinaryW_VX<LMULInfo m> { 2350e8d8bef9SDimitry Andric defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m, 23515f757f3fSDimitry Andric "@earlyclobber $rd", TargetConstraintType=3>; 23525f757f3fSDimitry Andric} 23535f757f3fSDimitry Andric 23545f757f3fSDimitry Andricmulticlass VPseudoBinaryW_VI<Operand ImmType, LMULInfo m> { 23555f757f3fSDimitry Andric defm "_VI" : VPseudoBinary<m.wvrclass, m.vrclass, ImmType, m, 23565f757f3fSDimitry Andric "@earlyclobber $rd", TargetConstraintType=3>; 2357e8d8bef9SDimitry Andric} 2358e8d8bef9SDimitry Andric 2359bdd1243dSDimitry Andricmulticlass VPseudoBinaryW_VF<LMULInfo m, FPR_Info f> { 2360e8d8bef9SDimitry Andric defm "_V" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass, 2361e8d8bef9SDimitry Andric f.fprclass, m, 2362e8d8bef9SDimitry Andric "@earlyclobber $rd">; 2363e8d8bef9SDimitry Andric} 2364e8d8bef9SDimitry Andric 236506c3fb27SDimitry Andricmulticlass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f> { 236606c3fb27SDimitry Andric defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, 236706c3fb27SDimitry Andric f.fprclass, m, 236806c3fb27SDimitry Andric "@earlyclobber $rd", 23695f757f3fSDimitry Andric UsesVXRM=0, 23705f757f3fSDimitry Andric TargetConstraintType=3>; 237106c3fb27SDimitry Andric} 237206c3fb27SDimitry Andric 2373bdd1243dSDimitry Andricmulticlass VPseudoBinaryW_WV<LMULInfo m> { 2374e8d8bef9SDimitry Andric defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m, 23755f757f3fSDimitry Andric "@earlyclobber $rd", TargetConstraintType=3>; 2376fe6060f1SDimitry Andric defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m, 23775f757f3fSDimitry Andric "@earlyclobber $rd", TargetConstraintType=3>; 2378fe6060f1SDimitry Andric} 2379e8d8bef9SDimitry Andric 238006c3fb27SDimitry Andricmulticlass VPseudoBinaryW_WV_RM<LMULInfo m> { 238106c3fb27SDimitry Andric defm _WV : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, m.vrclass, m, 23825f757f3fSDimitry Andric "@earlyclobber $rd", UsesVXRM=0, TargetConstraintType=3>; 238306c3fb27SDimitry Andric defm _WV : VPseudoTiedBinaryRoundingMode<m.wvrclass, m.vrclass, m, 23845f757f3fSDimitry Andric "@earlyclobber $rd", TargetConstraintType=3>; 238506c3fb27SDimitry Andric} 238606c3fb27SDimitry Andric 2387bdd1243dSDimitry Andricmulticlass VPseudoBinaryW_WX<LMULInfo m> { 23885f757f3fSDimitry Andric defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, /*Constraint*/ "", TargetConstraintType=3>; 2389e8d8bef9SDimitry Andric} 2390e8d8bef9SDimitry Andric 23915f757f3fSDimitry Andricmulticlass VPseudoBinaryW_WF<LMULInfo m, FPR_Info f, int TargetConstraintType = 1> { 2392e8d8bef9SDimitry Andric defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass, 23935f757f3fSDimitry Andric f.fprclass, m, /*Constraint*/ "", TargetConstraintType=TargetConstraintType>; 2394e8d8bef9SDimitry Andric} 2395e8d8bef9SDimitry Andric 239606c3fb27SDimitry Andricmulticlass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f> { 239706c3fb27SDimitry Andric defm "_W" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, 239806c3fb27SDimitry Andric f.fprclass, m, 23995f757f3fSDimitry Andric Constraint="", 24005f757f3fSDimitry Andric sew=0, 24015f757f3fSDimitry Andric UsesVXRM=0, 24025f757f3fSDimitry Andric TargetConstraintType=3>; 240306c3fb27SDimitry Andric} 240406c3fb27SDimitry Andric 2405fe6060f1SDimitry Andric// Narrowing instructions like vnsrl/vnsra/vnclip(u) don't need @earlyclobber 2406fe6060f1SDimitry Andric// if the source and destination have an LMUL<=1. This matches this overlap 2407fe6060f1SDimitry Andric// exception from the spec. 2408fe6060f1SDimitry Andric// "The destination EEW is smaller than the source EEW and the overlap is in the 2409fe6060f1SDimitry Andric// lowest-numbered part of the source register group." 24105f757f3fSDimitry Andricmulticlass VPseudoBinaryV_WV<LMULInfo m, int TargetConstraintType = 1> { 2411e8d8bef9SDimitry Andric defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m, 24125f757f3fSDimitry Andric !if(!ge(m.octuple, 8), "@earlyclobber $rd", ""), TargetConstraintType=TargetConstraintType>; 2413e8d8bef9SDimitry Andric} 2414e8d8bef9SDimitry Andric 241506c3fb27SDimitry Andricmulticlass VPseudoBinaryV_WV_RM<LMULInfo m> { 241606c3fb27SDimitry Andric defm _WV : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, m.vrclass, m, 241706c3fb27SDimitry Andric !if(!ge(m.octuple, 8), 241806c3fb27SDimitry Andric "@earlyclobber $rd", "")>; 241906c3fb27SDimitry Andric} 242006c3fb27SDimitry Andric 24215f757f3fSDimitry Andricmulticlass VPseudoBinaryV_WX<LMULInfo m, int TargetConstraintType = 1> { 2422e8d8bef9SDimitry Andric defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m, 24235f757f3fSDimitry Andric !if(!ge(m.octuple, 8), "@earlyclobber $rd", ""), TargetConstraintType=TargetConstraintType>; 2424e8d8bef9SDimitry Andric} 2425e8d8bef9SDimitry Andric 242606c3fb27SDimitry Andricmulticlass VPseudoBinaryV_WX_RM<LMULInfo m> { 242706c3fb27SDimitry Andric defm _WX : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, GPR, m, 242806c3fb27SDimitry Andric !if(!ge(m.octuple, 8), 242906c3fb27SDimitry Andric "@earlyclobber $rd", "")>; 243006c3fb27SDimitry Andric} 243106c3fb27SDimitry Andric 24325f757f3fSDimitry Andricmulticlass VPseudoBinaryV_WI<LMULInfo m, int TargetConstraintType = 1> { 2433e8d8bef9SDimitry Andric defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m, 24345f757f3fSDimitry Andric !if(!ge(m.octuple, 8), "@earlyclobber $rd", ""), TargetConstraintType=TargetConstraintType>; 2435e8d8bef9SDimitry Andric} 2436e8d8bef9SDimitry Andric 243706c3fb27SDimitry Andricmulticlass VPseudoBinaryV_WI_RM<LMULInfo m> { 243806c3fb27SDimitry Andric defm _WI : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, uimm5, m, 243906c3fb27SDimitry Andric !if(!ge(m.octuple, 8), 244006c3fb27SDimitry Andric "@earlyclobber $rd", "")>; 244106c3fb27SDimitry Andric} 244206c3fb27SDimitry Andric 2443e8d8bef9SDimitry Andric// For vadc and vsbc, the instruction encoding is reserved if the destination 2444e8d8bef9SDimitry Andric// vector register is v0. 2445e8d8bef9SDimitry Andric// For vadc and vsbc, CarryIn == 1 and CarryOut == 0 2446bdd1243dSDimitry Andricmulticlass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1, 24475f757f3fSDimitry Andric string Constraint = "", 24485f757f3fSDimitry Andric bit Commutable = 0, 24495f757f3fSDimitry Andric int TargetConstraintType = 1> { 24505f757f3fSDimitry Andric let isCommutable = Commutable in 2451e8d8bef9SDimitry Andric def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX : 2452e8d8bef9SDimitry Andric VPseudoBinaryCarryIn<!if(CarryOut, VR, 2453e8d8bef9SDimitry Andric !if(!and(CarryIn, !not(CarryOut)), 2454e8d8bef9SDimitry Andric GetVRegNoV0<m.vrclass>.R, m.vrclass)), 24555f757f3fSDimitry Andric m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>; 2456e8d8bef9SDimitry Andric} 2457e8d8bef9SDimitry Andric 2458647cbc5dSDimitry Andricmulticlass VPseudoTiedBinaryV_VM<LMULInfo m, int TargetConstraintType = 1> { 245906c3fb27SDimitry Andric def "_VVM" # "_" # m.MX: 246006c3fb27SDimitry Andric VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, 2461647cbc5dSDimitry Andric m.vrclass, m.vrclass, m, 1, "", 2462647cbc5dSDimitry Andric TargetConstraintType>; 246304eeddc0SDimitry Andric} 246404eeddc0SDimitry Andric 2465bdd1243dSDimitry Andricmulticlass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1, 24665f757f3fSDimitry Andric string Constraint = "", int TargetConstraintType = 1> { 2467e8d8bef9SDimitry Andric def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX : 2468e8d8bef9SDimitry Andric VPseudoBinaryCarryIn<!if(CarryOut, VR, 2469e8d8bef9SDimitry Andric !if(!and(CarryIn, !not(CarryOut)), 2470e8d8bef9SDimitry Andric GetVRegNoV0<m.vrclass>.R, m.vrclass)), 24715f757f3fSDimitry Andric m.vrclass, GPR, m, CarryIn, Constraint, TargetConstraintType>; 2472e8d8bef9SDimitry Andric} 2473e8d8bef9SDimitry Andric 2474647cbc5dSDimitry Andricmulticlass VPseudoTiedBinaryV_XM<LMULInfo m, int TargetConstraintType = 1> { 247506c3fb27SDimitry Andric def "_VXM" # "_" # m.MX: 247606c3fb27SDimitry Andric VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, 2477647cbc5dSDimitry Andric m.vrclass, GPR, m, 1, "", 2478647cbc5dSDimitry Andric TargetConstraintType>; 247904eeddc0SDimitry Andric} 248004eeddc0SDimitry Andric 24810eae32dcSDimitry Andricmulticlass VPseudoVMRG_FM { 2482bdd1243dSDimitry Andric foreach f = FPList in { 248304eeddc0SDimitry Andric foreach m = f.MxList in { 2484bdd1243dSDimitry Andric defvar mx = m.MX; 24855f757f3fSDimitry Andric def "_V" # f.FX # "M_" # mx 24865f757f3fSDimitry Andric : VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, m.vrclass, 24875f757f3fSDimitry Andric f.fprclass, m, CarryIn=1, 24885f757f3fSDimitry Andric Constraint = "">, 24895f757f3fSDimitry Andric SchedBinary<"WriteVFMergeV", "ReadVFMergeV", "ReadVFMergeF", mx, 24905f757f3fSDimitry Andric forceMasked=1, forceMergeOpRead=true>; 2491bdd1243dSDimitry Andric } 249204eeddc0SDimitry Andric } 2493e8d8bef9SDimitry Andric} 2494e8d8bef9SDimitry Andric 2495bdd1243dSDimitry Andricmulticlass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1, 24965f757f3fSDimitry Andric string Constraint = "", int TargetConstraintType = 1> { 2497e8d8bef9SDimitry Andric def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX : 2498e8d8bef9SDimitry Andric VPseudoBinaryCarryIn<!if(CarryOut, VR, 2499e8d8bef9SDimitry Andric !if(!and(CarryIn, !not(CarryOut)), 2500e8d8bef9SDimitry Andric GetVRegNoV0<m.vrclass>.R, m.vrclass)), 25015f757f3fSDimitry Andric m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>; 2502e8d8bef9SDimitry Andric} 2503e8d8bef9SDimitry Andric 250406c3fb27SDimitry Andricmulticlass VPseudoTiedBinaryV_IM<LMULInfo m> { 250506c3fb27SDimitry Andric def "_VIM" # "_" # m.MX: 250606c3fb27SDimitry Andric VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, 250706c3fb27SDimitry Andric m.vrclass, simm5, m, 1, "">; 250804eeddc0SDimitry Andric} 250904eeddc0SDimitry Andric 25100eae32dcSDimitry Andricmulticlass VPseudoUnaryVMV_V_X_I { 251104eeddc0SDimitry Andric foreach m = MxList in { 2512e8d8bef9SDimitry Andric let VLMul = m.value in { 2513bdd1243dSDimitry Andric defvar mx = m.MX; 2514bdd1243dSDimitry Andric let VLMul = m.value in { 251506c3fb27SDimitry Andric def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, 25165f757f3fSDimitry Andric SchedUnary<"WriteVIMovV", "ReadVIMovV", mx, 25175f757f3fSDimitry Andric forceMergeOpRead=true>; 251806c3fb27SDimitry Andric def "_X_" # mx : VPseudoUnaryNoMask<m.vrclass, GPR>, 25195f757f3fSDimitry Andric SchedUnary<"WriteVIMovX", "ReadVIMovX", mx, 25205f757f3fSDimitry Andric forceMergeOpRead=true>; 252106c3fb27SDimitry Andric def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>, 25225f757f3fSDimitry Andric SchedNullary<"WriteVIMovI", mx, 25235f757f3fSDimitry Andric forceMergeOpRead=true>; 2524bdd1243dSDimitry Andric } 2525e8d8bef9SDimitry Andric } 2526e8d8bef9SDimitry Andric } 2527e8d8bef9SDimitry Andric} 2528e8d8bef9SDimitry Andric 25290eae32dcSDimitry Andricmulticlass VPseudoVMV_F { 253004eeddc0SDimitry Andric foreach f = FPList in { 253104eeddc0SDimitry Andric foreach m = f.MxList in { 2532bdd1243dSDimitry Andric defvar mx = m.MX; 2533e8d8bef9SDimitry Andric let VLMul = m.value in { 2534bdd1243dSDimitry Andric def "_" # f.FX # "_" # mx : 253506c3fb27SDimitry Andric VPseudoUnaryNoMask<m.vrclass, f.fprclass>, 25365f757f3fSDimitry Andric SchedUnary<"WriteVFMovV", "ReadVFMovF", mx, forceMergeOpRead=true>; 2537e8d8bef9SDimitry Andric } 2538e8d8bef9SDimitry Andric } 2539e8d8bef9SDimitry Andric } 2540e8d8bef9SDimitry Andric} 2541e8d8bef9SDimitry Andric 25420eae32dcSDimitry Andricmulticlass VPseudoVCLS_V { 254304eeddc0SDimitry Andric foreach m = MxListF in { 2544bdd1243dSDimitry Andric defvar mx = m.MX; 2545349cc55cSDimitry Andric let VLMul = m.value in { 2546bdd1243dSDimitry Andric def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, 25475f757f3fSDimitry Andric SchedUnary<"WriteVFClassV", "ReadVFClassV", mx, 25485f757f3fSDimitry Andric forceMergeOpRead=true>; 254906c3fb27SDimitry Andric def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>, 255006c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>, 25515f757f3fSDimitry Andric SchedUnary<"WriteVFClassV", "ReadVFClassV", mx, 25525f757f3fSDimitry Andric forceMergeOpRead=true>; 2553349cc55cSDimitry Andric } 2554349cc55cSDimitry Andric } 2555349cc55cSDimitry Andric} 2556349cc55cSDimitry Andric 255706c3fb27SDimitry Andricmulticlass VPseudoVSQR_V_RM { 255804eeddc0SDimitry Andric foreach m = MxListF in { 2559bdd1243dSDimitry Andric defvar mx = m.MX; 256006c3fb27SDimitry Andric defvar sews = SchedSEWSet<m.MX, isF=1>.val; 2561bdd1243dSDimitry Andric 256206c3fb27SDimitry Andric let VLMul = m.value in 256306c3fb27SDimitry Andric foreach e = sews in { 256406c3fb27SDimitry Andric defvar suffix = "_" # mx # "_E" # e; 256506c3fb27SDimitry Andric let SEW = e in { 256606c3fb27SDimitry Andric def "_V" # suffix : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>, 25675f757f3fSDimitry Andric SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e, 25685f757f3fSDimitry Andric forceMergeOpRead=true>; 25695f757f3fSDimitry Andric def "_V" #suffix # "_MASK" 25705f757f3fSDimitry Andric : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>, 257106c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx = 2>, 25725f757f3fSDimitry Andric SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e, 25735f757f3fSDimitry Andric forceMergeOpRead=true>; 257406c3fb27SDimitry Andric } 2575e8d8bef9SDimitry Andric } 2576e8d8bef9SDimitry Andric } 2577e8d8bef9SDimitry Andric} 2578e8d8bef9SDimitry Andric 25790eae32dcSDimitry Andricmulticlass VPseudoVRCP_V { 258004eeddc0SDimitry Andric foreach m = MxListF in { 2581bdd1243dSDimitry Andric defvar mx = m.MX; 25820eae32dcSDimitry Andric let VLMul = m.value in { 25835f757f3fSDimitry Andric def "_V_" # mx 25845f757f3fSDimitry Andric : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, 25855f757f3fSDimitry Andric SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>; 25865f757f3fSDimitry Andric def "_V_" # mx # "_MASK" 25875f757f3fSDimitry Andric : VPseudoUnaryMask<m.vrclass, m.vrclass>, 258806c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx = 2>, 25895f757f3fSDimitry Andric SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>; 259006c3fb27SDimitry Andric } 259106c3fb27SDimitry Andric } 259206c3fb27SDimitry Andric} 259306c3fb27SDimitry Andric 259406c3fb27SDimitry Andricmulticlass VPseudoVRCP_V_RM { 259506c3fb27SDimitry Andric foreach m = MxListF in { 259606c3fb27SDimitry Andric defvar mx = m.MX; 259706c3fb27SDimitry Andric let VLMul = m.value in { 25985f757f3fSDimitry Andric def "_V_" # mx 25995f757f3fSDimitry Andric : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>, 26005f757f3fSDimitry Andric SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>; 26015f757f3fSDimitry Andric def "_V_" # mx # "_MASK" 26025f757f3fSDimitry Andric : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>, 260306c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx = 2>, 26045f757f3fSDimitry Andric SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>; 26050eae32dcSDimitry Andric } 26060eae32dcSDimitry Andric } 26070eae32dcSDimitry Andric} 26080eae32dcSDimitry Andric 2609647cbc5dSDimitry Andricmulticlass PseudoVEXT_VF2 { 2610e8d8bef9SDimitry Andric defvar constraints = "@earlyclobber $rd"; 261106c3fb27SDimitry Andric foreach m = MxListVF2 in { 2612bdd1243dSDimitry Andric defvar mx = m.MX; 2613647cbc5dSDimitry Andric defvar CurrTypeConstraints = !if(!or(!eq(mx, "MF4"), !eq(mx, "MF2"), !eq(mx, "M1")), 1, 3); 2614e8d8bef9SDimitry Andric let VLMul = m.value in { 2615647cbc5dSDimitry Andric def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints, CurrTypeConstraints>, 26165f757f3fSDimitry Andric SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>; 2617bdd1243dSDimitry Andric def "_" # mx # "_MASK" : 2618647cbc5dSDimitry Andric VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints, CurrTypeConstraints>, 261906c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>, 26205f757f3fSDimitry Andric SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>; 2621e8d8bef9SDimitry Andric } 2622e8d8bef9SDimitry Andric } 2623e8d8bef9SDimitry Andric} 2624e8d8bef9SDimitry Andric 2625647cbc5dSDimitry Andricmulticlass PseudoVEXT_VF4 { 2626e8d8bef9SDimitry Andric defvar constraints = "@earlyclobber $rd"; 262706c3fb27SDimitry Andric foreach m = MxListVF4 in { 2628bdd1243dSDimitry Andric defvar mx = m.MX; 2629647cbc5dSDimitry Andric defvar CurrTypeConstraints = !if(!or(!eq(mx, "MF2"), !eq(mx, "M1"), !eq(mx, "M2")), 1, 3); 2630e8d8bef9SDimitry Andric let VLMul = m.value in { 2631647cbc5dSDimitry Andric def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints, CurrTypeConstraints>, 26325f757f3fSDimitry Andric SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>; 2633bdd1243dSDimitry Andric def "_" # mx # "_MASK" : 2634647cbc5dSDimitry Andric VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints, CurrTypeConstraints>, 263506c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>, 26365f757f3fSDimitry Andric SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>; 2637e8d8bef9SDimitry Andric } 2638e8d8bef9SDimitry Andric } 2639e8d8bef9SDimitry Andric} 2640e8d8bef9SDimitry Andric 2641647cbc5dSDimitry Andricmulticlass PseudoVEXT_VF8 { 2642e8d8bef9SDimitry Andric defvar constraints = "@earlyclobber $rd"; 264306c3fb27SDimitry Andric foreach m = MxListVF8 in { 2644bdd1243dSDimitry Andric defvar mx = m.MX; 2645647cbc5dSDimitry Andric defvar CurrTypeConstraints = !if(!or(!eq(mx, "M1"), !eq(mx, "M2"), !eq(mx, "M4")), 1, 3); 2646e8d8bef9SDimitry Andric let VLMul = m.value in { 2647647cbc5dSDimitry Andric def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints, CurrTypeConstraints>, 26485f757f3fSDimitry Andric SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>; 2649bdd1243dSDimitry Andric def "_" # mx # "_MASK" : 2650647cbc5dSDimitry Andric VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints, CurrTypeConstraints>, 265106c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>, 26525f757f3fSDimitry Andric SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>; 2653e8d8bef9SDimitry Andric } 2654e8d8bef9SDimitry Andric } 2655e8d8bef9SDimitry Andric} 2656e8d8bef9SDimitry Andric 2657fe6060f1SDimitry Andric// The destination EEW is 1 since "For the purposes of register group overlap 2658fe6060f1SDimitry Andric// constraints, mask elements have EEW=1." 2659e8d8bef9SDimitry Andric// The source EEW is 8, 16, 32, or 64. 2660e8d8bef9SDimitry Andric// When the destination EEW is different from source EEW, we need to use 2661e8d8bef9SDimitry Andric// @earlyclobber to avoid the overlap between destination and source registers. 2662fe6060f1SDimitry Andric// We don't need @earlyclobber for LMUL<=1 since that matches this overlap 2663fe6060f1SDimitry Andric// exception from the spec 2664fe6060f1SDimitry Andric// "The destination EEW is smaller than the source EEW and the overlap is in the 2665fe6060f1SDimitry Andric// lowest-numbered part of the source register group". 2666fe6060f1SDimitry Andric// With LMUL<=1 the source and dest occupy a single register so any overlap 2667fe6060f1SDimitry Andric// is in the lowest-numbered part. 26685f757f3fSDimitry Andricmulticlass VPseudoBinaryM_VV<LMULInfo m, int TargetConstraintType = 1> { 2669fe6060f1SDimitry Andric defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m, 26705f757f3fSDimitry Andric !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; 2671e8d8bef9SDimitry Andric} 2672e8d8bef9SDimitry Andric 26735f757f3fSDimitry Andricmulticlass VPseudoBinaryM_VX<LMULInfo m, int TargetConstraintType = 1> { 2674e8d8bef9SDimitry Andric defm "_VX" : 2675fe6060f1SDimitry Andric VPseudoBinaryM<VR, m.vrclass, GPR, m, 26765f757f3fSDimitry Andric !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; 2677e8d8bef9SDimitry Andric} 2678e8d8bef9SDimitry Andric 26795f757f3fSDimitry Andricmulticlass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f, int TargetConstraintType = 1> { 2680e8d8bef9SDimitry Andric defm "_V" # f.FX : 2681fe6060f1SDimitry Andric VPseudoBinaryM<VR, m.vrclass, f.fprclass, m, 26825f757f3fSDimitry Andric !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; 2683e8d8bef9SDimitry Andric} 2684e8d8bef9SDimitry Andric 26855f757f3fSDimitry Andricmulticlass VPseudoBinaryM_VI<LMULInfo m, int TargetConstraintType = 1> { 2686fe6060f1SDimitry Andric defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m, 26875f757f3fSDimitry Andric !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; 2688e8d8bef9SDimitry Andric} 2689e8d8bef9SDimitry Andric 26900eae32dcSDimitry Andricmulticlass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { 2691bdd1243dSDimitry Andric foreach m = MxList in { 2692bdd1243dSDimitry Andric defvar mx = m.MX; 2693bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m, Constraint>, 26945f757f3fSDimitry Andric SchedBinary<"WriteVRGatherVX", "ReadVRGatherVX_data", 26955f757f3fSDimitry Andric "ReadVRGatherVX_index", mx, forceMergeOpRead=true>; 2696bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>, 26975f757f3fSDimitry Andric SchedUnary<"WriteVRGatherVI", "ReadVRGatherVI_data", mx, 26985f757f3fSDimitry Andric forceMergeOpRead=true>; 269906c3fb27SDimitry Andric 270006c3fb27SDimitry Andric defvar sews = SchedSEWSet<mx>.val; 270106c3fb27SDimitry Andric foreach e = sews in { 270206c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VV<m, Constraint, e>, 27035f757f3fSDimitry Andric SchedBinary<"WriteVRGatherVV", "ReadVRGatherVV_data", 27045f757f3fSDimitry Andric "ReadVRGatherVV_index", mx, e, forceMergeOpRead=true>; 270506c3fb27SDimitry Andric } 2706bdd1243dSDimitry Andric } 2707e8d8bef9SDimitry Andric} 2708e8d8bef9SDimitry Andric 27090eae32dcSDimitry Andricmulticlass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { 2710bdd1243dSDimitry Andric foreach m = MxList in { 2711bdd1243dSDimitry Andric defvar mx = m.MX; 2712bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VV<m, Constraint>, 27135f757f3fSDimitry Andric SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx, 27145f757f3fSDimitry Andric forceMergeOpRead=true>; 2715bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m, Constraint>, 27165f757f3fSDimitry Andric SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx, 27175f757f3fSDimitry Andric forceMergeOpRead=true>; 2718bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>, 27195f757f3fSDimitry Andric SchedUnary<"WriteVSALUI", "ReadVSALUV", mx, forceMergeOpRead=true>; 2720bdd1243dSDimitry Andric } 2721e8d8bef9SDimitry Andric} 2722e8d8bef9SDimitry Andric 27230eae32dcSDimitry Andric 27240eae32dcSDimitry Andricmulticlass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { 2725bdd1243dSDimitry Andric foreach m = MxList in { 2726bdd1243dSDimitry Andric defvar mx = m.MX; 2727bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VV<m, Constraint>, 27285f757f3fSDimitry Andric SchedBinary<"WriteVShiftV", "ReadVShiftV", "ReadVShiftV", mx, 27295f757f3fSDimitry Andric forceMergeOpRead=true>; 2730bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m, Constraint>, 27315f757f3fSDimitry Andric SchedBinary<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX", mx, 27325f757f3fSDimitry Andric forceMergeOpRead=true>; 2733bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>, 27345f757f3fSDimitry Andric SchedUnary<"WriteVShiftI", "ReadVShiftV", mx, forceMergeOpRead=true>; 2735bdd1243dSDimitry Andric } 2736e8d8bef9SDimitry Andric} 2737e8d8bef9SDimitry Andric 273806c3fb27SDimitry Andricmulticlass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint = ""> { 2739bdd1243dSDimitry Andric foreach m = MxList in { 2740bdd1243dSDimitry Andric defvar mx = m.MX; 274106c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VV_RM<m, Constraint>, 27425f757f3fSDimitry Andric SchedBinary<"WriteVSShiftV", "ReadVSShiftV", "ReadVSShiftV", mx, 27435f757f3fSDimitry Andric forceMergeOpRead=true>; 274406c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VX_RM<m, Constraint>, 27455f757f3fSDimitry Andric SchedBinary<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX", mx, 27465f757f3fSDimitry Andric forceMergeOpRead=true>; 274706c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VI_RM<ImmType, m, Constraint>, 27485f757f3fSDimitry Andric SchedUnary<"WriteVSShiftI", "ReadVSShiftV", mx, forceMergeOpRead=true>; 2749bdd1243dSDimitry Andric } 2750e8d8bef9SDimitry Andric} 2751e8d8bef9SDimitry Andric 27520eae32dcSDimitry Andricmulticlass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { 2753bdd1243dSDimitry Andric foreach m = MxList in { 2754bdd1243dSDimitry Andric defvar mx = m.MX; 2755bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VV<m, Constraint>, 27565f757f3fSDimitry Andric SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx, 27575f757f3fSDimitry Andric forceMergeOpRead=true>; 2758bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m, Constraint>, 27595f757f3fSDimitry Andric SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx, 27605f757f3fSDimitry Andric forceMergeOpRead=true>; 2761bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>, 27625f757f3fSDimitry Andric SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>; 2763bdd1243dSDimitry Andric } 27640eae32dcSDimitry Andric} 27650eae32dcSDimitry Andric 27660eae32dcSDimitry Andricmulticlass VPseudoVSALU_VV_VX { 2767bdd1243dSDimitry Andric foreach m = MxList in { 2768bdd1243dSDimitry Andric defvar mx = m.MX; 2769bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VV<m>, 27705f757f3fSDimitry Andric SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUV", mx, 27715f757f3fSDimitry Andric forceMergeOpRead=true>; 2772bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m>, 27735f757f3fSDimitry Andric SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx, 27745f757f3fSDimitry Andric forceMergeOpRead=true>; 2775bdd1243dSDimitry Andric } 27760eae32dcSDimitry Andric} 27770eae32dcSDimitry Andric 277806c3fb27SDimitry Andricmulticlass VPseudoVSMUL_VV_VX_RM { 2779bdd1243dSDimitry Andric foreach m = MxList in { 2780bdd1243dSDimitry Andric defvar mx = m.MX; 278106c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VV_RM<m>, 27825f757f3fSDimitry Andric SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx, 27835f757f3fSDimitry Andric forceMergeOpRead=true>; 278406c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VX_RM<m>, 27855f757f3fSDimitry Andric SchedBinary<"WriteVSMulX", "ReadVSMulV", "ReadVSMulX", mx, 27865f757f3fSDimitry Andric forceMergeOpRead=true>; 2787bdd1243dSDimitry Andric } 27880eae32dcSDimitry Andric} 27890eae32dcSDimitry Andric 279006c3fb27SDimitry Andricmulticlass VPseudoVAALU_VV_VX_RM { 2791bdd1243dSDimitry Andric foreach m = MxList in { 2792bdd1243dSDimitry Andric defvar mx = m.MX; 279306c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VV_RM<m>, 27945f757f3fSDimitry Andric SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx, 27955f757f3fSDimitry Andric forceMergeOpRead=true>; 279606c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VX_RM<m>, 27975f757f3fSDimitry Andric SchedBinary<"WriteVAALUX", "ReadVAALUV", "ReadVAALUX", mx, 27985f757f3fSDimitry Andric forceMergeOpRead=true>; 2799bdd1243dSDimitry Andric } 28000eae32dcSDimitry Andric} 28010eae32dcSDimitry Andric 28020eae32dcSDimitry Andricmulticlass VPseudoVMINMAX_VV_VX { 2803bdd1243dSDimitry Andric foreach m = MxList in { 2804bdd1243dSDimitry Andric defvar mx = m.MX; 2805bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VV<m>, 28065f757f3fSDimitry Andric SchedBinary<"WriteVIMinMaxV", "ReadVIMinMaxV", "ReadVIMinMaxV", mx>; 2807bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m>, 28085f757f3fSDimitry Andric SchedBinary<"WriteVIMinMaxX", "ReadVIMinMaxV", "ReadVIMinMaxX", mx>; 2809bdd1243dSDimitry Andric } 28100eae32dcSDimitry Andric} 28110eae32dcSDimitry Andric 28120eae32dcSDimitry Andricmulticlass VPseudoVMUL_VV_VX { 2813bdd1243dSDimitry Andric foreach m = MxList in { 2814bdd1243dSDimitry Andric defvar mx = m.MX; 2815bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VV<m>, 28165f757f3fSDimitry Andric SchedBinary<"WriteVIMulV", "ReadVIMulV", "ReadVIMulV", mx>; 2817bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m>, 28185f757f3fSDimitry Andric SchedBinary<"WriteVIMulX", "ReadVIMulV", "ReadVIMulX", mx>; 2819bdd1243dSDimitry Andric } 28200eae32dcSDimitry Andric} 28210eae32dcSDimitry Andric 28220eae32dcSDimitry Andricmulticlass VPseudoVDIV_VV_VX { 2823bdd1243dSDimitry Andric foreach m = MxList in { 2824bdd1243dSDimitry Andric defvar mx = m.MX; 282506c3fb27SDimitry Andric defvar sews = SchedSEWSet<mx>.val; 282606c3fb27SDimitry Andric foreach e = sews in { 282706c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VV<m, "", e>, 28285f757f3fSDimitry Andric SchedBinary<"WriteVIDivV", "ReadVIDivV", "ReadVIDivV", mx, e>; 282906c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VX<m, "", e>, 28305f757f3fSDimitry Andric SchedBinary<"WriteVIDivX", "ReadVIDivV", "ReadVIDivX", mx, e>; 283106c3fb27SDimitry Andric } 2832bdd1243dSDimitry Andric } 28330eae32dcSDimitry Andric} 28340eae32dcSDimitry Andric 283506c3fb27SDimitry Andricmulticlass VPseudoVFMUL_VV_VF_RM { 2836bdd1243dSDimitry Andric foreach m = MxListF in { 283706c3fb27SDimitry Andric defm "" : VPseudoBinaryFV_VV_RM<m>, 28385f757f3fSDimitry Andric SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX, 28395f757f3fSDimitry Andric forceMergeOpRead=true>; 2840bdd1243dSDimitry Andric } 2841bdd1243dSDimitry Andric 2842bdd1243dSDimitry Andric foreach f = FPList in { 2843bdd1243dSDimitry Andric foreach m = f.MxList in { 284406c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VF_RM<m, f>, 28455f757f3fSDimitry Andric SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX, 28465f757f3fSDimitry Andric forceMergeOpRead=true>; 2847bdd1243dSDimitry Andric } 2848bdd1243dSDimitry Andric } 28490eae32dcSDimitry Andric} 28500eae32dcSDimitry Andric 285106c3fb27SDimitry Andricmulticlass VPseudoVFDIV_VV_VF_RM { 2852bdd1243dSDimitry Andric foreach m = MxListF in { 2853bdd1243dSDimitry Andric defvar mx = m.MX; 285406c3fb27SDimitry Andric defvar sews = SchedSEWSet<mx, isF=1>.val; 285506c3fb27SDimitry Andric foreach e = sews in { 285606c3fb27SDimitry Andric defm "" : VPseudoBinaryFV_VV_RM<m, "", e>, 28575f757f3fSDimitry Andric SchedBinary<"WriteVFDivV", "ReadVFDivV", "ReadVFDivV", mx, e, 28585f757f3fSDimitry Andric forceMergeOpRead=true>; 285906c3fb27SDimitry Andric } 2860bdd1243dSDimitry Andric } 2861bdd1243dSDimitry Andric 2862bdd1243dSDimitry Andric foreach f = FPList in { 2863bdd1243dSDimitry Andric foreach m = f.MxList in { 286406c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>, 28655f757f3fSDimitry Andric SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW, 28665f757f3fSDimitry Andric forceMergeOpRead=true>; 2867bdd1243dSDimitry Andric } 2868bdd1243dSDimitry Andric } 28690eae32dcSDimitry Andric} 28700eae32dcSDimitry Andric 287106c3fb27SDimitry Andricmulticlass VPseudoVFRDIV_VF_RM { 2872bdd1243dSDimitry Andric foreach f = FPList in { 2873bdd1243dSDimitry Andric foreach m = f.MxList in { 287406c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>, 28755f757f3fSDimitry Andric SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW, 28765f757f3fSDimitry Andric forceMergeOpRead=true>; 2877bdd1243dSDimitry Andric } 2878bdd1243dSDimitry Andric } 28790eae32dcSDimitry Andric} 28800eae32dcSDimitry Andric 28810eae32dcSDimitry Andricmulticlass VPseudoVALU_VV_VX { 2882bdd1243dSDimitry Andric foreach m = MxList in { 2883bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VV<m>, 28845f757f3fSDimitry Andric SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, 28855f757f3fSDimitry Andric forceMergeOpRead=true>; 2886bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m>, 28875f757f3fSDimitry Andric SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX, 28885f757f3fSDimitry Andric forceMergeOpRead=true>; 2889bdd1243dSDimitry Andric } 28900eae32dcSDimitry Andric} 28910eae32dcSDimitry Andric 28920eae32dcSDimitry Andricmulticlass VPseudoVSGNJ_VV_VF { 2893bdd1243dSDimitry Andric foreach m = MxListF in { 2894bdd1243dSDimitry Andric defm "" : VPseudoBinaryFV_VV<m>, 28955f757f3fSDimitry Andric SchedBinary<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV", m.MX, 28965f757f3fSDimitry Andric forceMergeOpRead=true>; 2897bdd1243dSDimitry Andric } 2898bdd1243dSDimitry Andric 2899bdd1243dSDimitry Andric foreach f = FPList in { 2900bdd1243dSDimitry Andric foreach m = f.MxList in { 2901bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VF<m, f>, 29025f757f3fSDimitry Andric SchedBinary<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF", m.MX, 29035f757f3fSDimitry Andric forceMergeOpRead=true>; 2904bdd1243dSDimitry Andric } 2905bdd1243dSDimitry Andric } 29060eae32dcSDimitry Andric} 29070eae32dcSDimitry Andric 29080eae32dcSDimitry Andricmulticlass VPseudoVMAX_VV_VF { 2909bdd1243dSDimitry Andric foreach m = MxListF in { 2910bdd1243dSDimitry Andric defm "" : VPseudoBinaryFV_VV<m>, 29115f757f3fSDimitry Andric SchedBinary<"WriteVFMinMaxV", "ReadVFMinMaxV", "ReadVFMinMaxV", m.MX, 29125f757f3fSDimitry Andric forceMergeOpRead=true>; 2913bdd1243dSDimitry Andric } 2914bdd1243dSDimitry Andric 2915bdd1243dSDimitry Andric foreach f = FPList in { 2916bdd1243dSDimitry Andric foreach m = f.MxList in { 2917bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VF<m, f>, 29185f757f3fSDimitry Andric SchedBinary<"WriteVFMinMaxF", "ReadVFMinMaxV", "ReadVFMinMaxF", m.MX, 29195f757f3fSDimitry Andric forceMergeOpRead=true>; 2920bdd1243dSDimitry Andric } 2921bdd1243dSDimitry Andric } 29220eae32dcSDimitry Andric} 29230eae32dcSDimitry Andric 29240eae32dcSDimitry Andricmulticlass VPseudoVALU_VV_VF { 2925bdd1243dSDimitry Andric foreach m = MxListF in { 2926bdd1243dSDimitry Andric defm "" : VPseudoBinaryFV_VV<m>, 29275f757f3fSDimitry Andric SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX, 29285f757f3fSDimitry Andric forceMergeOpRead=true>; 2929bdd1243dSDimitry Andric } 2930bdd1243dSDimitry Andric 2931bdd1243dSDimitry Andric foreach f = FPList in { 2932bdd1243dSDimitry Andric foreach m = f.MxList in { 2933bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VF<m, f>, 29345f757f3fSDimitry Andric SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX, 29355f757f3fSDimitry Andric forceMergeOpRead=true>; 2936bdd1243dSDimitry Andric } 2937bdd1243dSDimitry Andric } 29380eae32dcSDimitry Andric} 29390eae32dcSDimitry Andric 294006c3fb27SDimitry Andricmulticlass VPseudoVALU_VV_VF_RM { 294106c3fb27SDimitry Andric foreach m = MxListF in { 294206c3fb27SDimitry Andric defm "" : VPseudoBinaryFV_VV_RM<m>, 29435f757f3fSDimitry Andric SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX, 29445f757f3fSDimitry Andric forceMergeOpRead=true>; 294506c3fb27SDimitry Andric } 294606c3fb27SDimitry Andric 294706c3fb27SDimitry Andric foreach f = FPList in { 294806c3fb27SDimitry Andric foreach m = f.MxList in { 294906c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VF_RM<m, f>, 29505f757f3fSDimitry Andric SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX, 29515f757f3fSDimitry Andric forceMergeOpRead=true>; 295206c3fb27SDimitry Andric } 295306c3fb27SDimitry Andric } 295406c3fb27SDimitry Andric} 295506c3fb27SDimitry Andric 29560eae32dcSDimitry Andricmulticlass VPseudoVALU_VF { 2957bdd1243dSDimitry Andric foreach f = FPList in { 2958bdd1243dSDimitry Andric foreach m = f.MxList in { 2959bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VF<m, f>, 29605f757f3fSDimitry Andric SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX, 29615f757f3fSDimitry Andric forceMergeOpRead=true>; 2962bdd1243dSDimitry Andric } 2963bdd1243dSDimitry Andric } 29640eae32dcSDimitry Andric} 29650eae32dcSDimitry Andric 296606c3fb27SDimitry Andricmulticlass VPseudoVALU_VF_RM { 296706c3fb27SDimitry Andric foreach f = FPList in { 296806c3fb27SDimitry Andric foreach m = f.MxList in { 296906c3fb27SDimitry Andric defm "" : VPseudoBinaryV_VF_RM<m, f>, 29705f757f3fSDimitry Andric SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX, 29715f757f3fSDimitry Andric forceMergeOpRead=true>; 297206c3fb27SDimitry Andric } 297306c3fb27SDimitry Andric } 297406c3fb27SDimitry Andric} 297506c3fb27SDimitry Andric 29760eae32dcSDimitry Andricmulticlass VPseudoVALU_VX_VI<Operand ImmType = simm5> { 2977bdd1243dSDimitry Andric foreach m = MxList in { 2978bdd1243dSDimitry Andric defvar mx = m.MX; 2979bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VX<m>, 29805f757f3fSDimitry Andric SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx, 29815f757f3fSDimitry Andric forceMergeOpRead=true>; 2982bdd1243dSDimitry Andric defm "" : VPseudoBinaryV_VI<ImmType, m>, 29835f757f3fSDimitry Andric SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>; 2984bdd1243dSDimitry Andric } 29850eae32dcSDimitry Andric} 29860eae32dcSDimitry Andric 29870eae32dcSDimitry Andricmulticlass VPseudoVWALU_VV_VX { 2988bdd1243dSDimitry Andric foreach m = MxListW in { 2989bdd1243dSDimitry Andric defvar mx = m.MX; 2990bdd1243dSDimitry Andric defm "" : VPseudoBinaryW_VV<m>, 29915f757f3fSDimitry Andric SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx, 29925f757f3fSDimitry Andric forceMergeOpRead=true>; 2993bdd1243dSDimitry Andric defm "" : VPseudoBinaryW_VX<m>, 29945f757f3fSDimitry Andric SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx, 29955f757f3fSDimitry Andric forceMergeOpRead=true>; 29965f757f3fSDimitry Andric } 29975f757f3fSDimitry Andric} 29985f757f3fSDimitry Andric 29995f757f3fSDimitry Andricmulticlass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX { 30005f757f3fSDimitry Andric foreach m = MxListW in { 30015f757f3fSDimitry Andric defm "" : VPseudoBinaryW_VI<ImmType, m>; 3002bdd1243dSDimitry Andric } 30030eae32dcSDimitry Andric} 30040eae32dcSDimitry Andric 30050eae32dcSDimitry Andricmulticlass VPseudoVWMUL_VV_VX { 3006bdd1243dSDimitry Andric foreach m = MxListW in { 3007bdd1243dSDimitry Andric defvar mx = m.MX; 3008bdd1243dSDimitry Andric defm "" : VPseudoBinaryW_VV<m>, 30095f757f3fSDimitry Andric SchedBinary<"WriteVIWMulV", "ReadVIWMulV", "ReadVIWMulV", mx, 30105f757f3fSDimitry Andric forceMergeOpRead=true>; 3011bdd1243dSDimitry Andric defm "" : VPseudoBinaryW_VX<m>, 30125f757f3fSDimitry Andric SchedBinary<"WriteVIWMulX", "ReadVIWMulV", "ReadVIWMulX", mx, 30135f757f3fSDimitry Andric forceMergeOpRead=true>; 3014bdd1243dSDimitry Andric } 30150eae32dcSDimitry Andric} 30160eae32dcSDimitry Andric 301706c3fb27SDimitry Andricmulticlass VPseudoVWMUL_VV_VF_RM { 3018bdd1243dSDimitry Andric foreach m = MxListFW in { 301906c3fb27SDimitry Andric defm "" : VPseudoBinaryW_VV_RM<m>, 30205f757f3fSDimitry Andric SchedBinary<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV", m.MX, 30215f757f3fSDimitry Andric forceMergeOpRead=true>; 3022bdd1243dSDimitry Andric } 3023bdd1243dSDimitry Andric 3024bdd1243dSDimitry Andric foreach f = FPListW in { 3025bdd1243dSDimitry Andric foreach m = f.MxListFW in { 302606c3fb27SDimitry Andric defm "" : VPseudoBinaryW_VF_RM<m, f>, 30275f757f3fSDimitry Andric SchedBinary<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF", m.MX, 30285f757f3fSDimitry Andric forceMergeOpRead=true>; 3029bdd1243dSDimitry Andric } 3030bdd1243dSDimitry Andric } 3031e8d8bef9SDimitry Andric} 3032e8d8bef9SDimitry Andric 30330eae32dcSDimitry Andricmulticlass VPseudoVWALU_WV_WX { 3034bdd1243dSDimitry Andric foreach m = MxListW in { 3035bdd1243dSDimitry Andric defvar mx = m.MX; 3036bdd1243dSDimitry Andric defm "" : VPseudoBinaryW_WV<m>, 30375f757f3fSDimitry Andric SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx, 30385f757f3fSDimitry Andric forceMergeOpRead=true>; 3039bdd1243dSDimitry Andric defm "" : VPseudoBinaryW_WX<m>, 30405f757f3fSDimitry Andric SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx, 30415f757f3fSDimitry Andric forceMergeOpRead=true>; 3042bdd1243dSDimitry Andric } 3043e8d8bef9SDimitry Andric} 3044e8d8bef9SDimitry Andric 304506c3fb27SDimitry Andricmulticlass VPseudoVFWALU_VV_VF_RM { 3046bdd1243dSDimitry Andric foreach m = MxListFW in { 304706c3fb27SDimitry Andric defm "" : VPseudoBinaryW_VV_RM<m>, 30485f757f3fSDimitry Andric SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX, 30495f757f3fSDimitry Andric forceMergeOpRead=true>; 3050bdd1243dSDimitry Andric } 3051bdd1243dSDimitry Andric 3052bdd1243dSDimitry Andric foreach f = FPListW in { 3053bdd1243dSDimitry Andric foreach m = f.MxListFW in { 305406c3fb27SDimitry Andric defm "" : VPseudoBinaryW_VF_RM<m, f>, 30555f757f3fSDimitry Andric SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX, 30565f757f3fSDimitry Andric forceMergeOpRead=true>; 3057bdd1243dSDimitry Andric } 3058bdd1243dSDimitry Andric } 3059e8d8bef9SDimitry Andric} 3060e8d8bef9SDimitry Andric 306106c3fb27SDimitry Andricmulticlass VPseudoVFWALU_WV_WF_RM { 3062bdd1243dSDimitry Andric foreach m = MxListFW in { 306306c3fb27SDimitry Andric defm "" : VPseudoBinaryW_WV_RM<m>, 30645f757f3fSDimitry Andric SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX, 30655f757f3fSDimitry Andric forceMergeOpRead=true>; 3066bdd1243dSDimitry Andric } 3067bdd1243dSDimitry Andric foreach f = FPListW in { 3068bdd1243dSDimitry Andric foreach m = f.MxListFW in { 306906c3fb27SDimitry Andric defm "" : VPseudoBinaryW_WF_RM<m, f>, 30705f757f3fSDimitry Andric SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX, 30715f757f3fSDimitry Andric forceMergeOpRead=true>; 3072bdd1243dSDimitry Andric } 3073bdd1243dSDimitry Andric } 3074e8d8bef9SDimitry Andric} 3075e8d8bef9SDimitry Andric 30760eae32dcSDimitry Andricmulticlass VPseudoVMRG_VM_XM_IM { 3077bdd1243dSDimitry Andric foreach m = MxList in { 3078bdd1243dSDimitry Andric defvar mx = m.MX; 307906c3fb27SDimitry Andric def "_VVM" # "_" # m.MX: 308006c3fb27SDimitry Andric VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, 308106c3fb27SDimitry Andric m.vrclass, m.vrclass, m, 1, "">, 30825f757f3fSDimitry Andric SchedBinary<"WriteVIMergeV", "ReadVIMergeV", "ReadVIMergeV", mx, 30835f757f3fSDimitry Andric forceMergeOpRead=true>; 308406c3fb27SDimitry Andric def "_VXM" # "_" # m.MX: 308506c3fb27SDimitry Andric VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, 308606c3fb27SDimitry Andric m.vrclass, GPR, m, 1, "">, 30875f757f3fSDimitry Andric SchedBinary<"WriteVIMergeX", "ReadVIMergeV", "ReadVIMergeX", mx, 30885f757f3fSDimitry Andric forceMergeOpRead=true>; 308906c3fb27SDimitry Andric def "_VIM" # "_" # m.MX: 309006c3fb27SDimitry Andric VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, 309106c3fb27SDimitry Andric m.vrclass, simm5, m, 1, "">, 30925f757f3fSDimitry Andric SchedUnary<"WriteVIMergeI", "ReadVIMergeV", mx, 30935f757f3fSDimitry Andric forceMergeOpRead=true>; 3094bdd1243dSDimitry Andric } 3095e8d8bef9SDimitry Andric} 3096e8d8bef9SDimitry Andric 30970eae32dcSDimitry Andricmulticlass VPseudoVCALU_VM_XM_IM { 3098bdd1243dSDimitry Andric foreach m = MxList in { 3099bdd1243dSDimitry Andric defvar mx = m.MX; 3100bdd1243dSDimitry Andric defm "" : VPseudoTiedBinaryV_VM<m>, 31015f757f3fSDimitry Andric SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, 31025f757f3fSDimitry Andric forceMergeOpRead=true>; 3103bdd1243dSDimitry Andric defm "" : VPseudoTiedBinaryV_XM<m>, 31045f757f3fSDimitry Andric SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, 31055f757f3fSDimitry Andric forceMergeOpRead=true>; 3106bdd1243dSDimitry Andric defm "" : VPseudoTiedBinaryV_IM<m>, 31075f757f3fSDimitry Andric SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, 31085f757f3fSDimitry Andric forceMergeOpRead=true>; 3109bdd1243dSDimitry Andric } 3110e8d8bef9SDimitry Andric} 3111e8d8bef9SDimitry Andric 31120eae32dcSDimitry Andricmulticlass VPseudoVCALU_VM_XM { 3113bdd1243dSDimitry Andric foreach m = MxList in { 3114bdd1243dSDimitry Andric defvar mx = m.MX; 3115bdd1243dSDimitry Andric defm "" : VPseudoTiedBinaryV_VM<m>, 31165f757f3fSDimitry Andric SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, 31175f757f3fSDimitry Andric forceMergeOpRead=true>; 3118bdd1243dSDimitry Andric defm "" : VPseudoTiedBinaryV_XM<m>, 31195f757f3fSDimitry Andric SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, 31205f757f3fSDimitry Andric forceMergeOpRead=true>; 3121bdd1243dSDimitry Andric } 3122e8d8bef9SDimitry Andric} 3123e8d8bef9SDimitry Andric 31240eae32dcSDimitry Andricmulticlass VPseudoVCALUM_VM_XM_IM<string Constraint> { 3125bdd1243dSDimitry Andric foreach m = MxList in { 3126bdd1243dSDimitry Andric defvar mx = m.MX; 31275f757f3fSDimitry Andric defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, 31285f757f3fSDimitry Andric Commutable=1, TargetConstraintType=2>, 31295f757f3fSDimitry Andric SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1, 31305f757f3fSDimitry Andric forceMergeOpRead=true>; 31315f757f3fSDimitry Andric defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>, 31325f757f3fSDimitry Andric SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1, 31335f757f3fSDimitry Andric forceMergeOpRead=true>; 31345f757f3fSDimitry Andric defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>, 31355f757f3fSDimitry Andric SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, forceMasked=1, 31365f757f3fSDimitry Andric forceMergeOpRead=true>; 3137bdd1243dSDimitry Andric } 3138e8d8bef9SDimitry Andric} 3139e8d8bef9SDimitry Andric 31400eae32dcSDimitry Andricmulticlass VPseudoVCALUM_VM_XM<string Constraint> { 3141bdd1243dSDimitry Andric foreach m = MxList in { 3142bdd1243dSDimitry Andric defvar mx = m.MX; 31435f757f3fSDimitry Andric defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>, 31445f757f3fSDimitry Andric SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1, 31455f757f3fSDimitry Andric forceMergeOpRead=true>; 31465f757f3fSDimitry Andric defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>, 31475f757f3fSDimitry Andric SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1, 31485f757f3fSDimitry Andric forceMergeOpRead=true>; 3149bdd1243dSDimitry Andric } 3150e8d8bef9SDimitry Andric} 3151e8d8bef9SDimitry Andric 31520eae32dcSDimitry Andricmulticlass VPseudoVCALUM_V_X_I<string Constraint> { 3153bdd1243dSDimitry Andric foreach m = MxList in { 3154bdd1243dSDimitry Andric defvar mx = m.MX; 31555f757f3fSDimitry Andric defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint, 31565f757f3fSDimitry Andric Commutable=1, TargetConstraintType=2>, 31575f757f3fSDimitry Andric SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, 31585f757f3fSDimitry Andric forceMergeOpRead=true>; 31595f757f3fSDimitry Andric defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint, TargetConstraintType=2>, 31605f757f3fSDimitry Andric SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, 31615f757f3fSDimitry Andric forceMergeOpRead=true>; 316206c3fb27SDimitry Andric defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>, 31635f757f3fSDimitry Andric SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, 31645f757f3fSDimitry Andric forceMergeOpRead=true>; 3165bdd1243dSDimitry Andric } 31660eae32dcSDimitry Andric} 31670eae32dcSDimitry Andric 31680eae32dcSDimitry Andricmulticlass VPseudoVCALUM_V_X<string Constraint> { 3169bdd1243dSDimitry Andric foreach m = MxList in { 3170bdd1243dSDimitry Andric defvar mx = m.MX; 31715f757f3fSDimitry Andric defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint, TargetConstraintType=2>, 31725f757f3fSDimitry Andric SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, 31735f757f3fSDimitry Andric forceMergeOpRead=true>; 31745f757f3fSDimitry Andric defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint, TargetConstraintType=2>, 31755f757f3fSDimitry Andric SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, 31765f757f3fSDimitry Andric forceMergeOpRead=true>; 3177bdd1243dSDimitry Andric } 31780eae32dcSDimitry Andric} 31790eae32dcSDimitry Andric 318006c3fb27SDimitry Andricmulticlass VPseudoVNCLP_WV_WX_WI_RM { 3181bdd1243dSDimitry Andric foreach m = MxListW in { 3182bdd1243dSDimitry Andric defvar mx = m.MX; 318306c3fb27SDimitry Andric defm "" : VPseudoBinaryV_WV_RM<m>, 31845f757f3fSDimitry Andric SchedBinary<"WriteVNClipV", "ReadVNClipV", "ReadVNClipV", mx, 31855f757f3fSDimitry Andric forceMergeOpRead=true>; 318606c3fb27SDimitry Andric defm "" : VPseudoBinaryV_WX_RM<m>, 31875f757f3fSDimitry Andric SchedBinary<"WriteVNClipX", "ReadVNClipV", "ReadVNClipX", mx, 31885f757f3fSDimitry Andric forceMergeOpRead=true>; 318906c3fb27SDimitry Andric defm "" : VPseudoBinaryV_WI_RM<m>, 31905f757f3fSDimitry Andric SchedUnary<"WriteVNClipI", "ReadVNClipV", mx, 31915f757f3fSDimitry Andric forceMergeOpRead=true>; 3192bdd1243dSDimitry Andric } 31930eae32dcSDimitry Andric} 31940eae32dcSDimitry Andric 31950eae32dcSDimitry Andricmulticlass VPseudoVNSHT_WV_WX_WI { 3196bdd1243dSDimitry Andric foreach m = MxListW in { 3197bdd1243dSDimitry Andric defvar mx = m.MX; 31985f757f3fSDimitry Andric defm "" : VPseudoBinaryV_WV<m, TargetConstraintType=2>, 31995f757f3fSDimitry Andric SchedBinary<"WriteVNShiftV", "ReadVNShiftV", "ReadVNShiftV", mx, 32005f757f3fSDimitry Andric forceMergeOpRead=true>; 32015f757f3fSDimitry Andric defm "" : VPseudoBinaryV_WX<m, TargetConstraintType=2>, 32025f757f3fSDimitry Andric SchedBinary<"WriteVNShiftX", "ReadVNShiftV", "ReadVNShiftX", mx, 32035f757f3fSDimitry Andric forceMergeOpRead=true>; 32045f757f3fSDimitry Andric defm "" : VPseudoBinaryV_WI<m, TargetConstraintType=2>, 32055f757f3fSDimitry Andric SchedUnary<"WriteVNShiftI", "ReadVNShiftV", mx, 32065f757f3fSDimitry Andric forceMergeOpRead=true>; 3207bdd1243dSDimitry Andric } 3208e8d8bef9SDimitry Andric} 3209e8d8bef9SDimitry Andric 321006c3fb27SDimitry Andricmulticlass VPseudoTernaryWithTailPolicy<VReg RetClass, 3211fe6060f1SDimitry Andric RegisterClass Op1Class, 3212fe6060f1SDimitry Andric DAGOperand Op2Class, 3213e8d8bef9SDimitry Andric LMULInfo MInfo, 321406c3fb27SDimitry Andric int sew, 321506c3fb27SDimitry Andric string Constraint = "", 321606c3fb27SDimitry Andric bit Commutable = 0> { 32175f757f3fSDimitry Andric let VLMul = MInfo.value, SEW=sew in { 321806c3fb27SDimitry Andric defvar mx = MInfo.MX; 321906c3fb27SDimitry Andric let isCommutable = Commutable in 322006c3fb27SDimitry Andric def "_" # mx # "_E" # sew : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>; 32215f757f3fSDimitry Andric def "_" # mx # "_E" # sew # "_MASK" : VPseudoTernaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>, 32225f757f3fSDimitry Andric RISCVMaskedPseudo<MaskIdx=3, MaskAffectsRes=true>; 3223e8d8bef9SDimitry Andric } 3224e8d8bef9SDimitry Andric} 3225e8d8bef9SDimitry Andric 322606c3fb27SDimitry Andricmulticlass VPseudoTernaryWithTailPolicyRoundingMode<VReg RetClass, 322781ad6265SDimitry Andric RegisterClass Op1Class, 322881ad6265SDimitry Andric DAGOperand Op2Class, 322981ad6265SDimitry Andric LMULInfo MInfo, 323006c3fb27SDimitry Andric int sew, 323106c3fb27SDimitry Andric string Constraint = "", 323206c3fb27SDimitry Andric bit Commutable = 0> { 32335f757f3fSDimitry Andric let VLMul = MInfo.value, SEW=sew in { 323406c3fb27SDimitry Andric defvar mx = MInfo.MX; 323506c3fb27SDimitry Andric let isCommutable = Commutable in 323606c3fb27SDimitry Andric def "_" # mx # "_E" # sew 323706c3fb27SDimitry Andric : VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class, 323806c3fb27SDimitry Andric Op2Class, Constraint>; 323906c3fb27SDimitry Andric def "_" # mx # "_E" # sew # "_MASK" 324006c3fb27SDimitry Andric : VPseudoTernaryMaskPolicyRoundingMode<RetClass, Op1Class, 32415f757f3fSDimitry Andric Op2Class, Constraint>, 32425f757f3fSDimitry Andric RISCVMaskedPseudo<MaskIdx=3, MaskAffectsRes=true>; 324381ad6265SDimitry Andric } 324481ad6265SDimitry Andric} 324581ad6265SDimitry Andric 3246349cc55cSDimitry Andricmulticlass VPseudoTernaryWithPolicy<VReg RetClass, 3247349cc55cSDimitry Andric RegisterClass Op1Class, 3248349cc55cSDimitry Andric DAGOperand Op2Class, 3249349cc55cSDimitry Andric LMULInfo MInfo, 3250349cc55cSDimitry Andric string Constraint = "", 32515f757f3fSDimitry Andric bit Commutable = 0, 32525f757f3fSDimitry Andric int TargetConstraintType = 1> { 3253349cc55cSDimitry Andric let VLMul = MInfo.value in { 3254349cc55cSDimitry Andric let isCommutable = Commutable in 32555f757f3fSDimitry Andric def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>; 32565f757f3fSDimitry Andric def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>, 325706c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>; 325806c3fb27SDimitry Andric } 325906c3fb27SDimitry Andric} 326006c3fb27SDimitry Andric 326106c3fb27SDimitry Andricmulticlass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass, 326206c3fb27SDimitry Andric RegisterClass Op1Class, 326306c3fb27SDimitry Andric DAGOperand Op2Class, 326406c3fb27SDimitry Andric LMULInfo MInfo, 326506c3fb27SDimitry Andric string Constraint = "", 32665f757f3fSDimitry Andric bit Commutable = 0, 32675f757f3fSDimitry Andric int TargetConstraintType = 1> { 326806c3fb27SDimitry Andric let VLMul = MInfo.value in { 326906c3fb27SDimitry Andric let isCommutable = Commutable in 327006c3fb27SDimitry Andric def "_" # MInfo.MX : 327106c3fb27SDimitry Andric VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class, 32725f757f3fSDimitry Andric Op2Class, Constraint, 32735f757f3fSDimitry Andric TargetConstraintType>; 327406c3fb27SDimitry Andric def "_" # MInfo.MX # "_MASK" : 327506c3fb27SDimitry Andric VPseudoBinaryMaskPolicyRoundingMode<RetClass, Op1Class, 327606c3fb27SDimitry Andric Op2Class, Constraint, 32775f757f3fSDimitry Andric UsesVXRM_=0, 32785f757f3fSDimitry Andric TargetConstraintType=TargetConstraintType>, 327906c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>; 3280349cc55cSDimitry Andric } 3281349cc55cSDimitry Andric} 3282fe6060f1SDimitry Andric 3283bdd1243dSDimitry Andricmulticlass VPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> { 3284349cc55cSDimitry Andric defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m, 328506c3fb27SDimitry Andric Constraint, Commutable=1>; 3286fe6060f1SDimitry Andric} 3287e8d8bef9SDimitry Andric 328806c3fb27SDimitry Andricmulticlass VPseudoTernaryV_VV_AAXA_RM<LMULInfo m, string Constraint = ""> { 328906c3fb27SDimitry Andric defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, 329006c3fb27SDimitry Andric Constraint, Commutable=1>; 3291e8d8bef9SDimitry Andric} 3292e8d8bef9SDimitry Andric 3293bdd1243dSDimitry Andricmulticlass VPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> { 3294349cc55cSDimitry Andric defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m, 329506c3fb27SDimitry Andric Constraint, Commutable=1>; 3296e8d8bef9SDimitry Andric} 3297e8d8bef9SDimitry Andric 3298bdd1243dSDimitry Andricmulticlass VPseudoTernaryV_VF_AAXA<LMULInfo m, FPR_Info f, string Constraint = ""> { 3299349cc55cSDimitry Andric defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.vrclass, f.fprclass, 3300349cc55cSDimitry Andric m.vrclass, m, Constraint, 330106c3fb27SDimitry Andric Commutable=1>; 330206c3fb27SDimitry Andric} 330306c3fb27SDimitry Andric 330406c3fb27SDimitry Andricmulticlass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f, string Constraint = ""> { 330506c3fb27SDimitry Andric defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, f.fprclass, 330606c3fb27SDimitry Andric m.vrclass, m, Constraint, 330706c3fb27SDimitry Andric Commutable=1>; 3308e8d8bef9SDimitry Andric} 3309e8d8bef9SDimitry Andric 3310bdd1243dSDimitry Andricmulticlass VPseudoTernaryW_VV<LMULInfo m> { 3311e8d8bef9SDimitry Andric defvar constraint = "@earlyclobber $rd"; 3312349cc55cSDimitry Andric defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m, 33135f757f3fSDimitry Andric constraint, /*Commutable*/ 0, TargetConstraintType=3>; 3314fe6060f1SDimitry Andric} 3315e8d8bef9SDimitry Andric 331606c3fb27SDimitry Andricmulticlass VPseudoTernaryW_VV_RM<LMULInfo m> { 331706c3fb27SDimitry Andric defvar constraint = "@earlyclobber $rd"; 331806c3fb27SDimitry Andric defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m, 33195f757f3fSDimitry Andric constraint, /* Commutable */ 0, 33205f757f3fSDimitry Andric TargetConstraintType=3>; 332106c3fb27SDimitry Andric} 332206c3fb27SDimitry Andric 3323bdd1243dSDimitry Andricmulticlass VPseudoTernaryW_VX<LMULInfo m> { 3324e8d8bef9SDimitry Andric defvar constraint = "@earlyclobber $rd"; 3325349cc55cSDimitry Andric defm "_VX" : VPseudoTernaryWithPolicy<m.wvrclass, GPR, m.vrclass, m, 33265f757f3fSDimitry Andric constraint, /*Commutable*/ 0, TargetConstraintType=3>; 3327e8d8bef9SDimitry Andric} 3328e8d8bef9SDimitry Andric 33295f757f3fSDimitry Andricmulticlass VPseudoTernaryW_VF<LMULInfo m, FPR_Info f, int TargetConstraintType = 1> { 3330e8d8bef9SDimitry Andric defvar constraint = "@earlyclobber $rd"; 3331349cc55cSDimitry Andric defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass, 33325f757f3fSDimitry Andric m.vrclass, m, constraint, /*Commutable*/ 0, TargetConstraintType>; 3333e8d8bef9SDimitry Andric} 3334e8d8bef9SDimitry Andric 333506c3fb27SDimitry Andricmulticlass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f> { 333606c3fb27SDimitry Andric defvar constraint = "@earlyclobber $rd"; 333706c3fb27SDimitry Andric defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass, 33385f757f3fSDimitry Andric m.vrclass, m, constraint, 33395f757f3fSDimitry Andric /* Commutable */ 0, 33405f757f3fSDimitry Andric TargetConstraintType=3>; 334106c3fb27SDimitry Andric} 334206c3fb27SDimitry Andric 334306c3fb27SDimitry Andricmulticlass VPseudoVSLDVWithPolicy<VReg RetClass, 334406c3fb27SDimitry Andric RegisterClass Op1Class, 334506c3fb27SDimitry Andric DAGOperand Op2Class, 334606c3fb27SDimitry Andric LMULInfo MInfo, 334706c3fb27SDimitry Andric string Constraint = ""> { 334806c3fb27SDimitry Andric let VLMul = MInfo.value in { 334906c3fb27SDimitry Andric def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>; 335006c3fb27SDimitry Andric def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>, 335106c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=3>; 335206c3fb27SDimitry Andric } 335306c3fb27SDimitry Andric} 335406c3fb27SDimitry Andric 335506c3fb27SDimitry Andricmulticlass VPseudoVSLDV_VX<LMULInfo m, string Constraint = ""> { 335606c3fb27SDimitry Andric defm _VX : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>; 335706c3fb27SDimitry Andric} 335806c3fb27SDimitry Andric 3359bdd1243dSDimitry Andricmulticlass VPseudoVSLDV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> { 336006c3fb27SDimitry Andric defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>; 3361e8d8bef9SDimitry Andric} 3362e8d8bef9SDimitry Andric 33630eae32dcSDimitry Andricmulticlass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> { 3364bdd1243dSDimitry Andric foreach m = MxList in { 3365bdd1243dSDimitry Andric defvar mx = m.MX; 3366bdd1243dSDimitry Andric defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>, 33675f757f3fSDimitry Andric SchedTernary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", 33685f757f3fSDimitry Andric "ReadVIMulAddV", mx>; 3369bdd1243dSDimitry Andric defm "" : VPseudoTernaryV_VX_AAXA<m, Constraint>, 33705f757f3fSDimitry Andric SchedTernary<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX", 33715f757f3fSDimitry Andric "ReadVIMulAddV", mx>; 3372bdd1243dSDimitry Andric } 3373e8d8bef9SDimitry Andric} 3374e8d8bef9SDimitry Andric 33750eae32dcSDimitry Andricmulticlass VPseudoVMAC_VV_VF_AAXA<string Constraint = ""> { 3376bdd1243dSDimitry Andric foreach m = MxListF in { 3377bdd1243dSDimitry Andric defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>, 33785f757f3fSDimitry Andric SchedTernary<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV", 33795f757f3fSDimitry Andric "ReadVFMulAddV", m.MX>; 3380bdd1243dSDimitry Andric } 3381bdd1243dSDimitry Andric 3382bdd1243dSDimitry Andric foreach f = FPList in { 3383bdd1243dSDimitry Andric foreach m = f.MxList in { 3384bdd1243dSDimitry Andric defm "" : VPseudoTernaryV_VF_AAXA<m, f, Constraint>, 33855f757f3fSDimitry Andric SchedTernary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF", 33865f757f3fSDimitry Andric "ReadVFMulAddV", m.MX>; 3387bdd1243dSDimitry Andric } 3388bdd1243dSDimitry Andric } 3389e8d8bef9SDimitry Andric} 3390e8d8bef9SDimitry Andric 339106c3fb27SDimitry Andricmulticlass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> { 339206c3fb27SDimitry Andric foreach m = MxListF in { 339306c3fb27SDimitry Andric defm "" : VPseudoTernaryV_VV_AAXA_RM<m, Constraint>, 33945f757f3fSDimitry Andric SchedTernary<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV", 33955f757f3fSDimitry Andric "ReadVFMulAddV", m.MX>; 339606c3fb27SDimitry Andric } 339706c3fb27SDimitry Andric 339806c3fb27SDimitry Andric foreach f = FPList in { 339906c3fb27SDimitry Andric foreach m = f.MxList in { 340006c3fb27SDimitry Andric defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, Constraint>, 34015f757f3fSDimitry Andric SchedTernary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF", 34025f757f3fSDimitry Andric "ReadVFMulAddV", m.MX>; 340306c3fb27SDimitry Andric } 340406c3fb27SDimitry Andric } 340506c3fb27SDimitry Andric} 340606c3fb27SDimitry Andric 34070eae32dcSDimitry Andricmulticlass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> { 3408bdd1243dSDimitry Andric foreach m = MxList in { 3409bdd1243dSDimitry Andric defvar mx = m.MX; 3410bdd1243dSDimitry Andric defm "" : VPseudoVSLDV_VX<m, Constraint>, 34115f757f3fSDimitry Andric SchedTernary<"WriteVISlideX", "ReadVISlideV", "ReadVISlideV", 34125f757f3fSDimitry Andric "ReadVISlideX", mx>; 3413bdd1243dSDimitry Andric defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>, 34145f757f3fSDimitry Andric SchedBinary<"WriteVISlideI", "ReadVISlideV", "ReadVISlideV", mx>; 3415bdd1243dSDimitry Andric } 3416e8d8bef9SDimitry Andric} 3417e8d8bef9SDimitry Andric 34180eae32dcSDimitry Andricmulticlass VPseudoVWMAC_VV_VX { 3419bdd1243dSDimitry Andric foreach m = MxListW in { 3420bdd1243dSDimitry Andric defvar mx = m.MX; 3421bdd1243dSDimitry Andric defm "" : VPseudoTernaryW_VV<m>, 34225f757f3fSDimitry Andric SchedTernary<"WriteVIWMulAddV", "ReadVIWMulAddV", "ReadVIWMulAddV", 34235f757f3fSDimitry Andric "ReadVIWMulAddV", mx>; 3424bdd1243dSDimitry Andric defm "" : VPseudoTernaryW_VX<m>, 34255f757f3fSDimitry Andric SchedTernary<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddX", 34265f757f3fSDimitry Andric "ReadVIWMulAddV", mx>; 3427bdd1243dSDimitry Andric } 3428e8d8bef9SDimitry Andric} 3429e8d8bef9SDimitry Andric 34300eae32dcSDimitry Andricmulticlass VPseudoVWMAC_VX { 3431bdd1243dSDimitry Andric foreach m = MxListW in { 3432bdd1243dSDimitry Andric defm "" : VPseudoTernaryW_VX<m>, 34335f757f3fSDimitry Andric SchedTernary<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddX", 34345f757f3fSDimitry Andric "ReadVIWMulAddV", m.MX>; 3435bdd1243dSDimitry Andric } 3436e8d8bef9SDimitry Andric} 3437e8d8bef9SDimitry Andric 343806c3fb27SDimitry Andricmulticlass VPseudoVWMAC_VV_VF_RM { 3439bdd1243dSDimitry Andric foreach m = MxListFW in { 344006c3fb27SDimitry Andric defm "" : VPseudoTernaryW_VV_RM<m>, 34415f757f3fSDimitry Andric SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV", 34425f757f3fSDimitry Andric "ReadVFWMulAddV", "ReadVFWMulAddV", m.MX>; 3443bdd1243dSDimitry Andric } 3444bdd1243dSDimitry Andric 3445bdd1243dSDimitry Andric foreach f = FPListW in { 3446bdd1243dSDimitry Andric foreach m = f.MxListFW in { 344706c3fb27SDimitry Andric defm "" : VPseudoTernaryW_VF_RM<m, f>, 34485f757f3fSDimitry Andric SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV", 34495f757f3fSDimitry Andric "ReadVFWMulAddF", "ReadVFWMulAddV", m.MX>; 34505f757f3fSDimitry Andric } 34515f757f3fSDimitry Andric } 34525f757f3fSDimitry Andric} 34535f757f3fSDimitry Andric 34545f757f3fSDimitry Andricmulticlass VPseudoVWMAC_VV_VF_BF_RM { 34555f757f3fSDimitry Andric foreach m = MxListFW in { 34565f757f3fSDimitry Andric defvar mx = m.MX; 34575f757f3fSDimitry Andric defm "" : VPseudoTernaryW_VV_RM<m>, 34585f757f3fSDimitry Andric SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV", 34595f757f3fSDimitry Andric "ReadVFWMulAddV", "ReadVFWMulAddV", mx>; 34605f757f3fSDimitry Andric } 34615f757f3fSDimitry Andric 34625f757f3fSDimitry Andric foreach f = BFPListW in { 34635f757f3fSDimitry Andric foreach m = f.MxListFW in { 34645f757f3fSDimitry Andric defvar mx = m.MX; 34655f757f3fSDimitry Andric defm "" : VPseudoTernaryW_VF_RM<m, f>, 34665f757f3fSDimitry Andric SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV", 34675f757f3fSDimitry Andric "ReadVFWMulAddF", "ReadVFWMulAddV", mx>; 3468bdd1243dSDimitry Andric } 3469bdd1243dSDimitry Andric } 3470e8d8bef9SDimitry Andric} 3471e8d8bef9SDimitry Andric 34720eae32dcSDimitry Andricmulticlass VPseudoVCMPM_VV_VX_VI { 3473bdd1243dSDimitry Andric foreach m = MxList in { 3474bdd1243dSDimitry Andric defvar mx = m.MX; 34755f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>, 34765f757f3fSDimitry Andric SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>; 34775f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>, 34785f757f3fSDimitry Andric SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>; 34795f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2>, 34805f757f3fSDimitry Andric SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>; 3481bdd1243dSDimitry Andric } 3482e8d8bef9SDimitry Andric} 3483e8d8bef9SDimitry Andric 34840eae32dcSDimitry Andricmulticlass VPseudoVCMPM_VV_VX { 3485bdd1243dSDimitry Andric foreach m = MxList in { 3486bdd1243dSDimitry Andric defvar mx = m.MX; 34875f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>, 34885f757f3fSDimitry Andric SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>; 34895f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>, 34905f757f3fSDimitry Andric SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>; 3491bdd1243dSDimitry Andric } 3492e8d8bef9SDimitry Andric} 3493e8d8bef9SDimitry Andric 34940eae32dcSDimitry Andricmulticlass VPseudoVCMPM_VV_VF { 3495bdd1243dSDimitry Andric foreach m = MxListF in { 34965f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>, 34975f757f3fSDimitry Andric SchedBinary<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV", m.MX>; 3498bdd1243dSDimitry Andric } 3499bdd1243dSDimitry Andric 3500bdd1243dSDimitry Andric foreach f = FPList in { 3501bdd1243dSDimitry Andric foreach m = f.MxList in { 35025f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2>, 35035f757f3fSDimitry Andric SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>; 3504bdd1243dSDimitry Andric } 3505bdd1243dSDimitry Andric } 3506e8d8bef9SDimitry Andric} 3507e8d8bef9SDimitry Andric 35080eae32dcSDimitry Andricmulticlass VPseudoVCMPM_VF { 3509bdd1243dSDimitry Andric foreach f = FPList in { 3510bdd1243dSDimitry Andric foreach m = f.MxList in { 35115f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2>, 35125f757f3fSDimitry Andric SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>; 3513bdd1243dSDimitry Andric } 3514bdd1243dSDimitry Andric } 35150eae32dcSDimitry Andric} 35160eae32dcSDimitry Andric 35170eae32dcSDimitry Andricmulticlass VPseudoVCMPM_VX_VI { 3518bdd1243dSDimitry Andric foreach m = MxList in { 3519bdd1243dSDimitry Andric defvar mx = m.MX; 35205f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>, 35215f757f3fSDimitry Andric SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>; 35225f757f3fSDimitry Andric defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2>, 35235f757f3fSDimitry Andric SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>; 3524bdd1243dSDimitry Andric } 35250eae32dcSDimitry Andric} 35260eae32dcSDimitry Andric 35270eae32dcSDimitry Andricmulticlass VPseudoVRED_VS { 352804eeddc0SDimitry Andric foreach m = MxList in { 352906c3fb27SDimitry Andric defvar mx = m.MX; 353006c3fb27SDimitry Andric foreach e = SchedSEWSet<mx>.val in { 353106c3fb27SDimitry Andric defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>, 35325f757f3fSDimitry Andric SchedReduction<"WriteVIRedV_From", "ReadVIRedV", mx, e>; 353306c3fb27SDimitry Andric } 353406c3fb27SDimitry Andric } 353506c3fb27SDimitry Andric} 353606c3fb27SDimitry Andric 353706c3fb27SDimitry Andricmulticlass VPseudoVREDMINMAX_VS { 353806c3fb27SDimitry Andric foreach m = MxList in { 353906c3fb27SDimitry Andric defvar mx = m.MX; 354006c3fb27SDimitry Andric foreach e = SchedSEWSet<mx>.val in { 354106c3fb27SDimitry Andric defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>, 35425f757f3fSDimitry Andric SchedReduction<"WriteVIRedMinMaxV_From", "ReadVIRedV", mx, e>; 354306c3fb27SDimitry Andric } 35440eae32dcSDimitry Andric } 35450eae32dcSDimitry Andric} 35460eae32dcSDimitry Andric 35470eae32dcSDimitry Andricmulticlass VPseudoVWRED_VS { 354806c3fb27SDimitry Andric foreach m = MxListWRed in { 354906c3fb27SDimitry Andric defvar mx = m.MX; 355006c3fb27SDimitry Andric foreach e = SchedSEWSet<mx, isWidening=1>.val in { 355106c3fb27SDimitry Andric defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>, 35525f757f3fSDimitry Andric SchedReduction<"WriteVIWRedV_From", "ReadVIWRedV", mx, e>; 355306c3fb27SDimitry Andric } 35540eae32dcSDimitry Andric } 35550eae32dcSDimitry Andric} 35560eae32dcSDimitry Andric 355706c3fb27SDimitry Andricmulticlass VPseudoVFRED_VS_RM { 355804eeddc0SDimitry Andric foreach m = MxListF in { 355906c3fb27SDimitry Andric defvar mx = m.MX; 356006c3fb27SDimitry Andric foreach e = SchedSEWSet<mx, isF=1>.val in { 356106c3fb27SDimitry Andric defm _VS 356206c3fb27SDimitry Andric : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass, 356306c3fb27SDimitry Andric V_M1.vrclass, m, e>, 35645f757f3fSDimitry Andric SchedReduction<"WriteVFRedV_From", "ReadVFRedV", mx, e>; 356506c3fb27SDimitry Andric } 35660eae32dcSDimitry Andric } 35670eae32dcSDimitry Andric} 35680eae32dcSDimitry Andric 356906c3fb27SDimitry Andricmulticlass VPseudoVFREDMINMAX_VS { 357004eeddc0SDimitry Andric foreach m = MxListF in { 357106c3fb27SDimitry Andric defvar mx = m.MX; 357206c3fb27SDimitry Andric foreach e = SchedSEWSet<mx, isF=1>.val in { 357306c3fb27SDimitry Andric defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>, 35745f757f3fSDimitry Andric SchedReduction<"WriteVFRedMinMaxV_From", "ReadVFRedV", mx, e>; 357506c3fb27SDimitry Andric } 35760eae32dcSDimitry Andric } 35770eae32dcSDimitry Andric} 35780eae32dcSDimitry Andric 357906c3fb27SDimitry Andricmulticlass VPseudoVFREDO_VS_RM { 358004eeddc0SDimitry Andric foreach m = MxListF in { 358106c3fb27SDimitry Andric defvar mx = m.MX; 358206c3fb27SDimitry Andric foreach e = SchedSEWSet<mx, isF=1>.val in { 358306c3fb27SDimitry Andric defm _VS : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass, 358406c3fb27SDimitry Andric V_M1.vrclass, m, e>, 35855f757f3fSDimitry Andric SchedReduction<"WriteVFRedOV_From", "ReadVFRedOV", mx, e>; 358606c3fb27SDimitry Andric } 358706c3fb27SDimitry Andric } 358806c3fb27SDimitry Andric} 358906c3fb27SDimitry Andric 359006c3fb27SDimitry Andricmulticlass VPseudoVFWRED_VS_RM { 359106c3fb27SDimitry Andric foreach m = MxListFWRed in { 359206c3fb27SDimitry Andric defvar mx = m.MX; 359306c3fb27SDimitry Andric foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in { 359406c3fb27SDimitry Andric defm _VS 359506c3fb27SDimitry Andric : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass, 359606c3fb27SDimitry Andric V_M1.vrclass, m, e>, 35975f757f3fSDimitry Andric SchedReduction<"WriteVFWRedV_From", "ReadVFWRedV", mx, e>; 35985f757f3fSDimitry Andric } 35995f757f3fSDimitry Andric } 36005f757f3fSDimitry Andric} 36015f757f3fSDimitry Andric 36025f757f3fSDimitry Andricmulticlass VPseudoVFWREDO_VS_RM { 36035f757f3fSDimitry Andric foreach m = MxListFWRed in { 36045f757f3fSDimitry Andric defvar mx = m.MX; 36055f757f3fSDimitry Andric foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in { 36065f757f3fSDimitry Andric defm _VS 36075f757f3fSDimitry Andric : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass, 36085f757f3fSDimitry Andric V_M1.vrclass, m, e>, 36095f757f3fSDimitry Andric SchedReduction<"WriteVFWRedOV_From", "ReadVFWRedV", mx, e>; 361006c3fb27SDimitry Andric } 3611e8d8bef9SDimitry Andric } 3612e8d8bef9SDimitry Andric} 3613e8d8bef9SDimitry Andric 3614e8d8bef9SDimitry Andricmulticlass VPseudoConversion<VReg RetClass, 3615e8d8bef9SDimitry Andric VReg Op1Class, 3616e8d8bef9SDimitry Andric LMULInfo MInfo, 36175f757f3fSDimitry Andric string Constraint = "", 36185f757f3fSDimitry Andric int TargetConstraintType = 1> { 3619e8d8bef9SDimitry Andric let VLMul = MInfo.value in { 36205f757f3fSDimitry Andric def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint, TargetConstraintType>; 362106c3fb27SDimitry Andric def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class, 36225f757f3fSDimitry Andric Constraint, TargetConstraintType>, 362306c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>; 3624e8d8bef9SDimitry Andric } 3625e8d8bef9SDimitry Andric} 3626e8d8bef9SDimitry Andric 362706c3fb27SDimitry Andricmulticlass VPseudoConversionRoundingMode<VReg RetClass, 362806c3fb27SDimitry Andric VReg Op1Class, 362906c3fb27SDimitry Andric LMULInfo MInfo, 36305f757f3fSDimitry Andric string Constraint = "", 36315f757f3fSDimitry Andric int TargetConstraintType = 1> { 363206c3fb27SDimitry Andric let VLMul = MInfo.value in { 36335f757f3fSDimitry Andric def "_" # MInfo.MX : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint, TargetConstraintType>; 363406c3fb27SDimitry Andric def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class, 3635647cbc5dSDimitry Andric Constraint, TargetConstraintType>, 363606c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>; 363706c3fb27SDimitry Andric } 363806c3fb27SDimitry Andric} 363906c3fb27SDimitry Andric 364006c3fb27SDimitry Andric 3641bdd1243dSDimitry Andricmulticlass VPseudoConversionRM<VReg RetClass, 3642bdd1243dSDimitry Andric VReg Op1Class, 3643bdd1243dSDimitry Andric LMULInfo MInfo, 3644647cbc5dSDimitry Andric string Constraint = "", 3645647cbc5dSDimitry Andric int TargetConstraintType = 1> { 3646bdd1243dSDimitry Andric let VLMul = MInfo.value in { 364706c3fb27SDimitry Andric def "_" # MInfo.MX : VPseudoUnaryNoMask_FRM<RetClass, Op1Class, 3648647cbc5dSDimitry Andric Constraint, TargetConstraintType>; 364906c3fb27SDimitry Andric def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class, 3650647cbc5dSDimitry Andric Constraint, TargetConstraintType>, 365106c3fb27SDimitry Andric RISCVMaskedPseudo<MaskIdx=2>; 3652bdd1243dSDimitry Andric } 3653bdd1243dSDimitry Andric} 3654bdd1243dSDimitry Andric 3655bdd1243dSDimitry Andricmulticlass VPseudoConversionNoExcept<VReg RetClass, 3656bdd1243dSDimitry Andric VReg Op1Class, 3657bdd1243dSDimitry Andric LMULInfo MInfo, 3658bdd1243dSDimitry Andric string Constraint = ""> { 3659bdd1243dSDimitry Andric let VLMul = MInfo.value in { 366006c3fb27SDimitry Andric def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_NoExcept<RetClass, Op1Class, Constraint>; 3661bdd1243dSDimitry Andric } 3662bdd1243dSDimitry Andric} 3663bdd1243dSDimitry Andric 36640eae32dcSDimitry Andricmulticlass VPseudoVCVTI_V { 3665bdd1243dSDimitry Andric foreach m = MxListF in { 36660eae32dcSDimitry Andric defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>, 36675f757f3fSDimitry Andric SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX, 36685f757f3fSDimitry Andric forceMergeOpRead=true>; 3669bdd1243dSDimitry Andric } 3670bdd1243dSDimitry Andric} 3671bdd1243dSDimitry Andric 367206c3fb27SDimitry Andricmulticlass VPseudoVCVTI_V_RM { 367306c3fb27SDimitry Andric foreach m = MxListF in { 367406c3fb27SDimitry Andric defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>, 36755f757f3fSDimitry Andric SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX, 36765f757f3fSDimitry Andric forceMergeOpRead=true>; 367706c3fb27SDimitry Andric } 367806c3fb27SDimitry Andric} 367906c3fb27SDimitry Andric 3680bdd1243dSDimitry Andricmulticlass VPseudoVCVTI_RM_V { 3681bdd1243dSDimitry Andric foreach m = MxListF in { 3682bdd1243dSDimitry Andric defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>, 36835f757f3fSDimitry Andric SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX, 36845f757f3fSDimitry Andric forceMergeOpRead=true>; 3685bdd1243dSDimitry Andric } 3686bdd1243dSDimitry Andric} 3687bdd1243dSDimitry Andric 3688bdd1243dSDimitry Andricmulticlass VPseudoVFROUND_NOEXCEPT_V { 3689bdd1243dSDimitry Andric foreach m = MxListF in { 3690bdd1243dSDimitry Andric defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m>, 36915f757f3fSDimitry Andric SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX, 36925f757f3fSDimitry Andric forceMergeOpRead=true>; 3693bdd1243dSDimitry Andric } 36940eae32dcSDimitry Andric} 36950eae32dcSDimitry Andric 369606c3fb27SDimitry Andricmulticlass VPseudoVCVTF_V_RM { 3697bdd1243dSDimitry Andric foreach m = MxListF in { 369806c3fb27SDimitry Andric defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>, 36995f757f3fSDimitry Andric SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, 37005f757f3fSDimitry Andric forceMergeOpRead=true>; 3701bdd1243dSDimitry Andric } 3702bdd1243dSDimitry Andric} 3703bdd1243dSDimitry Andric 3704bdd1243dSDimitry Andricmulticlass VPseudoVCVTF_RM_V { 3705bdd1243dSDimitry Andric foreach m = MxListF in { 3706bdd1243dSDimitry Andric defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>, 37075f757f3fSDimitry Andric SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, 37085f757f3fSDimitry Andric forceMergeOpRead=true>; 3709bdd1243dSDimitry Andric } 3710e8d8bef9SDimitry Andric} 3711e8d8bef9SDimitry Andric 37120eae32dcSDimitry Andricmulticlass VPseudoVWCVTI_V { 37130eae32dcSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3714bdd1243dSDimitry Andric foreach m = MxListFW in { 37155f757f3fSDimitry Andric defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>, 37165f757f3fSDimitry Andric SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX, 37175f757f3fSDimitry Andric forceMergeOpRead=true>; 3718bdd1243dSDimitry Andric } 3719bdd1243dSDimitry Andric} 3720bdd1243dSDimitry Andric 372106c3fb27SDimitry Andricmulticlass VPseudoVWCVTI_V_RM { 372206c3fb27SDimitry Andric defvar constraint = "@earlyclobber $rd"; 372306c3fb27SDimitry Andric foreach m = MxListFW in { 37245f757f3fSDimitry Andric defm _V : VPseudoConversionRoundingMode<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>, 37255f757f3fSDimitry Andric SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX, 37265f757f3fSDimitry Andric forceMergeOpRead=true>; 372706c3fb27SDimitry Andric } 372806c3fb27SDimitry Andric} 372906c3fb27SDimitry Andric 3730bdd1243dSDimitry Andricmulticlass VPseudoVWCVTI_RM_V { 3731bdd1243dSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3732bdd1243dSDimitry Andric foreach m = MxListFW in { 3733bdd1243dSDimitry Andric defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>, 37345f757f3fSDimitry Andric SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX, 37355f757f3fSDimitry Andric forceMergeOpRead=true>; 3736bdd1243dSDimitry Andric } 37370eae32dcSDimitry Andric} 37380eae32dcSDimitry Andric 37390eae32dcSDimitry Andricmulticlass VPseudoVWCVTF_V { 37400eae32dcSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3741bdd1243dSDimitry Andric foreach m = MxListW in { 37425f757f3fSDimitry Andric defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>, 37435f757f3fSDimitry Andric SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX, 37445f757f3fSDimitry Andric forceMergeOpRead=true>; 3745bdd1243dSDimitry Andric } 3746bdd1243dSDimitry Andric} 3747bdd1243dSDimitry Andric 37480eae32dcSDimitry Andricmulticlass VPseudoVWCVTD_V { 37490eae32dcSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3750bdd1243dSDimitry Andric foreach m = MxListFW in { 37515f757f3fSDimitry Andric defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>, 37525f757f3fSDimitry Andric SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX, 37535f757f3fSDimitry Andric forceMergeOpRead=true>; 3754bdd1243dSDimitry Andric } 37550eae32dcSDimitry Andric} 37560eae32dcSDimitry Andric 37570eae32dcSDimitry Andricmulticlass VPseudoVNCVTI_W { 37580eae32dcSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3759bdd1243dSDimitry Andric foreach m = MxListW in { 37605f757f3fSDimitry Andric defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>, 37615f757f3fSDimitry Andric SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX, 37625f757f3fSDimitry Andric forceMergeOpRead=true>; 3763bdd1243dSDimitry Andric } 3764bdd1243dSDimitry Andric} 3765bdd1243dSDimitry Andric 376606c3fb27SDimitry Andricmulticlass VPseudoVNCVTI_W_RM { 376706c3fb27SDimitry Andric defvar constraint = "@earlyclobber $rd"; 376806c3fb27SDimitry Andric foreach m = MxListW in { 37695f757f3fSDimitry Andric defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>, 37705f757f3fSDimitry Andric SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX, 37715f757f3fSDimitry Andric forceMergeOpRead=true>; 377206c3fb27SDimitry Andric } 377306c3fb27SDimitry Andric} 377406c3fb27SDimitry Andric 3775bdd1243dSDimitry Andricmulticlass VPseudoVNCVTI_RM_W { 3776bdd1243dSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3777bdd1243dSDimitry Andric foreach m = MxListW in { 3778647cbc5dSDimitry Andric defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>, 37795f757f3fSDimitry Andric SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX, 37805f757f3fSDimitry Andric forceMergeOpRead=true>; 3781bdd1243dSDimitry Andric } 37820eae32dcSDimitry Andric} 37830eae32dcSDimitry Andric 378406c3fb27SDimitry Andricmulticlass VPseudoVNCVTF_W_RM { 37850eae32dcSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3786bdd1243dSDimitry Andric foreach m = MxListFW in { 37875f757f3fSDimitry Andric defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>, 37885f757f3fSDimitry Andric SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, 37895f757f3fSDimitry Andric forceMergeOpRead=true>; 3790bdd1243dSDimitry Andric } 3791bdd1243dSDimitry Andric} 3792bdd1243dSDimitry Andric 3793bdd1243dSDimitry Andricmulticlass VPseudoVNCVTF_RM_W { 3794bdd1243dSDimitry Andric defvar constraint = "@earlyclobber $rd"; 3795bdd1243dSDimitry Andric foreach m = MxListFW in { 3796bdd1243dSDimitry Andric defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>, 37975f757f3fSDimitry Andric SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, 37985f757f3fSDimitry Andric forceMergeOpRead=true>; 3799bdd1243dSDimitry Andric } 38000eae32dcSDimitry Andric} 38010eae32dcSDimitry Andric 38020eae32dcSDimitry Andricmulticlass VPseudoVNCVTD_W { 3803e8d8bef9SDimitry Andric defvar constraint = "@earlyclobber $rd"; 3804bdd1243dSDimitry Andric foreach m = MxListFW in { 38055f757f3fSDimitry Andric defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>, 38065f757f3fSDimitry Andric SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 38075f757f3fSDimitry Andric forceMergeOpRead=true>; 3808bdd1243dSDimitry Andric } 3809e8d8bef9SDimitry Andric} 3810e8d8bef9SDimitry Andric 381106c3fb27SDimitry Andricmulticlass VPseudoVNCVTD_W_RM { 381206c3fb27SDimitry Andric defvar constraint = "@earlyclobber $rd"; 381306c3fb27SDimitry Andric foreach m = MxListFW in { 38145f757f3fSDimitry Andric defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>, 38155f757f3fSDimitry Andric SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 38165f757f3fSDimitry Andric forceMergeOpRead=true>; 381706c3fb27SDimitry Andric } 381806c3fb27SDimitry Andric} 381906c3fb27SDimitry Andric 382081ad6265SDimitry Andricmulticlass VPseudoUSSegLoad { 3821e8d8bef9SDimitry Andric foreach eew = EEWList in { 3822e8d8bef9SDimitry Andric foreach lmul = MxSet<eew>.m in { 3823e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 382406c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 3825e8d8bef9SDimitry Andric foreach nf = NFSet<lmul>.L in { 3826e8d8bef9SDimitry Andric defvar vreg = SegRegClass<lmul, nf>.RC; 382781ad6265SDimitry Andric def nf # "E" # eew # "_V_" # LInfo : 3828bdd1243dSDimitry Andric VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>; 382981ad6265SDimitry Andric def nf # "E" # eew # "_V_" # LInfo # "_MASK" : 3830bdd1243dSDimitry Andric VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>; 383181ad6265SDimitry Andric } 383281ad6265SDimitry Andric } 383381ad6265SDimitry Andric } 383481ad6265SDimitry Andric } 383581ad6265SDimitry Andric} 383681ad6265SDimitry Andric 383781ad6265SDimitry Andricmulticlass VPseudoUSSegLoadFF { 383881ad6265SDimitry Andric foreach eew = EEWList in { 383981ad6265SDimitry Andric foreach lmul = MxSet<eew>.m in { 384081ad6265SDimitry Andric defvar LInfo = lmul.MX; 384106c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 384281ad6265SDimitry Andric foreach nf = NFSet<lmul>.L in { 384381ad6265SDimitry Andric defvar vreg = SegRegClass<lmul, nf>.RC; 384481ad6265SDimitry Andric def nf # "E" # eew # "FF_V_" # LInfo : 3845bdd1243dSDimitry Andric VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>; 384681ad6265SDimitry Andric def nf # "E" # eew # "FF_V_" # LInfo # "_MASK" : 3847bdd1243dSDimitry Andric VPseudoUSSegLoadFFMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>; 3848e8d8bef9SDimitry Andric } 3849e8d8bef9SDimitry Andric } 3850e8d8bef9SDimitry Andric } 3851e8d8bef9SDimitry Andric } 3852e8d8bef9SDimitry Andric} 3853e8d8bef9SDimitry Andric 3854e8d8bef9SDimitry Andricmulticlass VPseudoSSegLoad { 3855e8d8bef9SDimitry Andric foreach eew = EEWList in { 3856e8d8bef9SDimitry Andric foreach lmul = MxSet<eew>.m in { 3857e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 385806c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 3859e8d8bef9SDimitry Andric foreach nf = NFSet<lmul>.L in { 3860e8d8bef9SDimitry Andric defvar vreg = SegRegClass<lmul, nf>.RC; 3861bdd1243dSDimitry Andric def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>, 3862bdd1243dSDimitry Andric VLSSEGSched<nf, eew, LInfo>; 3863bdd1243dSDimitry Andric def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>, 3864bdd1243dSDimitry Andric VLSSEGSched<nf, eew, LInfo>; 3865e8d8bef9SDimitry Andric } 3866e8d8bef9SDimitry Andric } 3867e8d8bef9SDimitry Andric } 3868e8d8bef9SDimitry Andric } 3869e8d8bef9SDimitry Andric} 3870e8d8bef9SDimitry Andric 3871fe6060f1SDimitry Andricmulticlass VPseudoISegLoad<bit Ordered> { 387206c3fb27SDimitry Andric foreach idxEEW = EEWList in { 387306c3fb27SDimitry Andric foreach dataEEW = EEWList in { 387406c3fb27SDimitry Andric foreach dataEMUL = MxSet<dataEEW>.m in { 387506c3fb27SDimitry Andric defvar dataEMULOctuple = dataEMUL.octuple; 3876fe6060f1SDimitry Andric // Calculate emul = eew * lmul / sew 387706c3fb27SDimitry Andric defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW)); 387806c3fb27SDimitry Andric if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then { 387906c3fb27SDimitry Andric defvar DataLInfo = dataEMUL.MX; 388006c3fb27SDimitry Andric defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret; 388106c3fb27SDimitry Andric defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo); 388206c3fb27SDimitry Andric defvar DataVreg = dataEMUL.vrclass; 388306c3fb27SDimitry Andric defvar IdxVreg = idxEMUL.vrclass; 388406c3fb27SDimitry Andric let VLMul = dataEMUL.value in { 388506c3fb27SDimitry Andric foreach nf = NFSet<dataEMUL>.L in { 388606c3fb27SDimitry Andric defvar Vreg = SegRegClass<dataEMUL, nf>.RC; 388706c3fb27SDimitry Andric def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo : 388806c3fb27SDimitry Andric VPseudoISegLoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, 3889bdd1243dSDimitry Andric nf, Ordered>, 38905f757f3fSDimitry Andric VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>; 389106c3fb27SDimitry Andric def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" : 389206c3fb27SDimitry Andric VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, 3893bdd1243dSDimitry Andric nf, Ordered>, 38945f757f3fSDimitry Andric VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>; 3895fe6060f1SDimitry Andric } 3896e8d8bef9SDimitry Andric } 3897e8d8bef9SDimitry Andric } 3898e8d8bef9SDimitry Andric } 3899e8d8bef9SDimitry Andric } 3900e8d8bef9SDimitry Andric } 3901e8d8bef9SDimitry Andric} 3902e8d8bef9SDimitry Andric 3903e8d8bef9SDimitry Andricmulticlass VPseudoUSSegStore { 3904e8d8bef9SDimitry Andric foreach eew = EEWList in { 3905e8d8bef9SDimitry Andric foreach lmul = MxSet<eew>.m in { 3906e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 390706c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 3908e8d8bef9SDimitry Andric foreach nf = NFSet<lmul>.L in { 3909e8d8bef9SDimitry Andric defvar vreg = SegRegClass<lmul, nf>.RC; 3910bdd1243dSDimitry Andric def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>, 3911bdd1243dSDimitry Andric VSSEGSched<nf, eew, LInfo>; 3912bdd1243dSDimitry Andric def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>, 3913bdd1243dSDimitry Andric VSSEGSched<nf, eew, LInfo>; 3914e8d8bef9SDimitry Andric } 3915e8d8bef9SDimitry Andric } 3916e8d8bef9SDimitry Andric } 3917e8d8bef9SDimitry Andric } 3918e8d8bef9SDimitry Andric} 3919e8d8bef9SDimitry Andric 3920e8d8bef9SDimitry Andricmulticlass VPseudoSSegStore { 3921e8d8bef9SDimitry Andric foreach eew = EEWList in { 3922e8d8bef9SDimitry Andric foreach lmul = MxSet<eew>.m in { 3923e8d8bef9SDimitry Andric defvar LInfo = lmul.MX; 392406c3fb27SDimitry Andric let VLMul = lmul.value, SEW=eew in { 3925e8d8bef9SDimitry Andric foreach nf = NFSet<lmul>.L in { 3926e8d8bef9SDimitry Andric defvar vreg = SegRegClass<lmul, nf>.RC; 3927bdd1243dSDimitry Andric def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>, 3928bdd1243dSDimitry Andric VSSSEGSched<nf, eew, LInfo>; 3929bdd1243dSDimitry Andric def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>, 3930bdd1243dSDimitry Andric VSSSEGSched<nf, eew, LInfo>; 3931e8d8bef9SDimitry Andric } 3932e8d8bef9SDimitry Andric } 3933e8d8bef9SDimitry Andric } 3934e8d8bef9SDimitry Andric } 3935e8d8bef9SDimitry Andric} 3936e8d8bef9SDimitry Andric 3937fe6060f1SDimitry Andricmulticlass VPseudoISegStore<bit Ordered> { 393806c3fb27SDimitry Andric foreach idxEEW = EEWList in { 393906c3fb27SDimitry Andric foreach dataEEW = EEWList in { 394006c3fb27SDimitry Andric foreach dataEMUL = MxSet<dataEEW>.m in { 394106c3fb27SDimitry Andric defvar dataEMULOctuple = dataEMUL.octuple; 3942fe6060f1SDimitry Andric // Calculate emul = eew * lmul / sew 394306c3fb27SDimitry Andric defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW)); 394406c3fb27SDimitry Andric if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then { 394506c3fb27SDimitry Andric defvar DataLInfo = dataEMUL.MX; 394606c3fb27SDimitry Andric defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret; 394706c3fb27SDimitry Andric defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo); 394806c3fb27SDimitry Andric defvar DataVreg = dataEMUL.vrclass; 394906c3fb27SDimitry Andric defvar IdxVreg = idxEMUL.vrclass; 395006c3fb27SDimitry Andric let VLMul = dataEMUL.value in { 395106c3fb27SDimitry Andric foreach nf = NFSet<dataEMUL>.L in { 395206c3fb27SDimitry Andric defvar Vreg = SegRegClass<dataEMUL, nf>.RC; 395306c3fb27SDimitry Andric def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo : 395406c3fb27SDimitry Andric VPseudoISegStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, 3955bdd1243dSDimitry Andric nf, Ordered>, 39565f757f3fSDimitry Andric VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>; 395706c3fb27SDimitry Andric def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" : 395806c3fb27SDimitry Andric VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, 3959bdd1243dSDimitry Andric nf, Ordered>, 39605f757f3fSDimitry Andric VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>; 3961fe6060f1SDimitry Andric } 3962e8d8bef9SDimitry Andric } 3963e8d8bef9SDimitry Andric } 3964e8d8bef9SDimitry Andric } 3965e8d8bef9SDimitry Andric } 3966e8d8bef9SDimitry Andric } 3967e8d8bef9SDimitry Andric} 3968e8d8bef9SDimitry Andric 3969e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 3970e8d8bef9SDimitry Andric// Helpers to define the intrinsic patterns. 3971e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 3972e8d8bef9SDimitry Andric 3973e8d8bef9SDimitry Andricclass VPatUnaryNoMask<string intrinsic_name, 3974e8d8bef9SDimitry Andric string inst, 3975e8d8bef9SDimitry Andric string kind, 3976e8d8bef9SDimitry Andric ValueType result_type, 3977e8d8bef9SDimitry Andric ValueType op2_type, 397806c3fb27SDimitry Andric int log2sew, 3979e8d8bef9SDimitry Andric LMULInfo vlmul, 398006c3fb27SDimitry Andric VReg result_reg_class, 39815f757f3fSDimitry Andric VReg op2_reg_class> : 3982e8d8bef9SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 398306c3fb27SDimitry Andric (result_type result_reg_class:$merge), 3984e8d8bef9SDimitry Andric (op2_type op2_reg_class:$rs2), 3985fe6060f1SDimitry Andric VLOpFrag)), 39865f757f3fSDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) 398706c3fb27SDimitry Andric (result_type result_reg_class:$merge), 3988e8d8bef9SDimitry Andric (op2_type op2_reg_class:$rs2), 398906c3fb27SDimitry Andric GPR:$vl, log2sew, TU_MU)>; 3990e8d8bef9SDimitry Andric 399106c3fb27SDimitry Andricclass VPatUnaryNoMaskRoundingMode<string intrinsic_name, 399281ad6265SDimitry Andric string inst, 399381ad6265SDimitry Andric string kind, 399481ad6265SDimitry Andric ValueType result_type, 399581ad6265SDimitry Andric ValueType op2_type, 399606c3fb27SDimitry Andric int log2sew, 399781ad6265SDimitry Andric LMULInfo vlmul, 399881ad6265SDimitry Andric VReg result_reg_class, 399906c3fb27SDimitry Andric VReg op2_reg_class, 400006c3fb27SDimitry Andric bit isSEWAware = 0> : 400181ad6265SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 400281ad6265SDimitry Andric (result_type result_reg_class:$merge), 400381ad6265SDimitry Andric (op2_type op2_reg_class:$rs2), 400406c3fb27SDimitry Andric (XLenVT timm:$round), 400581ad6265SDimitry Andric VLOpFrag)), 400606c3fb27SDimitry Andric (!cast<Instruction>( 400706c3fb27SDimitry Andric !if(isSEWAware, 400806c3fb27SDimitry Andric inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew), 400906c3fb27SDimitry Andric inst#"_"#kind#"_"#vlmul.MX)) 401081ad6265SDimitry Andric (result_type result_reg_class:$merge), 401181ad6265SDimitry Andric (op2_type op2_reg_class:$rs2), 401206c3fb27SDimitry Andric (XLenVT timm:$round), 401306c3fb27SDimitry Andric GPR:$vl, log2sew, TU_MU)>; 401406c3fb27SDimitry Andric 401581ad6265SDimitry Andric 4016e8d8bef9SDimitry Andricclass VPatUnaryMask<string intrinsic_name, 4017e8d8bef9SDimitry Andric string inst, 4018e8d8bef9SDimitry Andric string kind, 4019e8d8bef9SDimitry Andric ValueType result_type, 4020e8d8bef9SDimitry Andric ValueType op2_type, 4021e8d8bef9SDimitry Andric ValueType mask_type, 402206c3fb27SDimitry Andric int log2sew, 4023e8d8bef9SDimitry Andric LMULInfo vlmul, 4024e8d8bef9SDimitry Andric VReg result_reg_class, 40255f757f3fSDimitry Andric VReg op2_reg_class> : 4026349cc55cSDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 4027349cc55cSDimitry Andric (result_type result_reg_class:$merge), 4028349cc55cSDimitry Andric (op2_type op2_reg_class:$rs2), 4029349cc55cSDimitry Andric (mask_type V0), 4030349cc55cSDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 40315f757f3fSDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK") 4032349cc55cSDimitry Andric (result_type result_reg_class:$merge), 4033349cc55cSDimitry Andric (op2_type op2_reg_class:$rs2), 403406c3fb27SDimitry Andric (mask_type V0), GPR:$vl, log2sew, (XLenVT timm:$policy))>; 403506c3fb27SDimitry Andric 403606c3fb27SDimitry Andricclass VPatUnaryMaskRoundingMode<string intrinsic_name, 403706c3fb27SDimitry Andric string inst, 403806c3fb27SDimitry Andric string kind, 403906c3fb27SDimitry Andric ValueType result_type, 404006c3fb27SDimitry Andric ValueType op2_type, 404106c3fb27SDimitry Andric ValueType mask_type, 404206c3fb27SDimitry Andric int log2sew, 404306c3fb27SDimitry Andric LMULInfo vlmul, 404406c3fb27SDimitry Andric VReg result_reg_class, 404506c3fb27SDimitry Andric VReg op2_reg_class, 404606c3fb27SDimitry Andric bit isSEWAware = 0> : 404706c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 404806c3fb27SDimitry Andric (result_type result_reg_class:$merge), 404906c3fb27SDimitry Andric (op2_type op2_reg_class:$rs2), 405006c3fb27SDimitry Andric (mask_type V0), 405106c3fb27SDimitry Andric (XLenVT timm:$round), 405206c3fb27SDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 405306c3fb27SDimitry Andric (!cast<Instruction>( 405406c3fb27SDimitry Andric !if(isSEWAware, 405506c3fb27SDimitry Andric inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK", 405606c3fb27SDimitry Andric inst#"_"#kind#"_"#vlmul.MX#"_MASK")) 405706c3fb27SDimitry Andric (result_type result_reg_class:$merge), 405806c3fb27SDimitry Andric (op2_type op2_reg_class:$rs2), 405906c3fb27SDimitry Andric (mask_type V0), 406006c3fb27SDimitry Andric (XLenVT timm:$round), 406106c3fb27SDimitry Andric GPR:$vl, log2sew, (XLenVT timm:$policy))>; 406206c3fb27SDimitry Andric 4063349cc55cSDimitry Andric 4064e8d8bef9SDimitry Andricclass VPatMaskUnaryNoMask<string intrinsic_name, 4065e8d8bef9SDimitry Andric string inst, 4066e8d8bef9SDimitry Andric MTypeInfo mti> : 4067e8d8bef9SDimitry Andric Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name) 4068e8d8bef9SDimitry Andric (mti.Mask VR:$rs2), 4069fe6060f1SDimitry Andric VLOpFrag)), 4070e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_M_"#mti.BX) 407106c3fb27SDimitry Andric (mti.Mask (IMPLICIT_DEF)), 4072e8d8bef9SDimitry Andric (mti.Mask VR:$rs2), 40735f757f3fSDimitry Andric GPR:$vl, mti.Log2SEW, TA_MA)>; 4074e8d8bef9SDimitry Andric 4075e8d8bef9SDimitry Andricclass VPatMaskUnaryMask<string intrinsic_name, 4076e8d8bef9SDimitry Andric string inst, 4077e8d8bef9SDimitry Andric MTypeInfo mti> : 4078e8d8bef9SDimitry Andric Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask") 4079e8d8bef9SDimitry Andric (mti.Mask VR:$merge), 4080e8d8bef9SDimitry Andric (mti.Mask VR:$rs2), 4081e8d8bef9SDimitry Andric (mti.Mask V0), 4082fe6060f1SDimitry Andric VLOpFrag)), 4083e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK") 4084e8d8bef9SDimitry Andric (mti.Mask VR:$merge), 4085e8d8bef9SDimitry Andric (mti.Mask VR:$rs2), 408606c3fb27SDimitry Andric (mti.Mask V0), GPR:$vl, mti.Log2SEW, TU_MU)>; 4087e8d8bef9SDimitry Andric 4088e8d8bef9SDimitry Andricclass VPatUnaryAnyMask<string intrinsic, 4089e8d8bef9SDimitry Andric string inst, 4090e8d8bef9SDimitry Andric string kind, 4091e8d8bef9SDimitry Andric ValueType result_type, 4092e8d8bef9SDimitry Andric ValueType op1_type, 4093e8d8bef9SDimitry Andric ValueType mask_type, 409406c3fb27SDimitry Andric int log2sew, 4095e8d8bef9SDimitry Andric LMULInfo vlmul, 4096e8d8bef9SDimitry Andric VReg result_reg_class, 4097e8d8bef9SDimitry Andric VReg op1_reg_class> : 4098e8d8bef9SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic) 4099e8d8bef9SDimitry Andric (result_type result_reg_class:$merge), 4100e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4101e8d8bef9SDimitry Andric (mask_type VR:$rs2), 4102fe6060f1SDimitry Andric VLOpFrag)), 410306c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)) 4104e8d8bef9SDimitry Andric (result_type result_reg_class:$merge), 4105e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4106e8d8bef9SDimitry Andric (mask_type VR:$rs2), 410706c3fb27SDimitry Andric GPR:$vl, log2sew)>; 4108e8d8bef9SDimitry Andric 410981ad6265SDimitry Andricclass VPatBinaryM<string intrinsic_name, 4110e8d8bef9SDimitry Andric string inst, 4111e8d8bef9SDimitry Andric ValueType result_type, 4112e8d8bef9SDimitry Andric ValueType op1_type, 4113e8d8bef9SDimitry Andric ValueType op2_type, 4114e8d8bef9SDimitry Andric int sew, 4115e8d8bef9SDimitry Andric VReg op1_reg_class, 4116e8d8bef9SDimitry Andric DAGOperand op2_kind> : 4117e8d8bef9SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 4118e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4119e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4120fe6060f1SDimitry Andric VLOpFrag)), 4121fe6060f1SDimitry Andric (!cast<Instruction>(inst) 4122fe6060f1SDimitry Andric (op1_type op1_reg_class:$rs1), 4123fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 4124fe6060f1SDimitry Andric GPR:$vl, sew)>; 4125fe6060f1SDimitry Andric 412681ad6265SDimitry Andricclass VPatBinaryNoMaskTU<string intrinsic_name, 412781ad6265SDimitry Andric string inst, 412881ad6265SDimitry Andric ValueType result_type, 412981ad6265SDimitry Andric ValueType op1_type, 413081ad6265SDimitry Andric ValueType op2_type, 413181ad6265SDimitry Andric int sew, 413281ad6265SDimitry Andric VReg result_reg_class, 413381ad6265SDimitry Andric VReg op1_reg_class, 413481ad6265SDimitry Andric DAGOperand op2_kind> : 413581ad6265SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 413681ad6265SDimitry Andric (result_type result_reg_class:$merge), 413781ad6265SDimitry Andric (op1_type op1_reg_class:$rs1), 413881ad6265SDimitry Andric (op2_type op2_kind:$rs2), 413981ad6265SDimitry Andric VLOpFrag)), 414006c3fb27SDimitry Andric (!cast<Instruction>(inst) 414181ad6265SDimitry Andric (result_type result_reg_class:$merge), 414281ad6265SDimitry Andric (op1_type op1_reg_class:$rs1), 414381ad6265SDimitry Andric (op2_type op2_kind:$rs2), 414406c3fb27SDimitry Andric GPR:$vl, sew, TU_MU)>; 414506c3fb27SDimitry Andric 414606c3fb27SDimitry Andricclass VPatBinaryNoMaskRoundingMode<string intrinsic_name, 414706c3fb27SDimitry Andric string inst, 414806c3fb27SDimitry Andric ValueType result_type, 414906c3fb27SDimitry Andric ValueType op1_type, 415006c3fb27SDimitry Andric ValueType op2_type, 415106c3fb27SDimitry Andric int sew, 415206c3fb27SDimitry Andric VReg op1_reg_class, 415306c3fb27SDimitry Andric DAGOperand op2_kind> : 415406c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 415506c3fb27SDimitry Andric (result_type (undef)), 415606c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 415706c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 415806c3fb27SDimitry Andric (XLenVT timm:$round), 415906c3fb27SDimitry Andric VLOpFrag)), 416006c3fb27SDimitry Andric (!cast<Instruction>(inst) 416106c3fb27SDimitry Andric (result_type (IMPLICIT_DEF)), 416206c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 416306c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 416406c3fb27SDimitry Andric (XLenVT timm:$round), 416506c3fb27SDimitry Andric GPR:$vl, sew, TA_MA)>; 416606c3fb27SDimitry Andric 416706c3fb27SDimitry Andricclass VPatBinaryNoMaskTURoundingMode<string intrinsic_name, 416806c3fb27SDimitry Andric string inst, 416906c3fb27SDimitry Andric ValueType result_type, 417006c3fb27SDimitry Andric ValueType op1_type, 417106c3fb27SDimitry Andric ValueType op2_type, 417206c3fb27SDimitry Andric int sew, 417306c3fb27SDimitry Andric VReg result_reg_class, 417406c3fb27SDimitry Andric VReg op1_reg_class, 417506c3fb27SDimitry Andric DAGOperand op2_kind> : 417606c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 417706c3fb27SDimitry Andric (result_type result_reg_class:$merge), 417806c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 417906c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 418006c3fb27SDimitry Andric (XLenVT timm:$round), 418106c3fb27SDimitry Andric VLOpFrag)), 418206c3fb27SDimitry Andric (!cast<Instruction>(inst) 418306c3fb27SDimitry Andric (result_type result_reg_class:$merge), 418406c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 418506c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 418606c3fb27SDimitry Andric (XLenVT timm:$round), 418706c3fb27SDimitry Andric GPR:$vl, sew, TU_MU)>; 418806c3fb27SDimitry Andric 418981ad6265SDimitry Andric 4190fe6060f1SDimitry Andric// Same as above but source operands are swapped. 4191fe6060f1SDimitry Andricclass VPatBinaryNoMaskSwapped<string intrinsic_name, 4192fe6060f1SDimitry Andric string inst, 4193fe6060f1SDimitry Andric ValueType result_type, 4194fe6060f1SDimitry Andric ValueType op1_type, 4195fe6060f1SDimitry Andric ValueType op2_type, 4196fe6060f1SDimitry Andric int sew, 4197fe6060f1SDimitry Andric VReg op1_reg_class, 4198fe6060f1SDimitry Andric DAGOperand op2_kind> : 4199fe6060f1SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 4200fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 4201fe6060f1SDimitry Andric (op1_type op1_reg_class:$rs1), 4202fe6060f1SDimitry Andric VLOpFrag)), 4203e8d8bef9SDimitry Andric (!cast<Instruction>(inst) 4204e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4205e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4206d409305fSDimitry Andric GPR:$vl, sew)>; 4207e8d8bef9SDimitry Andric 4208e8d8bef9SDimitry Andricclass VPatBinaryMask<string intrinsic_name, 4209e8d8bef9SDimitry Andric string inst, 4210e8d8bef9SDimitry Andric ValueType result_type, 4211e8d8bef9SDimitry Andric ValueType op1_type, 4212e8d8bef9SDimitry Andric ValueType op2_type, 4213e8d8bef9SDimitry Andric ValueType mask_type, 4214e8d8bef9SDimitry Andric int sew, 4215e8d8bef9SDimitry Andric VReg result_reg_class, 4216e8d8bef9SDimitry Andric VReg op1_reg_class, 4217e8d8bef9SDimitry Andric DAGOperand op2_kind> : 4218e8d8bef9SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 4219e8d8bef9SDimitry Andric (result_type result_reg_class:$merge), 4220e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4221e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4222e8d8bef9SDimitry Andric (mask_type V0), 4223fe6060f1SDimitry Andric VLOpFrag)), 4224e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_MASK") 4225e8d8bef9SDimitry Andric (result_type result_reg_class:$merge), 4226e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4227e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4228d409305fSDimitry Andric (mask_type V0), GPR:$vl, sew)>; 4229e8d8bef9SDimitry Andric 4230349cc55cSDimitry Andricclass VPatBinaryMaskTA<string intrinsic_name, 4231349cc55cSDimitry Andric string inst, 4232349cc55cSDimitry Andric ValueType result_type, 4233349cc55cSDimitry Andric ValueType op1_type, 4234349cc55cSDimitry Andric ValueType op2_type, 4235349cc55cSDimitry Andric ValueType mask_type, 4236349cc55cSDimitry Andric int sew, 4237349cc55cSDimitry Andric VReg result_reg_class, 4238349cc55cSDimitry Andric VReg op1_reg_class, 4239349cc55cSDimitry Andric DAGOperand op2_kind> : 4240349cc55cSDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 4241349cc55cSDimitry Andric (result_type result_reg_class:$merge), 4242349cc55cSDimitry Andric (op1_type op1_reg_class:$rs1), 4243349cc55cSDimitry Andric (op2_type op2_kind:$rs2), 4244349cc55cSDimitry Andric (mask_type V0), 4245349cc55cSDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 4246349cc55cSDimitry Andric (!cast<Instruction>(inst#"_MASK") 4247349cc55cSDimitry Andric (result_type result_reg_class:$merge), 4248349cc55cSDimitry Andric (op1_type op1_reg_class:$rs1), 4249349cc55cSDimitry Andric (op2_type op2_kind:$rs2), 4250349cc55cSDimitry Andric (mask_type V0), GPR:$vl, sew, (XLenVT timm:$policy))>; 4251349cc55cSDimitry Andric 425206c3fb27SDimitry Andricclass VPatBinaryMaskTARoundingMode<string intrinsic_name, 425306c3fb27SDimitry Andric string inst, 425406c3fb27SDimitry Andric ValueType result_type, 425506c3fb27SDimitry Andric ValueType op1_type, 425606c3fb27SDimitry Andric ValueType op2_type, 425706c3fb27SDimitry Andric ValueType mask_type, 425806c3fb27SDimitry Andric int sew, 425906c3fb27SDimitry Andric VReg result_reg_class, 426006c3fb27SDimitry Andric VReg op1_reg_class, 426106c3fb27SDimitry Andric DAGOperand op2_kind> : 426206c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 426306c3fb27SDimitry Andric (result_type result_reg_class:$merge), 426406c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 426506c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 426606c3fb27SDimitry Andric (mask_type V0), 426706c3fb27SDimitry Andric (XLenVT timm:$round), 426806c3fb27SDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 426906c3fb27SDimitry Andric (!cast<Instruction>(inst#"_MASK") 427006c3fb27SDimitry Andric (result_type result_reg_class:$merge), 427106c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 427206c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 427306c3fb27SDimitry Andric (mask_type V0), 427406c3fb27SDimitry Andric (XLenVT timm:$round), 427506c3fb27SDimitry Andric GPR:$vl, sew, (XLenVT timm:$policy))>; 427606c3fb27SDimitry Andric 4277fe6060f1SDimitry Andric// Same as above but source operands are swapped. 4278fe6060f1SDimitry Andricclass VPatBinaryMaskSwapped<string intrinsic_name, 4279fe6060f1SDimitry Andric string inst, 4280fe6060f1SDimitry Andric ValueType result_type, 4281fe6060f1SDimitry Andric ValueType op1_type, 4282fe6060f1SDimitry Andric ValueType op2_type, 4283fe6060f1SDimitry Andric ValueType mask_type, 4284fe6060f1SDimitry Andric int sew, 4285fe6060f1SDimitry Andric VReg result_reg_class, 4286fe6060f1SDimitry Andric VReg op1_reg_class, 4287fe6060f1SDimitry Andric DAGOperand op2_kind> : 4288fe6060f1SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 4289fe6060f1SDimitry Andric (result_type result_reg_class:$merge), 4290fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 4291fe6060f1SDimitry Andric (op1_type op1_reg_class:$rs1), 4292fe6060f1SDimitry Andric (mask_type V0), 4293fe6060f1SDimitry Andric VLOpFrag)), 4294fe6060f1SDimitry Andric (!cast<Instruction>(inst#"_MASK") 4295fe6060f1SDimitry Andric (result_type result_reg_class:$merge), 4296fe6060f1SDimitry Andric (op1_type op1_reg_class:$rs1), 4297fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 4298fe6060f1SDimitry Andric (mask_type V0), GPR:$vl, sew)>; 4299fe6060f1SDimitry Andric 4300fe6060f1SDimitry Andricclass VPatTiedBinaryNoMask<string intrinsic_name, 4301fe6060f1SDimitry Andric string inst, 4302fe6060f1SDimitry Andric ValueType result_type, 4303fe6060f1SDimitry Andric ValueType op2_type, 4304fe6060f1SDimitry Andric int sew, 4305fe6060f1SDimitry Andric VReg result_reg_class, 4306fe6060f1SDimitry Andric DAGOperand op2_kind> : 4307fe6060f1SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 430881ad6265SDimitry Andric (result_type (undef)), 4309fe6060f1SDimitry Andric (result_type result_reg_class:$rs1), 4310fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 4311fe6060f1SDimitry Andric VLOpFrag)), 4312fe6060f1SDimitry Andric (!cast<Instruction>(inst#"_TIED") 4313fe6060f1SDimitry Andric (result_type result_reg_class:$rs1), 4314fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 431581ad6265SDimitry Andric GPR:$vl, sew, TAIL_AGNOSTIC)>; 431681ad6265SDimitry Andric 431706c3fb27SDimitry Andricclass VPatTiedBinaryNoMaskRoundingMode<string intrinsic_name, 431806c3fb27SDimitry Andric string inst, 431906c3fb27SDimitry Andric ValueType result_type, 432006c3fb27SDimitry Andric ValueType op2_type, 432106c3fb27SDimitry Andric int sew, 432206c3fb27SDimitry Andric VReg result_reg_class, 432306c3fb27SDimitry Andric DAGOperand op2_kind> : 432406c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 432506c3fb27SDimitry Andric (result_type (undef)), 432606c3fb27SDimitry Andric (result_type result_reg_class:$rs1), 432706c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 432806c3fb27SDimitry Andric (XLenVT timm:$round), 432906c3fb27SDimitry Andric VLOpFrag)), 433006c3fb27SDimitry Andric (!cast<Instruction>(inst#"_TIED") 433106c3fb27SDimitry Andric (result_type result_reg_class:$rs1), 433206c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 433306c3fb27SDimitry Andric (XLenVT timm:$round), 433406c3fb27SDimitry Andric GPR:$vl, sew, TAIL_AGNOSTIC)>; 433506c3fb27SDimitry Andric 433681ad6265SDimitry Andricclass VPatTiedBinaryNoMaskTU<string intrinsic_name, 433781ad6265SDimitry Andric string inst, 433881ad6265SDimitry Andric ValueType result_type, 433981ad6265SDimitry Andric ValueType op2_type, 434081ad6265SDimitry Andric int sew, 434181ad6265SDimitry Andric VReg result_reg_class, 434281ad6265SDimitry Andric DAGOperand op2_kind> : 434381ad6265SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 434481ad6265SDimitry Andric (result_type result_reg_class:$merge), 434581ad6265SDimitry Andric (result_type result_reg_class:$merge), 434681ad6265SDimitry Andric (op2_type op2_kind:$rs2), 434781ad6265SDimitry Andric VLOpFrag)), 434881ad6265SDimitry Andric (!cast<Instruction>(inst#"_TIED") 434981ad6265SDimitry Andric (result_type result_reg_class:$merge), 435081ad6265SDimitry Andric (op2_type op2_kind:$rs2), 435106c3fb27SDimitry Andric GPR:$vl, sew, TU_MU)>; 435206c3fb27SDimitry Andric 435306c3fb27SDimitry Andricclass VPatTiedBinaryNoMaskTURoundingMode<string intrinsic_name, 435406c3fb27SDimitry Andric string inst, 435506c3fb27SDimitry Andric ValueType result_type, 435606c3fb27SDimitry Andric ValueType op2_type, 435706c3fb27SDimitry Andric int sew, 435806c3fb27SDimitry Andric VReg result_reg_class, 435906c3fb27SDimitry Andric DAGOperand op2_kind> : 436006c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 436106c3fb27SDimitry Andric (result_type result_reg_class:$merge), 436206c3fb27SDimitry Andric (result_type result_reg_class:$merge), 436306c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 436406c3fb27SDimitry Andric (XLenVT timm:$round), 436506c3fb27SDimitry Andric VLOpFrag)), 436606c3fb27SDimitry Andric (!cast<Instruction>(inst#"_TIED") 436706c3fb27SDimitry Andric (result_type result_reg_class:$merge), 436806c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 436906c3fb27SDimitry Andric (XLenVT timm:$round), 437006c3fb27SDimitry Andric GPR:$vl, sew, TU_MU)>; 4371fe6060f1SDimitry Andric 4372fe6060f1SDimitry Andricclass VPatTiedBinaryMask<string intrinsic_name, 4373fe6060f1SDimitry Andric string inst, 4374fe6060f1SDimitry Andric ValueType result_type, 4375fe6060f1SDimitry Andric ValueType op2_type, 4376fe6060f1SDimitry Andric ValueType mask_type, 4377fe6060f1SDimitry Andric int sew, 4378fe6060f1SDimitry Andric VReg result_reg_class, 4379fe6060f1SDimitry Andric DAGOperand op2_kind> : 4380fe6060f1SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 4381fe6060f1SDimitry Andric (result_type result_reg_class:$merge), 4382fe6060f1SDimitry Andric (result_type result_reg_class:$merge), 4383fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 4384fe6060f1SDimitry Andric (mask_type V0), 4385349cc55cSDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 4386fe6060f1SDimitry Andric (!cast<Instruction>(inst#"_MASK_TIED") 4387fe6060f1SDimitry Andric (result_type result_reg_class:$merge), 4388fe6060f1SDimitry Andric (op2_type op2_kind:$rs2), 4389349cc55cSDimitry Andric (mask_type V0), GPR:$vl, sew, (XLenVT timm:$policy))>; 4390fe6060f1SDimitry Andric 439106c3fb27SDimitry Andricclass VPatTiedBinaryMaskRoundingMode<string intrinsic_name, 439206c3fb27SDimitry Andric string inst, 439306c3fb27SDimitry Andric ValueType result_type, 439406c3fb27SDimitry Andric ValueType op2_type, 439506c3fb27SDimitry Andric ValueType mask_type, 439606c3fb27SDimitry Andric int sew, 439706c3fb27SDimitry Andric VReg result_reg_class, 439806c3fb27SDimitry Andric DAGOperand op2_kind> : 439906c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") 440006c3fb27SDimitry Andric (result_type result_reg_class:$merge), 440106c3fb27SDimitry Andric (result_type result_reg_class:$merge), 440206c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 440306c3fb27SDimitry Andric (mask_type V0), 440406c3fb27SDimitry Andric (XLenVT timm:$round), 440506c3fb27SDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 440606c3fb27SDimitry Andric (!cast<Instruction>(inst#"_MASK_TIED") 440706c3fb27SDimitry Andric (result_type result_reg_class:$merge), 440806c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 440906c3fb27SDimitry Andric (mask_type V0), 441006c3fb27SDimitry Andric (XLenVT timm:$round), 441106c3fb27SDimitry Andric GPR:$vl, sew, (XLenVT timm:$policy))>; 441206c3fb27SDimitry Andric 4413e8d8bef9SDimitry Andricclass VPatTernaryNoMask<string intrinsic, 4414e8d8bef9SDimitry Andric string inst, 4415e8d8bef9SDimitry Andric string kind, 4416e8d8bef9SDimitry Andric ValueType result_type, 4417e8d8bef9SDimitry Andric ValueType op1_type, 4418e8d8bef9SDimitry Andric ValueType op2_type, 4419e8d8bef9SDimitry Andric int sew, 4420e8d8bef9SDimitry Andric LMULInfo vlmul, 4421e8d8bef9SDimitry Andric VReg result_reg_class, 4422e8d8bef9SDimitry Andric RegisterClass op1_reg_class, 4423e8d8bef9SDimitry Andric DAGOperand op2_kind> : 4424e8d8bef9SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic) 4425e8d8bef9SDimitry Andric (result_type result_reg_class:$rs3), 4426e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4427e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4428fe6060f1SDimitry Andric VLOpFrag)), 4429e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) 4430e8d8bef9SDimitry Andric result_reg_class:$rs3, 4431e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4432e8d8bef9SDimitry Andric op2_kind:$rs2, 4433d409305fSDimitry Andric GPR:$vl, sew)>; 4434e8d8bef9SDimitry Andric 443506c3fb27SDimitry Andricclass VPatTernaryNoMaskTA<string intrinsic, 443606c3fb27SDimitry Andric string inst, 443706c3fb27SDimitry Andric string kind, 443806c3fb27SDimitry Andric ValueType result_type, 443906c3fb27SDimitry Andric ValueType op1_type, 444006c3fb27SDimitry Andric ValueType op2_type, 444106c3fb27SDimitry Andric int log2sew, 444206c3fb27SDimitry Andric LMULInfo vlmul, 444306c3fb27SDimitry Andric VReg result_reg_class, 444406c3fb27SDimitry Andric RegisterClass op1_reg_class, 444506c3fb27SDimitry Andric DAGOperand op2_kind> : 444606c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic) 444706c3fb27SDimitry Andric (result_type result_reg_class:$rs3), 444806c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 444906c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 445006c3fb27SDimitry Andric VLOpFrag)), 445106c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)) 445206c3fb27SDimitry Andric result_reg_class:$rs3, 445306c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 445406c3fb27SDimitry Andric op2_kind:$rs2, 445506c3fb27SDimitry Andric GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 445606c3fb27SDimitry Andric 445706c3fb27SDimitry Andricclass VPatTernaryNoMaskTARoundingMode<string intrinsic, 445806c3fb27SDimitry Andric string inst, 445906c3fb27SDimitry Andric string kind, 446006c3fb27SDimitry Andric ValueType result_type, 446106c3fb27SDimitry Andric ValueType op1_type, 446206c3fb27SDimitry Andric ValueType op2_type, 446306c3fb27SDimitry Andric int log2sew, 446406c3fb27SDimitry Andric LMULInfo vlmul, 446506c3fb27SDimitry Andric VReg result_reg_class, 446606c3fb27SDimitry Andric RegisterClass op1_reg_class, 446706c3fb27SDimitry Andric DAGOperand op2_kind> : 446806c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic) 446906c3fb27SDimitry Andric (result_type result_reg_class:$rs3), 447006c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 447106c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 447206c3fb27SDimitry Andric (XLenVT timm:$round), 447306c3fb27SDimitry Andric VLOpFrag)), 447406c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)) 447506c3fb27SDimitry Andric result_reg_class:$rs3, 447606c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 447706c3fb27SDimitry Andric op2_kind:$rs2, 447806c3fb27SDimitry Andric (XLenVT timm:$round), 447906c3fb27SDimitry Andric GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 448006c3fb27SDimitry Andric 4481349cc55cSDimitry Andricclass VPatTernaryNoMaskWithPolicy<string intrinsic, 4482349cc55cSDimitry Andric string inst, 4483349cc55cSDimitry Andric string kind, 4484349cc55cSDimitry Andric ValueType result_type, 4485349cc55cSDimitry Andric ValueType op1_type, 4486349cc55cSDimitry Andric ValueType op2_type, 4487349cc55cSDimitry Andric int sew, 4488349cc55cSDimitry Andric LMULInfo vlmul, 4489349cc55cSDimitry Andric VReg result_reg_class, 4490349cc55cSDimitry Andric RegisterClass op1_reg_class, 4491349cc55cSDimitry Andric DAGOperand op2_kind> : 4492349cc55cSDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic) 4493349cc55cSDimitry Andric (result_type result_reg_class:$rs3), 4494349cc55cSDimitry Andric (op1_type op1_reg_class:$rs1), 4495349cc55cSDimitry Andric (op2_type op2_kind:$rs2), 449681ad6265SDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 4497349cc55cSDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) 4498349cc55cSDimitry Andric result_reg_class:$rs3, 4499349cc55cSDimitry Andric (op1_type op1_reg_class:$rs1), 4500349cc55cSDimitry Andric op2_kind:$rs2, 450181ad6265SDimitry Andric GPR:$vl, sew, (XLenVT timm:$policy))>; 4502349cc55cSDimitry Andric 450306c3fb27SDimitry Andricclass VPatTernaryNoMaskWithPolicyRoundingMode<string intrinsic, 450406c3fb27SDimitry Andric string inst, 450506c3fb27SDimitry Andric string kind, 450606c3fb27SDimitry Andric ValueType result_type, 450706c3fb27SDimitry Andric ValueType op1_type, 450806c3fb27SDimitry Andric ValueType op2_type, 450906c3fb27SDimitry Andric int sew, 451006c3fb27SDimitry Andric LMULInfo vlmul, 451106c3fb27SDimitry Andric VReg result_reg_class, 451206c3fb27SDimitry Andric RegisterClass op1_reg_class, 451306c3fb27SDimitry Andric DAGOperand op2_kind> : 451406c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic) 451506c3fb27SDimitry Andric (result_type result_reg_class:$rs3), 451606c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 451706c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 451806c3fb27SDimitry Andric (XLenVT timm:$round), 451906c3fb27SDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 452006c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) 452106c3fb27SDimitry Andric result_reg_class:$rs3, 452206c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 452306c3fb27SDimitry Andric op2_kind:$rs2, 452406c3fb27SDimitry Andric (XLenVT timm:$round), 452506c3fb27SDimitry Andric GPR:$vl, sew, (XLenVT timm:$policy))>; 452606c3fb27SDimitry Andric 4527e8d8bef9SDimitry Andricclass VPatTernaryMask<string intrinsic, 4528e8d8bef9SDimitry Andric string inst, 4529e8d8bef9SDimitry Andric string kind, 4530e8d8bef9SDimitry Andric ValueType result_type, 4531e8d8bef9SDimitry Andric ValueType op1_type, 4532e8d8bef9SDimitry Andric ValueType op2_type, 4533e8d8bef9SDimitry Andric ValueType mask_type, 4534e8d8bef9SDimitry Andric int sew, 4535e8d8bef9SDimitry Andric LMULInfo vlmul, 4536e8d8bef9SDimitry Andric VReg result_reg_class, 4537e8d8bef9SDimitry Andric RegisterClass op1_reg_class, 4538e8d8bef9SDimitry Andric DAGOperand op2_kind> : 4539e8d8bef9SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask") 4540e8d8bef9SDimitry Andric (result_type result_reg_class:$rs3), 4541e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4542e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4543e8d8bef9SDimitry Andric (mask_type V0), 4544fe6060f1SDimitry Andric VLOpFrag)), 4545e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") 4546e8d8bef9SDimitry Andric result_reg_class:$rs3, 4547e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4548e8d8bef9SDimitry Andric op2_kind:$rs2, 4549e8d8bef9SDimitry Andric (mask_type V0), 4550d409305fSDimitry Andric GPR:$vl, sew)>; 4551e8d8bef9SDimitry Andric 455281ad6265SDimitry Andricclass VPatTernaryMaskPolicy<string intrinsic, 455381ad6265SDimitry Andric string inst, 455481ad6265SDimitry Andric string kind, 455581ad6265SDimitry Andric ValueType result_type, 455681ad6265SDimitry Andric ValueType op1_type, 455781ad6265SDimitry Andric ValueType op2_type, 455881ad6265SDimitry Andric ValueType mask_type, 455981ad6265SDimitry Andric int sew, 456081ad6265SDimitry Andric LMULInfo vlmul, 456181ad6265SDimitry Andric VReg result_reg_class, 456281ad6265SDimitry Andric RegisterClass op1_reg_class, 456381ad6265SDimitry Andric DAGOperand op2_kind> : 456481ad6265SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask") 456581ad6265SDimitry Andric (result_type result_reg_class:$rs3), 456681ad6265SDimitry Andric (op1_type op1_reg_class:$rs1), 456781ad6265SDimitry Andric (op2_type op2_kind:$rs2), 456881ad6265SDimitry Andric (mask_type V0), 456981ad6265SDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 457081ad6265SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") 457181ad6265SDimitry Andric result_reg_class:$rs3, 457281ad6265SDimitry Andric (op1_type op1_reg_class:$rs1), 457381ad6265SDimitry Andric op2_kind:$rs2, 457481ad6265SDimitry Andric (mask_type V0), 457581ad6265SDimitry Andric GPR:$vl, sew, (XLenVT timm:$policy))>; 457681ad6265SDimitry Andric 457706c3fb27SDimitry Andricclass VPatTernaryMaskPolicyRoundingMode<string intrinsic, 457806c3fb27SDimitry Andric string inst, 457906c3fb27SDimitry Andric string kind, 458006c3fb27SDimitry Andric ValueType result_type, 458106c3fb27SDimitry Andric ValueType op1_type, 458206c3fb27SDimitry Andric ValueType op2_type, 458306c3fb27SDimitry Andric ValueType mask_type, 458406c3fb27SDimitry Andric int sew, 458506c3fb27SDimitry Andric LMULInfo vlmul, 458606c3fb27SDimitry Andric VReg result_reg_class, 458706c3fb27SDimitry Andric RegisterClass op1_reg_class, 458806c3fb27SDimitry Andric DAGOperand op2_kind> : 458906c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask") 459006c3fb27SDimitry Andric (result_type result_reg_class:$rs3), 459106c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 459206c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 459306c3fb27SDimitry Andric (mask_type V0), 459406c3fb27SDimitry Andric (XLenVT timm:$round), 459506c3fb27SDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 459606c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") 459706c3fb27SDimitry Andric result_reg_class:$rs3, 459806c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 459906c3fb27SDimitry Andric op2_kind:$rs2, 460006c3fb27SDimitry Andric (mask_type V0), 460106c3fb27SDimitry Andric (XLenVT timm:$round), 460206c3fb27SDimitry Andric GPR:$vl, sew, (XLenVT timm:$policy))>; 460306c3fb27SDimitry Andric 460406c3fb27SDimitry Andricclass VPatTernaryMaskTA<string intrinsic, 460506c3fb27SDimitry Andric string inst, 460606c3fb27SDimitry Andric string kind, 460706c3fb27SDimitry Andric ValueType result_type, 460806c3fb27SDimitry Andric ValueType op1_type, 460906c3fb27SDimitry Andric ValueType op2_type, 461006c3fb27SDimitry Andric ValueType mask_type, 461106c3fb27SDimitry Andric int log2sew, 461206c3fb27SDimitry Andric LMULInfo vlmul, 461306c3fb27SDimitry Andric VReg result_reg_class, 461406c3fb27SDimitry Andric RegisterClass op1_reg_class, 461506c3fb27SDimitry Andric DAGOperand op2_kind> : 461606c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask") 461706c3fb27SDimitry Andric (result_type result_reg_class:$rs3), 461806c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 461906c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 462006c3fb27SDimitry Andric (mask_type V0), 462106c3fb27SDimitry Andric VLOpFrag)), 462206c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)# "_MASK") 462306c3fb27SDimitry Andric result_reg_class:$rs3, 462406c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 462506c3fb27SDimitry Andric op2_kind:$rs2, 462606c3fb27SDimitry Andric (mask_type V0), 462706c3fb27SDimitry Andric GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 462806c3fb27SDimitry Andric 462906c3fb27SDimitry Andricclass VPatTernaryMaskTARoundingMode<string intrinsic, 463006c3fb27SDimitry Andric string inst, 463106c3fb27SDimitry Andric string kind, 463206c3fb27SDimitry Andric ValueType result_type, 463306c3fb27SDimitry Andric ValueType op1_type, 463406c3fb27SDimitry Andric ValueType op2_type, 463506c3fb27SDimitry Andric ValueType mask_type, 463606c3fb27SDimitry Andric int log2sew, 463706c3fb27SDimitry Andric LMULInfo vlmul, 463806c3fb27SDimitry Andric VReg result_reg_class, 463906c3fb27SDimitry Andric RegisterClass op1_reg_class, 464006c3fb27SDimitry Andric DAGOperand op2_kind> : 464106c3fb27SDimitry Andric Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask") 464206c3fb27SDimitry Andric (result_type result_reg_class:$rs3), 464306c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 464406c3fb27SDimitry Andric (op2_type op2_kind:$rs2), 464506c3fb27SDimitry Andric (mask_type V0), 464606c3fb27SDimitry Andric (XLenVT timm:$round), 464706c3fb27SDimitry Andric VLOpFrag)), 464806c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)# "_MASK") 464906c3fb27SDimitry Andric result_reg_class:$rs3, 465006c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 465106c3fb27SDimitry Andric op2_kind:$rs2, 465206c3fb27SDimitry Andric (mask_type V0), 465306c3fb27SDimitry Andric (XLenVT timm:$round), 465406c3fb27SDimitry Andric GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 465506c3fb27SDimitry Andric 4656e8d8bef9SDimitry Andricmulticlass VPatUnaryS_M<string intrinsic_name, 465706c3fb27SDimitry Andric string inst> { 4658e8d8bef9SDimitry Andric foreach mti = AllMasks in { 4659e8d8bef9SDimitry Andric def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name) 4660fe6060f1SDimitry Andric (mti.Mask VR:$rs1), VLOpFrag)), 4661e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_M_"#mti.BX) $rs1, 4662fe6060f1SDimitry Andric GPR:$vl, mti.Log2SEW)>; 4663e8d8bef9SDimitry Andric def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name # "_mask") 4664fe6060f1SDimitry Andric (mti.Mask VR:$rs1), (mti.Mask V0), VLOpFrag)), 4665e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK") $rs1, 4666fe6060f1SDimitry Andric (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 4667e8d8bef9SDimitry Andric } 4668e8d8bef9SDimitry Andric} 4669e8d8bef9SDimitry Andric 4670e8d8bef9SDimitry Andricmulticlass VPatUnaryV_V_AnyMask<string intrinsic, string instruction, 4671e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 4672e8d8bef9SDimitry Andric foreach vti = vtilist in { 467306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 4674e8d8bef9SDimitry Andric def : VPatUnaryAnyMask<intrinsic, instruction, "VM", 4675e8d8bef9SDimitry Andric vti.Vector, vti.Vector, vti.Mask, 467606c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 4677e8d8bef9SDimitry Andric } 4678e8d8bef9SDimitry Andric} 4679e8d8bef9SDimitry Andric 4680e8d8bef9SDimitry Andricmulticlass VPatUnaryM_M<string intrinsic, 468106c3fb27SDimitry Andric string inst> { 4682e8d8bef9SDimitry Andric foreach mti = AllMasks in { 4683e8d8bef9SDimitry Andric def : VPatMaskUnaryNoMask<intrinsic, inst, mti>; 4684e8d8bef9SDimitry Andric def : VPatMaskUnaryMask<intrinsic, inst, mti>; 4685e8d8bef9SDimitry Andric } 4686e8d8bef9SDimitry Andric} 4687e8d8bef9SDimitry Andric 468806c3fb27SDimitry Andricmulticlass VPatUnaryV_M<string intrinsic, string instruction> { 4689e8d8bef9SDimitry Andric foreach vti = AllIntegerVectors in { 469006c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 4691e8d8bef9SDimitry Andric def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask, 469281ad6265SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, VR>; 469306c3fb27SDimitry Andric def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask, 4694fe6060f1SDimitry Andric vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>; 4695e8d8bef9SDimitry Andric } 4696e8d8bef9SDimitry Andric } 469706c3fb27SDimitry Andric} 4698e8d8bef9SDimitry Andric 4699e8d8bef9SDimitry Andricmulticlass VPatUnaryV_VF<string intrinsic, string instruction, string suffix, 470006c3fb27SDimitry Andric list<VTypeInfoToFraction> fractionList> { 470106c3fb27SDimitry Andric foreach vtiTofti = fractionList in { 4702e8d8bef9SDimitry Andric defvar vti = vtiTofti.Vti; 4703e8d8bef9SDimitry Andric defvar fti = vtiTofti.Fti; 470406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 470506c3fb27SDimitry Andric GetVTypePredicates<fti>.Predicates) in { 4706e8d8bef9SDimitry Andric def : VPatUnaryNoMask<intrinsic, instruction, suffix, 4707e8d8bef9SDimitry Andric vti.Vector, fti.Vector, 470881ad6265SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>; 470906c3fb27SDimitry Andric def : VPatUnaryMask<intrinsic, instruction, suffix, 4710e8d8bef9SDimitry Andric vti.Vector, fti.Vector, vti.Mask, 4711fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>; 4712e8d8bef9SDimitry Andric } 4713e8d8bef9SDimitry Andric } 471406c3fb27SDimitry Andric} 4715e8d8bef9SDimitry Andric 4716e8d8bef9SDimitry Andricmulticlass VPatUnaryV_V<string intrinsic, string instruction, 47175f757f3fSDimitry Andric list<VTypeInfo> vtilist> { 4718e8d8bef9SDimitry Andric foreach vti = vtilist in { 471906c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 4720e8d8bef9SDimitry Andric def : VPatUnaryNoMask<intrinsic, instruction, "V", 472106c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Log2SEW, 47225f757f3fSDimitry Andric vti.LMul, vti.RegClass, vti.RegClass>; 472306c3fb27SDimitry Andric def : VPatUnaryMask<intrinsic, instruction, "V", 472406c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 47255f757f3fSDimitry Andric vti.LMul, vti.RegClass, vti.RegClass>; 472606c3fb27SDimitry Andric } 4727e8d8bef9SDimitry Andric } 4728e8d8bef9SDimitry Andric} 4729e8d8bef9SDimitry Andric 473006c3fb27SDimitry Andricmulticlass VPatUnaryV_V_RM<string intrinsic, string instruction, 473106c3fb27SDimitry Andric list<VTypeInfo> vtilist, bit isSEWAware = 0> { 473206c3fb27SDimitry Andric foreach vti = vtilist in { 473306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 473406c3fb27SDimitry Andric def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "V", 473506c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Log2SEW, 473606c3fb27SDimitry Andric vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>; 473706c3fb27SDimitry Andric def : VPatUnaryMaskRoundingMode<intrinsic, instruction, "V", 473806c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 473906c3fb27SDimitry Andric vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>; 474006c3fb27SDimitry Andric } 474106c3fb27SDimitry Andric } 474206c3fb27SDimitry Andric} 474306c3fb27SDimitry Andric 474406c3fb27SDimitry Andricmulticlass VPatNullaryV<string intrinsic, string instruction> { 4745e8d8bef9SDimitry Andric foreach vti = AllIntegerVectors in { 474606c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 474781ad6265SDimitry Andric def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic) 474881ad6265SDimitry Andric (vti.Vector vti.RegClass:$merge), 474981ad6265SDimitry Andric VLOpFrag)), 475006c3fb27SDimitry Andric (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX) 475106c3fb27SDimitry Andric vti.RegClass:$merge, GPR:$vl, vti.Log2SEW, TU_MU)>; 4752e8d8bef9SDimitry Andric def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask") 4753e8d8bef9SDimitry Andric (vti.Vector vti.RegClass:$merge), 475481ad6265SDimitry Andric (vti.Mask V0), VLOpFrag, (XLenVT timm:$policy))), 4755e8d8bef9SDimitry Andric (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK") 4756e8d8bef9SDimitry Andric vti.RegClass:$merge, (vti.Mask V0), 475781ad6265SDimitry Andric GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>; 4758e8d8bef9SDimitry Andric } 4759e8d8bef9SDimitry Andric } 476006c3fb27SDimitry Andric} 4761e8d8bef9SDimitry Andric 4762e8d8bef9SDimitry Andricmulticlass VPatNullaryM<string intrinsic, string inst> { 4763e8d8bef9SDimitry Andric foreach mti = AllMasks in 4764e8d8bef9SDimitry Andric def : Pat<(mti.Mask (!cast<Intrinsic>(intrinsic) 476581ad6265SDimitry Andric VLOpFrag)), 4766e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_M_"#mti.BX) 4767fe6060f1SDimitry Andric GPR:$vl, mti.Log2SEW)>; 4768e8d8bef9SDimitry Andric} 4769e8d8bef9SDimitry Andric 477081ad6265SDimitry Andricmulticlass VPatBinaryM<string intrinsic, 4771e8d8bef9SDimitry Andric string inst, 4772e8d8bef9SDimitry Andric ValueType result_type, 4773e8d8bef9SDimitry Andric ValueType op1_type, 4774e8d8bef9SDimitry Andric ValueType op2_type, 4775e8d8bef9SDimitry Andric ValueType mask_type, 4776e8d8bef9SDimitry Andric int sew, 4777e8d8bef9SDimitry Andric VReg result_reg_class, 4778e8d8bef9SDimitry Andric VReg op1_reg_class, 477906c3fb27SDimitry Andric DAGOperand op2_kind> { 478081ad6265SDimitry Andric def : VPatBinaryM<intrinsic, inst, result_type, op1_type, op2_type, 4781e8d8bef9SDimitry Andric sew, op1_reg_class, op2_kind>; 4782e8d8bef9SDimitry Andric def : VPatBinaryMask<intrinsic, inst, result_type, op1_type, op2_type, 4783e8d8bef9SDimitry Andric mask_type, sew, result_reg_class, op1_reg_class, 4784e8d8bef9SDimitry Andric op2_kind>; 4785e8d8bef9SDimitry Andric} 4786e8d8bef9SDimitry Andric 478706c3fb27SDimitry Andricmulticlass VPatBinary<string intrinsic, 4788349cc55cSDimitry Andric string inst, 4789349cc55cSDimitry Andric ValueType result_type, 4790349cc55cSDimitry Andric ValueType op1_type, 4791349cc55cSDimitry Andric ValueType op2_type, 4792349cc55cSDimitry Andric ValueType mask_type, 4793349cc55cSDimitry Andric int sew, 4794349cc55cSDimitry Andric VReg result_reg_class, 4795349cc55cSDimitry Andric VReg op1_reg_class, 479606c3fb27SDimitry Andric DAGOperand op2_kind> { 479781ad6265SDimitry Andric def : VPatBinaryNoMaskTU<intrinsic, inst, result_type, op1_type, op2_type, 479881ad6265SDimitry Andric sew, result_reg_class, op1_reg_class, op2_kind>; 4799349cc55cSDimitry Andric def : VPatBinaryMaskTA<intrinsic, inst, result_type, op1_type, op2_type, 4800349cc55cSDimitry Andric mask_type, sew, result_reg_class, op1_reg_class, 4801349cc55cSDimitry Andric op2_kind>; 4802349cc55cSDimitry Andric} 4803349cc55cSDimitry Andric 480406c3fb27SDimitry Andricmulticlass VPatBinaryRoundingMode<string intrinsic, 480506c3fb27SDimitry Andric string inst, 480606c3fb27SDimitry Andric ValueType result_type, 480706c3fb27SDimitry Andric ValueType op1_type, 480806c3fb27SDimitry Andric ValueType op2_type, 480906c3fb27SDimitry Andric ValueType mask_type, 481006c3fb27SDimitry Andric int sew, 481106c3fb27SDimitry Andric VReg result_reg_class, 481206c3fb27SDimitry Andric VReg op1_reg_class, 481306c3fb27SDimitry Andric DAGOperand op2_kind> { 481406c3fb27SDimitry Andric def : VPatBinaryNoMaskRoundingMode<intrinsic, inst, result_type, op1_type, op2_type, 481506c3fb27SDimitry Andric sew, op1_reg_class, op2_kind>; 481606c3fb27SDimitry Andric def : VPatBinaryNoMaskTURoundingMode<intrinsic, inst, result_type, op1_type, op2_type, 481706c3fb27SDimitry Andric sew, result_reg_class, op1_reg_class, op2_kind>; 481806c3fb27SDimitry Andric def : VPatBinaryMaskTARoundingMode<intrinsic, inst, result_type, op1_type, op2_type, 481906c3fb27SDimitry Andric mask_type, sew, result_reg_class, op1_reg_class, 482006c3fb27SDimitry Andric op2_kind>; 482106c3fb27SDimitry Andric} 482206c3fb27SDimitry Andric 4823fe6060f1SDimitry Andricmulticlass VPatBinarySwapped<string intrinsic, 4824fe6060f1SDimitry Andric string inst, 4825fe6060f1SDimitry Andric ValueType result_type, 4826fe6060f1SDimitry Andric ValueType op1_type, 4827fe6060f1SDimitry Andric ValueType op2_type, 4828fe6060f1SDimitry Andric ValueType mask_type, 4829fe6060f1SDimitry Andric int sew, 4830fe6060f1SDimitry Andric VReg result_reg_class, 4831fe6060f1SDimitry Andric VReg op1_reg_class, 483206c3fb27SDimitry Andric DAGOperand op2_kind> { 4833fe6060f1SDimitry Andric def : VPatBinaryNoMaskSwapped<intrinsic, inst, result_type, op1_type, op2_type, 4834fe6060f1SDimitry Andric sew, op1_reg_class, op2_kind>; 4835fe6060f1SDimitry Andric def : VPatBinaryMaskSwapped<intrinsic, inst, result_type, op1_type, op2_type, 4836fe6060f1SDimitry Andric mask_type, sew, result_reg_class, op1_reg_class, 4837fe6060f1SDimitry Andric op2_kind>; 4838fe6060f1SDimitry Andric} 4839fe6060f1SDimitry Andric 484081ad6265SDimitry Andricmulticlass VPatBinaryCarryInTAIL<string intrinsic, 484181ad6265SDimitry Andric string inst, 484281ad6265SDimitry Andric string kind, 484381ad6265SDimitry Andric ValueType result_type, 484481ad6265SDimitry Andric ValueType op1_type, 484581ad6265SDimitry Andric ValueType op2_type, 484681ad6265SDimitry Andric ValueType mask_type, 484781ad6265SDimitry Andric int sew, 484881ad6265SDimitry Andric LMULInfo vlmul, 484981ad6265SDimitry Andric VReg result_reg_class, 485081ad6265SDimitry Andric VReg op1_reg_class, 485106c3fb27SDimitry Andric DAGOperand op2_kind> { 485281ad6265SDimitry Andric def : Pat<(result_type (!cast<Intrinsic>(intrinsic) 485381ad6265SDimitry Andric (result_type result_reg_class:$merge), 485481ad6265SDimitry Andric (op1_type op1_reg_class:$rs1), 485581ad6265SDimitry Andric (op2_type op2_kind:$rs2), 485681ad6265SDimitry Andric (mask_type V0), 485781ad6265SDimitry Andric VLOpFrag)), 485806c3fb27SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) 485981ad6265SDimitry Andric (result_type result_reg_class:$merge), 486081ad6265SDimitry Andric (op1_type op1_reg_class:$rs1), 486181ad6265SDimitry Andric (op2_type op2_kind:$rs2), 486281ad6265SDimitry Andric (mask_type V0), GPR:$vl, sew)>; 486381ad6265SDimitry Andric} 486481ad6265SDimitry Andric 4865e8d8bef9SDimitry Andricmulticlass VPatBinaryCarryIn<string intrinsic, 4866e8d8bef9SDimitry Andric string inst, 4867e8d8bef9SDimitry Andric string kind, 4868e8d8bef9SDimitry Andric ValueType result_type, 4869e8d8bef9SDimitry Andric ValueType op1_type, 4870e8d8bef9SDimitry Andric ValueType op2_type, 4871e8d8bef9SDimitry Andric ValueType mask_type, 4872e8d8bef9SDimitry Andric int sew, 4873e8d8bef9SDimitry Andric LMULInfo vlmul, 4874e8d8bef9SDimitry Andric VReg op1_reg_class, 487506c3fb27SDimitry Andric DAGOperand op2_kind> { 4876e8d8bef9SDimitry Andric def : Pat<(result_type (!cast<Intrinsic>(intrinsic) 4877e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4878e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4879e8d8bef9SDimitry Andric (mask_type V0), 4880fe6060f1SDimitry Andric VLOpFrag)), 4881e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) 4882e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4883e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4884d409305fSDimitry Andric (mask_type V0), GPR:$vl, sew)>; 4885e8d8bef9SDimitry Andric} 4886e8d8bef9SDimitry Andric 4887e8d8bef9SDimitry Andricmulticlass VPatBinaryMaskOut<string intrinsic, 4888e8d8bef9SDimitry Andric string inst, 4889e8d8bef9SDimitry Andric string kind, 4890e8d8bef9SDimitry Andric ValueType result_type, 4891e8d8bef9SDimitry Andric ValueType op1_type, 4892e8d8bef9SDimitry Andric ValueType op2_type, 4893e8d8bef9SDimitry Andric int sew, 4894e8d8bef9SDimitry Andric LMULInfo vlmul, 4895e8d8bef9SDimitry Andric VReg op1_reg_class, 489606c3fb27SDimitry Andric DAGOperand op2_kind> { 4897e8d8bef9SDimitry Andric def : Pat<(result_type (!cast<Intrinsic>(intrinsic) 4898e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4899e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4900fe6060f1SDimitry Andric VLOpFrag)), 4901e8d8bef9SDimitry Andric (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) 4902e8d8bef9SDimitry Andric (op1_type op1_reg_class:$rs1), 4903e8d8bef9SDimitry Andric (op2_type op2_kind:$rs2), 4904d409305fSDimitry Andric GPR:$vl, sew)>; 4905e8d8bef9SDimitry Andric} 4906e8d8bef9SDimitry Andric 4907349cc55cSDimitry Andricmulticlass VPatConversionTA<string intrinsic, 4908349cc55cSDimitry Andric string inst, 4909349cc55cSDimitry Andric string kind, 4910349cc55cSDimitry Andric ValueType result_type, 4911349cc55cSDimitry Andric ValueType op1_type, 4912349cc55cSDimitry Andric ValueType mask_type, 4913349cc55cSDimitry Andric int sew, 4914349cc55cSDimitry Andric LMULInfo vlmul, 4915349cc55cSDimitry Andric VReg result_reg_class, 491606c3fb27SDimitry Andric VReg op1_reg_class> { 4917349cc55cSDimitry Andric def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type, 491881ad6265SDimitry Andric sew, vlmul, result_reg_class, op1_reg_class>; 491906c3fb27SDimitry Andric def : VPatUnaryMask<intrinsic, inst, kind, result_type, op1_type, 492006c3fb27SDimitry Andric mask_type, sew, vlmul, result_reg_class, op1_reg_class>; 492106c3fb27SDimitry Andric} 492206c3fb27SDimitry Andric 492306c3fb27SDimitry Andricmulticlass VPatConversionTARoundingMode<string intrinsic, 492406c3fb27SDimitry Andric string inst, 492506c3fb27SDimitry Andric string kind, 492606c3fb27SDimitry Andric ValueType result_type, 492706c3fb27SDimitry Andric ValueType op1_type, 492806c3fb27SDimitry Andric ValueType mask_type, 492906c3fb27SDimitry Andric int sew, 493006c3fb27SDimitry Andric LMULInfo vlmul, 493106c3fb27SDimitry Andric VReg result_reg_class, 493206c3fb27SDimitry Andric VReg op1_reg_class> { 493306c3fb27SDimitry Andric def : VPatUnaryNoMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type, 493406c3fb27SDimitry Andric sew, vlmul, result_reg_class, op1_reg_class>; 493506c3fb27SDimitry Andric def : VPatUnaryMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type, 4936349cc55cSDimitry Andric mask_type, sew, vlmul, result_reg_class, op1_reg_class>; 4937349cc55cSDimitry Andric} 4938349cc55cSDimitry Andric 4939e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VV<string intrinsic, string instruction, 494006c3fb27SDimitry Andric list<VTypeInfo> vtilist, bit isSEWAware = 0> { 4941e8d8bef9SDimitry Andric foreach vti = vtilist in 494206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 494306c3fb27SDimitry Andric defm : VPatBinary<intrinsic, 494406c3fb27SDimitry Andric !if(isSEWAware, 494506c3fb27SDimitry Andric instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW, 494606c3fb27SDimitry Andric instruction # "_VV_" # vti.LMul.MX), 494706c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Vector,vti.Mask, 494806c3fb27SDimitry Andric vti.Log2SEW, vti.RegClass, 494906c3fb27SDimitry Andric vti.RegClass, vti.RegClass>; 495006c3fb27SDimitry Andric} 495106c3fb27SDimitry Andric 495206c3fb27SDimitry Andricmulticlass VPatBinaryV_VV_RM<string intrinsic, string instruction, 495306c3fb27SDimitry Andric list<VTypeInfo> vtilist, bit isSEWAware = 0> { 495406c3fb27SDimitry Andric foreach vti = vtilist in 495506c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 495606c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, 495706c3fb27SDimitry Andric !if(isSEWAware, 495806c3fb27SDimitry Andric instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW, 495906c3fb27SDimitry Andric instruction # "_VV_" # vti.LMul.MX), 4960e8d8bef9SDimitry Andric vti.Vector, vti.Vector, vti.Vector,vti.Mask, 4961fe6060f1SDimitry Andric vti.Log2SEW, vti.RegClass, 4962e8d8bef9SDimitry Andric vti.RegClass, vti.RegClass>; 4963e8d8bef9SDimitry Andric} 4964e8d8bef9SDimitry Andric 4965e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VV_INT<string intrinsic, string instruction, 4966e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 4967e8d8bef9SDimitry Andric foreach vti = vtilist in { 4968e8d8bef9SDimitry Andric defvar ivti = GetIntVTypeInfo<vti>.Vti; 496906c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 497006c3fb27SDimitry Andric defm : VPatBinary<intrinsic, 497106c3fb27SDimitry Andric instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW, 4972e8d8bef9SDimitry Andric vti.Vector, vti.Vector, ivti.Vector, vti.Mask, 4973fe6060f1SDimitry Andric vti.Log2SEW, vti.RegClass, 4974e8d8bef9SDimitry Andric vti.RegClass, vti.RegClass>; 4975e8d8bef9SDimitry Andric } 4976e8d8bef9SDimitry Andric} 4977e8d8bef9SDimitry Andric 4978e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction, 4979e8d8bef9SDimitry Andric int eew, list<VTypeInfo> vtilist> { 4980e8d8bef9SDimitry Andric foreach vti = vtilist in { 4981e8d8bef9SDimitry Andric // emul = lmul * eew / sew 4982e8d8bef9SDimitry Andric defvar vlmul = vti.LMul; 4983fe6060f1SDimitry Andric defvar octuple_lmul = vlmul.octuple; 4984fe6060f1SDimitry Andric defvar octuple_emul = !srl(!mul(octuple_lmul, eew), vti.Log2SEW); 4985e8d8bef9SDimitry Andric if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 4986e8d8bef9SDimitry Andric defvar emul_str = octuple_to_str<octuple_emul>.ret; 4987e8d8bef9SDimitry Andric defvar ivti = !cast<VTypeInfo>("VI" # eew # emul_str); 498806c3fb27SDimitry Andric defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; 498906c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 499006c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 499106c3fb27SDimitry Andric defm : VPatBinary<intrinsic, inst, 4992e8d8bef9SDimitry Andric vti.Vector, vti.Vector, ivti.Vector, vti.Mask, 4993fe6060f1SDimitry Andric vti.Log2SEW, vti.RegClass, 4994e8d8bef9SDimitry Andric vti.RegClass, ivti.RegClass>; 4995e8d8bef9SDimitry Andric } 4996e8d8bef9SDimitry Andric } 4997e8d8bef9SDimitry Andric} 4998e8d8bef9SDimitry Andric 4999e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VX<string intrinsic, string instruction, 500006c3fb27SDimitry Andric list<VTypeInfo> vtilist, bit isSEWAware = 0> { 5001e8d8bef9SDimitry Andric foreach vti = vtilist in { 5002e8d8bef9SDimitry Andric defvar kind = "V"#vti.ScalarSuffix; 500306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 500406c3fb27SDimitry Andric defm : VPatBinary<intrinsic, 500506c3fb27SDimitry Andric !if(isSEWAware, 500606c3fb27SDimitry Andric instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW, 500706c3fb27SDimitry Andric instruction#"_"#kind#"_"#vti.LMul.MX), 500806c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Scalar, vti.Mask, 500906c3fb27SDimitry Andric vti.Log2SEW, vti.RegClass, 501006c3fb27SDimitry Andric vti.RegClass, vti.ScalarRegClass>; 501106c3fb27SDimitry Andric } 501206c3fb27SDimitry Andric} 501306c3fb27SDimitry Andric 501406c3fb27SDimitry Andricmulticlass VPatBinaryV_VX_RM<string intrinsic, string instruction, 501506c3fb27SDimitry Andric list<VTypeInfo> vtilist, bit isSEWAware = 0> { 501606c3fb27SDimitry Andric foreach vti = vtilist in { 501706c3fb27SDimitry Andric defvar kind = "V"#vti.ScalarSuffix; 501806c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 501906c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, 502006c3fb27SDimitry Andric !if(isSEWAware, 502106c3fb27SDimitry Andric instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW, 502206c3fb27SDimitry Andric instruction#"_"#kind#"_"#vti.LMul.MX), 5023e8d8bef9SDimitry Andric vti.Vector, vti.Vector, vti.Scalar, vti.Mask, 5024fe6060f1SDimitry Andric vti.Log2SEW, vti.RegClass, 5025e8d8bef9SDimitry Andric vti.RegClass, vti.ScalarRegClass>; 5026e8d8bef9SDimitry Andric } 5027e8d8bef9SDimitry Andric} 5028e8d8bef9SDimitry Andric 5029e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VX_INT<string intrinsic, string instruction, 5030e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 5031e8d8bef9SDimitry Andric foreach vti = vtilist in 503206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 503306c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction # "_VX_" # vti.LMul.MX, 5034e8d8bef9SDimitry Andric vti.Vector, vti.Vector, XLenVT, vti.Mask, 5035fe6060f1SDimitry Andric vti.Log2SEW, vti.RegClass, 5036e8d8bef9SDimitry Andric vti.RegClass, GPR>; 5037e8d8bef9SDimitry Andric} 5038e8d8bef9SDimitry Andric 5039e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VI<string intrinsic, string instruction, 5040e8d8bef9SDimitry Andric list<VTypeInfo> vtilist, Operand imm_type> { 5041e8d8bef9SDimitry Andric foreach vti = vtilist in 504206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 504306c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX, 504406c3fb27SDimitry Andric vti.Vector, vti.Vector, XLenVT, vti.Mask, 504506c3fb27SDimitry Andric vti.Log2SEW, vti.RegClass, 504606c3fb27SDimitry Andric vti.RegClass, imm_type>; 504706c3fb27SDimitry Andric} 504806c3fb27SDimitry Andric 504906c3fb27SDimitry Andricmulticlass VPatBinaryV_VI_RM<string intrinsic, string instruction, 505006c3fb27SDimitry Andric list<VTypeInfo> vtilist, 505106c3fb27SDimitry Andric Operand imm_type> { 505206c3fb27SDimitry Andric foreach vti = vtilist in 505306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 505406c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, 505506c3fb27SDimitry Andric instruction # "_VI_" # vti.LMul.MX, 5056e8d8bef9SDimitry Andric vti.Vector, vti.Vector, XLenVT, vti.Mask, 5057fe6060f1SDimitry Andric vti.Log2SEW, vti.RegClass, 5058e8d8bef9SDimitry Andric vti.RegClass, imm_type>; 5059e8d8bef9SDimitry Andric} 5060e8d8bef9SDimitry Andric 5061e8d8bef9SDimitry Andricmulticlass VPatBinaryM_MM<string intrinsic, string instruction> { 5062e8d8bef9SDimitry Andric foreach mti = AllMasks in 506306c3fb27SDimitry Andric let Predicates = [HasVInstructions] in 506481ad6265SDimitry Andric def : VPatBinaryM<intrinsic, instruction # "_MM_" # mti.LMul.MX, 5065e8d8bef9SDimitry Andric mti.Mask, mti.Mask, mti.Mask, 5066fe6060f1SDimitry Andric mti.Log2SEW, VR, VR>; 5067e8d8bef9SDimitry Andric} 5068e8d8bef9SDimitry Andric 5069e8d8bef9SDimitry Andricmulticlass VPatBinaryW_VV<string intrinsic, string instruction, 5070e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5071e8d8bef9SDimitry Andric foreach VtiToWti = vtilist in { 5072e8d8bef9SDimitry Andric defvar Vti = VtiToWti.Vti; 5073e8d8bef9SDimitry Andric defvar Wti = VtiToWti.Wti; 507406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 507506c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 507606c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction # "_VV_" # Vti.LMul.MX, 507706c3fb27SDimitry Andric Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask, 507806c3fb27SDimitry Andric Vti.Log2SEW, Wti.RegClass, 507906c3fb27SDimitry Andric Vti.RegClass, Vti.RegClass>; 508006c3fb27SDimitry Andric } 508106c3fb27SDimitry Andric} 508206c3fb27SDimitry Andric 508306c3fb27SDimitry Andricmulticlass VPatBinaryW_VV_RM<string intrinsic, string instruction, 508406c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 508506c3fb27SDimitry Andric foreach VtiToWti = vtilist in { 508606c3fb27SDimitry Andric defvar Vti = VtiToWti.Vti; 508706c3fb27SDimitry Andric defvar Wti = VtiToWti.Wti; 508806c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 508906c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 509006c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, instruction # "_VV_" # Vti.LMul.MX, 5091e8d8bef9SDimitry Andric Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask, 5092fe6060f1SDimitry Andric Vti.Log2SEW, Wti.RegClass, 5093e8d8bef9SDimitry Andric Vti.RegClass, Vti.RegClass>; 5094e8d8bef9SDimitry Andric } 5095e8d8bef9SDimitry Andric} 5096e8d8bef9SDimitry Andric 5097e8d8bef9SDimitry Andricmulticlass VPatBinaryW_VX<string intrinsic, string instruction, 5098e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5099e8d8bef9SDimitry Andric foreach VtiToWti = vtilist in { 5100e8d8bef9SDimitry Andric defvar Vti = VtiToWti.Vti; 5101e8d8bef9SDimitry Andric defvar Wti = VtiToWti.Wti; 5102e8d8bef9SDimitry Andric defvar kind = "V"#Vti.ScalarSuffix; 510306c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 510406c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 510506c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, 510606c3fb27SDimitry Andric Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask, 510706c3fb27SDimitry Andric Vti.Log2SEW, Wti.RegClass, 510806c3fb27SDimitry Andric Vti.RegClass, Vti.ScalarRegClass>; 510906c3fb27SDimitry Andric } 511006c3fb27SDimitry Andric} 511106c3fb27SDimitry Andric 511206c3fb27SDimitry Andricmulticlass VPatBinaryW_VX_RM<string intrinsic, string instruction, 511306c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 511406c3fb27SDimitry Andric foreach VtiToWti = vtilist in { 511506c3fb27SDimitry Andric defvar Vti = VtiToWti.Vti; 511606c3fb27SDimitry Andric defvar Wti = VtiToWti.Wti; 511706c3fb27SDimitry Andric defvar kind = "V"#Vti.ScalarSuffix; 511806c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 511906c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 512006c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, 5121e8d8bef9SDimitry Andric Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask, 5122fe6060f1SDimitry Andric Vti.Log2SEW, Wti.RegClass, 5123e8d8bef9SDimitry Andric Vti.RegClass, Vti.ScalarRegClass>; 5124e8d8bef9SDimitry Andric } 5125e8d8bef9SDimitry Andric} 5126e8d8bef9SDimitry Andric 5127e8d8bef9SDimitry Andricmulticlass VPatBinaryW_WV<string intrinsic, string instruction, 5128e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5129e8d8bef9SDimitry Andric foreach VtiToWti = vtilist in { 5130e8d8bef9SDimitry Andric defvar Vti = VtiToWti.Vti; 5131e8d8bef9SDimitry Andric defvar Wti = VtiToWti.Wti; 513206c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 513306c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in { 5134fe6060f1SDimitry Andric def : VPatTiedBinaryNoMask<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 5135fe6060f1SDimitry Andric Wti.Vector, Vti.Vector, 5136fe6060f1SDimitry Andric Vti.Log2SEW, Wti.RegClass, Vti.RegClass>; 513781ad6265SDimitry Andric def : VPatBinaryNoMaskTU<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 513881ad6265SDimitry Andric Wti.Vector, Wti.Vector, Vti.Vector, Vti.Log2SEW, 513981ad6265SDimitry Andric Wti.RegClass, Wti.RegClass, Vti.RegClass>; 514081ad6265SDimitry Andric let AddedComplexity = 1 in { 514181ad6265SDimitry Andric def : VPatTiedBinaryNoMaskTU<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 514281ad6265SDimitry Andric Wti.Vector, Vti.Vector, 514381ad6265SDimitry Andric Vti.Log2SEW, Wti.RegClass, Vti.RegClass>; 5144fe6060f1SDimitry Andric def : VPatTiedBinaryMask<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 5145fe6060f1SDimitry Andric Wti.Vector, Vti.Vector, Vti.Mask, 5146fe6060f1SDimitry Andric Vti.Log2SEW, Wti.RegClass, Vti.RegClass>; 514781ad6265SDimitry Andric } 5148349cc55cSDimitry Andric def : VPatBinaryMaskTA<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 5149e8d8bef9SDimitry Andric Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, 5150fe6060f1SDimitry Andric Vti.Log2SEW, Wti.RegClass, 5151e8d8bef9SDimitry Andric Wti.RegClass, Vti.RegClass>; 5152e8d8bef9SDimitry Andric } 5153e8d8bef9SDimitry Andric } 515406c3fb27SDimitry Andric} 515506c3fb27SDimitry Andric 515606c3fb27SDimitry Andricmulticlass VPatBinaryW_WV_RM<string intrinsic, string instruction, 515706c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 515806c3fb27SDimitry Andric foreach VtiToWti = vtilist in { 515906c3fb27SDimitry Andric defvar Vti = VtiToWti.Vti; 516006c3fb27SDimitry Andric defvar Wti = VtiToWti.Wti; 516106c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 516206c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in { 516306c3fb27SDimitry Andric def : VPatTiedBinaryNoMaskRoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 516406c3fb27SDimitry Andric Wti.Vector, Vti.Vector, 516506c3fb27SDimitry Andric Vti.Log2SEW, Wti.RegClass, Vti.RegClass>; 516606c3fb27SDimitry Andric def : VPatBinaryNoMaskTURoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 516706c3fb27SDimitry Andric Wti.Vector, Wti.Vector, Vti.Vector, Vti.Log2SEW, 516806c3fb27SDimitry Andric Wti.RegClass, Wti.RegClass, Vti.RegClass>; 516906c3fb27SDimitry Andric let AddedComplexity = 1 in { 517006c3fb27SDimitry Andric def : VPatTiedBinaryNoMaskTURoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 517106c3fb27SDimitry Andric Wti.Vector, Vti.Vector, 517206c3fb27SDimitry Andric Vti.Log2SEW, Wti.RegClass, Vti.RegClass>; 517306c3fb27SDimitry Andric def : VPatTiedBinaryMaskRoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 517406c3fb27SDimitry Andric Wti.Vector, Vti.Vector, Vti.Mask, 517506c3fb27SDimitry Andric Vti.Log2SEW, Wti.RegClass, Vti.RegClass>; 517606c3fb27SDimitry Andric } 517706c3fb27SDimitry Andric def : VPatBinaryMaskTARoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 517806c3fb27SDimitry Andric Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, 517906c3fb27SDimitry Andric Vti.Log2SEW, Wti.RegClass, 518006c3fb27SDimitry Andric Wti.RegClass, Vti.RegClass>; 518106c3fb27SDimitry Andric } 518206c3fb27SDimitry Andric } 518306c3fb27SDimitry Andric} 5184e8d8bef9SDimitry Andric 5185e8d8bef9SDimitry Andricmulticlass VPatBinaryW_WX<string intrinsic, string instruction, 5186e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5187e8d8bef9SDimitry Andric foreach VtiToWti = vtilist in { 5188e8d8bef9SDimitry Andric defvar Vti = VtiToWti.Vti; 5189e8d8bef9SDimitry Andric defvar Wti = VtiToWti.Wti; 5190e8d8bef9SDimitry Andric defvar kind = "W"#Vti.ScalarSuffix; 519106c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 519206c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 519306c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, 519406c3fb27SDimitry Andric Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, 519506c3fb27SDimitry Andric Vti.Log2SEW, Wti.RegClass, 519606c3fb27SDimitry Andric Wti.RegClass, Vti.ScalarRegClass>; 519706c3fb27SDimitry Andric } 519806c3fb27SDimitry Andric} 519906c3fb27SDimitry Andric 520006c3fb27SDimitry Andricmulticlass VPatBinaryW_WX_RM<string intrinsic, string instruction, 520106c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 520206c3fb27SDimitry Andric foreach VtiToWti = vtilist in { 520306c3fb27SDimitry Andric defvar Vti = VtiToWti.Vti; 520406c3fb27SDimitry Andric defvar Wti = VtiToWti.Wti; 520506c3fb27SDimitry Andric defvar kind = "W"#Vti.ScalarSuffix; 520606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 520706c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 520806c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, 5209e8d8bef9SDimitry Andric Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, 5210fe6060f1SDimitry Andric Vti.Log2SEW, Wti.RegClass, 5211e8d8bef9SDimitry Andric Wti.RegClass, Vti.ScalarRegClass>; 5212e8d8bef9SDimitry Andric } 5213e8d8bef9SDimitry Andric} 5214e8d8bef9SDimitry Andric 5215e8d8bef9SDimitry Andricmulticlass VPatBinaryV_WV<string intrinsic, string instruction, 5216e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5217e8d8bef9SDimitry Andric foreach VtiToWti = vtilist in { 5218e8d8bef9SDimitry Andric defvar Vti = VtiToWti.Vti; 5219e8d8bef9SDimitry Andric defvar Wti = VtiToWti.Wti; 522006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 522106c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 522206c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX, 522306c3fb27SDimitry Andric Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, 522406c3fb27SDimitry Andric Vti.Log2SEW, Vti.RegClass, 522506c3fb27SDimitry Andric Wti.RegClass, Vti.RegClass>; 522606c3fb27SDimitry Andric } 522706c3fb27SDimitry Andric} 522806c3fb27SDimitry Andric 522906c3fb27SDimitry Andricmulticlass VPatBinaryV_WV_RM<string intrinsic, string instruction, 523006c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 523106c3fb27SDimitry Andric foreach VtiToWti = vtilist in { 523206c3fb27SDimitry Andric defvar Vti = VtiToWti.Vti; 523306c3fb27SDimitry Andric defvar Wti = VtiToWti.Wti; 523406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 523506c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 523606c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, 523706c3fb27SDimitry Andric instruction # "_WV_" # Vti.LMul.MX, 5238e8d8bef9SDimitry Andric Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, 5239fe6060f1SDimitry Andric Vti.Log2SEW, Vti.RegClass, 5240e8d8bef9SDimitry Andric Wti.RegClass, Vti.RegClass>; 5241e8d8bef9SDimitry Andric } 5242e8d8bef9SDimitry Andric} 5243e8d8bef9SDimitry Andric 5244e8d8bef9SDimitry Andricmulticlass VPatBinaryV_WX<string intrinsic, string instruction, 5245e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5246e8d8bef9SDimitry Andric foreach VtiToWti = vtilist in { 5247e8d8bef9SDimitry Andric defvar Vti = VtiToWti.Vti; 5248e8d8bef9SDimitry Andric defvar Wti = VtiToWti.Wti; 5249e8d8bef9SDimitry Andric defvar kind = "W"#Vti.ScalarSuffix; 525006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 525106c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 525206c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, 5253e8d8bef9SDimitry Andric Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, 5254fe6060f1SDimitry Andric Vti.Log2SEW, Vti.RegClass, 5255e8d8bef9SDimitry Andric Wti.RegClass, Vti.ScalarRegClass>; 5256e8d8bef9SDimitry Andric } 5257e8d8bef9SDimitry Andric} 5258e8d8bef9SDimitry Andric 525906c3fb27SDimitry Andricmulticlass VPatBinaryV_WX_RM<string intrinsic, string instruction, 526006c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 526106c3fb27SDimitry Andric foreach VtiToWti = vtilist in { 526206c3fb27SDimitry Andric defvar Vti = VtiToWti.Vti; 526306c3fb27SDimitry Andric defvar Wti = VtiToWti.Wti; 526406c3fb27SDimitry Andric defvar kind = "W"#Vti.ScalarSuffix; 526506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 526606c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 526706c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, 526806c3fb27SDimitry Andric instruction#"_"#kind#"_"#Vti.LMul.MX, 526906c3fb27SDimitry Andric Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, 527006c3fb27SDimitry Andric Vti.Log2SEW, Vti.RegClass, 527106c3fb27SDimitry Andric Wti.RegClass, Vti.ScalarRegClass>; 527206c3fb27SDimitry Andric } 527306c3fb27SDimitry Andric} 527406c3fb27SDimitry Andric 527506c3fb27SDimitry Andric 5276e8d8bef9SDimitry Andricmulticlass VPatBinaryV_WI<string intrinsic, string instruction, 5277e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5278e8d8bef9SDimitry Andric foreach VtiToWti = vtilist in { 5279e8d8bef9SDimitry Andric defvar Vti = VtiToWti.Vti; 5280e8d8bef9SDimitry Andric defvar Wti = VtiToWti.Wti; 528106c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 528206c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 528306c3fb27SDimitry Andric defm : VPatBinary<intrinsic, instruction # "_WI_" # Vti.LMul.MX, 528406c3fb27SDimitry Andric Vti.Vector, Wti.Vector, XLenVT, Vti.Mask, 528506c3fb27SDimitry Andric Vti.Log2SEW, Vti.RegClass, 528606c3fb27SDimitry Andric Wti.RegClass, uimm5>; 528706c3fb27SDimitry Andric } 528806c3fb27SDimitry Andric} 528906c3fb27SDimitry Andric 529006c3fb27SDimitry Andricmulticlass VPatBinaryV_WI_RM<string intrinsic, string instruction, 529106c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 529206c3fb27SDimitry Andric foreach VtiToWti = vtilist in { 529306c3fb27SDimitry Andric defvar Vti = VtiToWti.Vti; 529406c3fb27SDimitry Andric defvar Wti = VtiToWti.Wti; 529506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates, 529606c3fb27SDimitry Andric GetVTypePredicates<Wti>.Predicates) in 529706c3fb27SDimitry Andric defm : VPatBinaryRoundingMode<intrinsic, 529806c3fb27SDimitry Andric instruction # "_WI_" # Vti.LMul.MX, 5299e8d8bef9SDimitry Andric Vti.Vector, Wti.Vector, XLenVT, Vti.Mask, 5300fe6060f1SDimitry Andric Vti.Log2SEW, Vti.RegClass, 5301e8d8bef9SDimitry Andric Wti.RegClass, uimm5>; 5302e8d8bef9SDimitry Andric } 5303e8d8bef9SDimitry Andric} 5304e8d8bef9SDimitry Andric 5305e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VM<string intrinsic, string instruction, 5306e8d8bef9SDimitry Andric bit CarryOut = 0, 5307e8d8bef9SDimitry Andric list<VTypeInfo> vtilist = AllIntegerVectors> { 5308e8d8bef9SDimitry Andric foreach vti = vtilist in 530906c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5310e8d8bef9SDimitry Andric defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM", 5311e8d8bef9SDimitry Andric !if(CarryOut, vti.Mask, vti.Vector), 5312e8d8bef9SDimitry Andric vti.Vector, vti.Vector, vti.Mask, 5313fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5314e8d8bef9SDimitry Andric vti.RegClass, vti.RegClass>; 5315e8d8bef9SDimitry Andric} 5316e8d8bef9SDimitry Andric 5317e8d8bef9SDimitry Andricmulticlass VPatBinaryV_XM<string intrinsic, string instruction, 5318e8d8bef9SDimitry Andric bit CarryOut = 0, 5319e8d8bef9SDimitry Andric list<VTypeInfo> vtilist = AllIntegerVectors> { 5320e8d8bef9SDimitry Andric foreach vti = vtilist in 532106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5322e8d8bef9SDimitry Andric defm : VPatBinaryCarryIn<intrinsic, instruction, 5323e8d8bef9SDimitry Andric "V"#vti.ScalarSuffix#"M", 5324e8d8bef9SDimitry Andric !if(CarryOut, vti.Mask, vti.Vector), 5325e8d8bef9SDimitry Andric vti.Vector, vti.Scalar, vti.Mask, 5326fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5327e8d8bef9SDimitry Andric vti.RegClass, vti.ScalarRegClass>; 5328e8d8bef9SDimitry Andric} 5329e8d8bef9SDimitry Andric 5330e8d8bef9SDimitry Andricmulticlass VPatBinaryV_IM<string intrinsic, string instruction, 5331e8d8bef9SDimitry Andric bit CarryOut = 0> { 5332e8d8bef9SDimitry Andric foreach vti = AllIntegerVectors in 533306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5334e8d8bef9SDimitry Andric defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM", 5335e8d8bef9SDimitry Andric !if(CarryOut, vti.Mask, vti.Vector), 5336e8d8bef9SDimitry Andric vti.Vector, XLenVT, vti.Mask, 5337fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5338e8d8bef9SDimitry Andric vti.RegClass, simm5>; 5339e8d8bef9SDimitry Andric} 5340e8d8bef9SDimitry Andric 534106c3fb27SDimitry Andricmulticlass VPatBinaryV_VM_TAIL<string intrinsic, string instruction> { 534206c3fb27SDimitry Andric foreach vti = AllIntegerVectors in 534306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 534481ad6265SDimitry Andric defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VVM", 534506c3fb27SDimitry Andric vti.Vector, 534681ad6265SDimitry Andric vti.Vector, vti.Vector, vti.Mask, 534781ad6265SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 534881ad6265SDimitry Andric vti.RegClass, vti.RegClass>; 534981ad6265SDimitry Andric} 535081ad6265SDimitry Andric 535106c3fb27SDimitry Andricmulticlass VPatBinaryV_XM_TAIL<string intrinsic, string instruction> { 535206c3fb27SDimitry Andric foreach vti = AllIntegerVectors in 535306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 535481ad6265SDimitry Andric defm : VPatBinaryCarryInTAIL<intrinsic, instruction, 535581ad6265SDimitry Andric "V"#vti.ScalarSuffix#"M", 535606c3fb27SDimitry Andric vti.Vector, 535781ad6265SDimitry Andric vti.Vector, vti.Scalar, vti.Mask, 535881ad6265SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 535981ad6265SDimitry Andric vti.RegClass, vti.ScalarRegClass>; 536081ad6265SDimitry Andric} 536181ad6265SDimitry Andric 536206c3fb27SDimitry Andricmulticlass VPatBinaryV_IM_TAIL<string intrinsic, string instruction> { 536381ad6265SDimitry Andric foreach vti = AllIntegerVectors in 536406c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 536581ad6265SDimitry Andric defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VIM", 536606c3fb27SDimitry Andric vti.Vector, 536781ad6265SDimitry Andric vti.Vector, XLenVT, vti.Mask, 536881ad6265SDimitry Andric vti.Log2SEW, vti.LMul, 536981ad6265SDimitry Andric vti.RegClass, vti.RegClass, simm5>; 537081ad6265SDimitry Andric} 537181ad6265SDimitry Andric 5372e8d8bef9SDimitry Andricmulticlass VPatBinaryV_V<string intrinsic, string instruction> { 5373e8d8bef9SDimitry Andric foreach vti = AllIntegerVectors in 537406c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5375e8d8bef9SDimitry Andric defm : VPatBinaryMaskOut<intrinsic, instruction, "VV", 5376e8d8bef9SDimitry Andric vti.Mask, vti.Vector, vti.Vector, 5377fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5378e8d8bef9SDimitry Andric vti.RegClass, vti.RegClass>; 5379e8d8bef9SDimitry Andric} 5380e8d8bef9SDimitry Andric 5381e8d8bef9SDimitry Andricmulticlass VPatBinaryV_X<string intrinsic, string instruction> { 5382e8d8bef9SDimitry Andric foreach vti = AllIntegerVectors in 538306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5384e8d8bef9SDimitry Andric defm : VPatBinaryMaskOut<intrinsic, instruction, "VX", 5385e8d8bef9SDimitry Andric vti.Mask, vti.Vector, XLenVT, 5386fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5387e8d8bef9SDimitry Andric vti.RegClass, GPR>; 5388e8d8bef9SDimitry Andric} 5389e8d8bef9SDimitry Andric 5390e8d8bef9SDimitry Andricmulticlass VPatBinaryV_I<string intrinsic, string instruction> { 5391e8d8bef9SDimitry Andric foreach vti = AllIntegerVectors in 539206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5393e8d8bef9SDimitry Andric defm : VPatBinaryMaskOut<intrinsic, instruction, "VI", 5394e8d8bef9SDimitry Andric vti.Mask, vti.Vector, XLenVT, 5395fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5396e8d8bef9SDimitry Andric vti.RegClass, simm5>; 5397e8d8bef9SDimitry Andric} 5398e8d8bef9SDimitry Andric 5399e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VV<string intrinsic, string instruction, 5400e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 5401e8d8bef9SDimitry Andric foreach vti = vtilist in 540206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 540381ad6265SDimitry Andric defm : VPatBinaryM<intrinsic, instruction # "_VV_" # vti.LMul.MX, 5404e8d8bef9SDimitry Andric vti.Mask, vti.Vector, vti.Vector, vti.Mask, 5405fe6060f1SDimitry Andric vti.Log2SEW, VR, 5406fe6060f1SDimitry Andric vti.RegClass, vti.RegClass>; 5407fe6060f1SDimitry Andric} 5408fe6060f1SDimitry Andric 5409fe6060f1SDimitry Andricmulticlass VPatBinarySwappedM_VV<string intrinsic, string instruction, 5410fe6060f1SDimitry Andric list<VTypeInfo> vtilist> { 5411fe6060f1SDimitry Andric foreach vti = vtilist in 541206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5413fe6060f1SDimitry Andric defm : VPatBinarySwapped<intrinsic, instruction # "_VV_" # vti.LMul.MX, 5414fe6060f1SDimitry Andric vti.Mask, vti.Vector, vti.Vector, vti.Mask, 5415fe6060f1SDimitry Andric vti.Log2SEW, VR, 5416e8d8bef9SDimitry Andric vti.RegClass, vti.RegClass>; 5417e8d8bef9SDimitry Andric} 5418e8d8bef9SDimitry Andric 5419e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VX<string intrinsic, string instruction, 5420e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 5421e8d8bef9SDimitry Andric foreach vti = vtilist in { 5422e8d8bef9SDimitry Andric defvar kind = "V"#vti.ScalarSuffix; 542306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 542481ad6265SDimitry Andric defm : VPatBinaryM<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX, 5425e8d8bef9SDimitry Andric vti.Mask, vti.Vector, vti.Scalar, vti.Mask, 5426fe6060f1SDimitry Andric vti.Log2SEW, VR, 5427e8d8bef9SDimitry Andric vti.RegClass, vti.ScalarRegClass>; 5428e8d8bef9SDimitry Andric } 5429e8d8bef9SDimitry Andric} 5430e8d8bef9SDimitry Andric 5431e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VI<string intrinsic, string instruction, 5432e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 5433e8d8bef9SDimitry Andric foreach vti = vtilist in 543406c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 543581ad6265SDimitry Andric defm : VPatBinaryM<intrinsic, instruction # "_VI_" # vti.LMul.MX, 5436e8d8bef9SDimitry Andric vti.Mask, vti.Vector, XLenVT, vti.Mask, 5437fe6060f1SDimitry Andric vti.Log2SEW, VR, 5438e8d8bef9SDimitry Andric vti.RegClass, simm5>; 5439e8d8bef9SDimitry Andric} 5440e8d8bef9SDimitry Andric 5441e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction, 5442e8d8bef9SDimitry Andric list<VTypeInfo> vtilist, Operand ImmType = simm5> 5443fe6060f1SDimitry Andric : VPatBinaryV_VV<intrinsic, instruction, vtilist>, 5444fe6060f1SDimitry Andric VPatBinaryV_VX<intrinsic, instruction, vtilist>, 5445fe6060f1SDimitry Andric VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>; 5446e8d8bef9SDimitry Andric 544706c3fb27SDimitry Andricmulticlass VPatBinaryV_VV_VX_VI_RM<string intrinsic, string instruction, 544806c3fb27SDimitry Andric list<VTypeInfo> vtilist, Operand ImmType = simm5> 544906c3fb27SDimitry Andric : VPatBinaryV_VV_RM<intrinsic, instruction, vtilist>, 545006c3fb27SDimitry Andric VPatBinaryV_VX_RM<intrinsic, instruction, vtilist>, 545106c3fb27SDimitry Andric VPatBinaryV_VI_RM<intrinsic, instruction, vtilist, ImmType>; 545206c3fb27SDimitry Andric 5453e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VV_VX<string intrinsic, string instruction, 545406c3fb27SDimitry Andric list<VTypeInfo> vtilist, bit isSEWAware = 0> 545506c3fb27SDimitry Andric : VPatBinaryV_VV<intrinsic, instruction, vtilist, isSEWAware>, 545606c3fb27SDimitry Andric VPatBinaryV_VX<intrinsic, instruction, vtilist, isSEWAware>; 545706c3fb27SDimitry Andric 545806c3fb27SDimitry Andricmulticlass VPatBinaryV_VV_VX_RM<string intrinsic, string instruction, 545906c3fb27SDimitry Andric list<VTypeInfo> vtilist, bit isSEWAware = 0> 546006c3fb27SDimitry Andric : VPatBinaryV_VV_RM<intrinsic, instruction, vtilist, isSEWAware>, 546106c3fb27SDimitry Andric VPatBinaryV_VX_RM<intrinsic, instruction, vtilist, isSEWAware>; 5462e8d8bef9SDimitry Andric 5463e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VX_VI<string intrinsic, string instruction, 5464e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> 5465fe6060f1SDimitry Andric : VPatBinaryV_VX<intrinsic, instruction, vtilist>, 5466fe6060f1SDimitry Andric VPatBinaryV_VI<intrinsic, instruction, vtilist, simm5>; 5467e8d8bef9SDimitry Andric 5468e8d8bef9SDimitry Andricmulticlass VPatBinaryW_VV_VX<string intrinsic, string instruction, 5469e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> 5470fe6060f1SDimitry Andric : VPatBinaryW_VV<intrinsic, instruction, vtilist>, 5471fe6060f1SDimitry Andric VPatBinaryW_VX<intrinsic, instruction, vtilist>; 5472e8d8bef9SDimitry Andric 547306c3fb27SDimitry Andricmulticlass VPatBinaryW_VV_VX_RM<string intrinsic, string instruction, 547406c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> 547506c3fb27SDimitry Andric : VPatBinaryW_VV_RM<intrinsic, instruction, vtilist>, 547606c3fb27SDimitry Andric VPatBinaryW_VX_RM<intrinsic, instruction, vtilist>; 547706c3fb27SDimitry Andric 5478e8d8bef9SDimitry Andricmulticlass VPatBinaryW_WV_WX<string intrinsic, string instruction, 5479e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> 5480fe6060f1SDimitry Andric : VPatBinaryW_WV<intrinsic, instruction, vtilist>, 5481fe6060f1SDimitry Andric VPatBinaryW_WX<intrinsic, instruction, vtilist>; 5482e8d8bef9SDimitry Andric 548306c3fb27SDimitry Andricmulticlass VPatBinaryW_WV_WX_RM<string intrinsic, string instruction, 548406c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> 548506c3fb27SDimitry Andric : VPatBinaryW_WV_RM<intrinsic, instruction, vtilist>, 548606c3fb27SDimitry Andric VPatBinaryW_WX_RM<intrinsic, instruction, vtilist>; 548706c3fb27SDimitry Andric 5488e8d8bef9SDimitry Andricmulticlass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction, 5489e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> 5490fe6060f1SDimitry Andric : VPatBinaryV_WV<intrinsic, instruction, vtilist>, 5491fe6060f1SDimitry Andric VPatBinaryV_WX<intrinsic, instruction, vtilist>, 5492fe6060f1SDimitry Andric VPatBinaryV_WI<intrinsic, instruction, vtilist>; 5493e8d8bef9SDimitry Andric 549406c3fb27SDimitry Andricmulticlass VPatBinaryV_WV_WX_WI_RM<string intrinsic, string instruction, 549506c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> 549606c3fb27SDimitry Andric : VPatBinaryV_WV_RM<intrinsic, instruction, vtilist>, 549706c3fb27SDimitry Andric VPatBinaryV_WX_RM<intrinsic, instruction, vtilist>, 549806c3fb27SDimitry Andric VPatBinaryV_WI_RM<intrinsic, instruction, vtilist>; 549906c3fb27SDimitry Andric 5500e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction> 550181ad6265SDimitry Andric : VPatBinaryV_VM_TAIL<intrinsic, instruction>, 550281ad6265SDimitry Andric VPatBinaryV_XM_TAIL<intrinsic, instruction>, 550381ad6265SDimitry Andric VPatBinaryV_IM_TAIL<intrinsic, instruction>; 5504e8d8bef9SDimitry Andric 5505e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VM_XM_IM<string intrinsic, string instruction> 550606c3fb27SDimitry Andric : VPatBinaryV_VM<intrinsic, instruction, CarryOut=1>, 550706c3fb27SDimitry Andric VPatBinaryV_XM<intrinsic, instruction, CarryOut=1>, 550806c3fb27SDimitry Andric VPatBinaryV_IM<intrinsic, instruction, CarryOut=1>; 5509e8d8bef9SDimitry Andric 5510e8d8bef9SDimitry Andricmulticlass VPatBinaryM_V_X_I<string intrinsic, string instruction> 5511fe6060f1SDimitry Andric : VPatBinaryV_V<intrinsic, instruction>, 5512fe6060f1SDimitry Andric VPatBinaryV_X<intrinsic, instruction>, 5513fe6060f1SDimitry Andric VPatBinaryV_I<intrinsic, instruction>; 5514e8d8bef9SDimitry Andric 5515e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VM_XM<string intrinsic, string instruction> 551681ad6265SDimitry Andric : VPatBinaryV_VM_TAIL<intrinsic, instruction>, 551781ad6265SDimitry Andric VPatBinaryV_XM_TAIL<intrinsic, instruction>; 5518e8d8bef9SDimitry Andric 5519e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VM_XM<string intrinsic, string instruction> 552006c3fb27SDimitry Andric : VPatBinaryV_VM<intrinsic, instruction, CarryOut=1>, 552106c3fb27SDimitry Andric VPatBinaryV_XM<intrinsic, instruction, CarryOut=1>; 5522e8d8bef9SDimitry Andric 5523e8d8bef9SDimitry Andricmulticlass VPatBinaryM_V_X<string intrinsic, string instruction> 5524fe6060f1SDimitry Andric : VPatBinaryV_V<intrinsic, instruction>, 5525fe6060f1SDimitry Andric VPatBinaryV_X<intrinsic, instruction>; 5526e8d8bef9SDimitry Andric 5527e8d8bef9SDimitry Andricmulticlass VPatTernary<string intrinsic, 5528e8d8bef9SDimitry Andric string inst, 5529e8d8bef9SDimitry Andric string kind, 5530e8d8bef9SDimitry Andric ValueType result_type, 5531e8d8bef9SDimitry Andric ValueType op1_type, 5532e8d8bef9SDimitry Andric ValueType op2_type, 5533e8d8bef9SDimitry Andric ValueType mask_type, 5534e8d8bef9SDimitry Andric int sew, 5535e8d8bef9SDimitry Andric LMULInfo vlmul, 5536e8d8bef9SDimitry Andric VReg result_reg_class, 5537e8d8bef9SDimitry Andric RegisterClass op1_reg_class, 5538e8d8bef9SDimitry Andric DAGOperand op2_kind> { 5539e8d8bef9SDimitry Andric def : VPatTernaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type, 5540349cc55cSDimitry Andric sew, vlmul, result_reg_class, op1_reg_class, 5541e8d8bef9SDimitry Andric op2_kind>; 5542e8d8bef9SDimitry Andric def : VPatTernaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type, 5543e8d8bef9SDimitry Andric mask_type, sew, vlmul, result_reg_class, op1_reg_class, 5544e8d8bef9SDimitry Andric op2_kind>; 5545e8d8bef9SDimitry Andric} 5546e8d8bef9SDimitry Andric 554781ad6265SDimitry Andricmulticlass VPatTernaryNoMaskNoPolicy<string intrinsic, 554881ad6265SDimitry Andric string inst, 554981ad6265SDimitry Andric string kind, 555081ad6265SDimitry Andric ValueType result_type, 555181ad6265SDimitry Andric ValueType op1_type, 555281ad6265SDimitry Andric ValueType op2_type, 555381ad6265SDimitry Andric ValueType mask_type, 555481ad6265SDimitry Andric int sew, 555581ad6265SDimitry Andric LMULInfo vlmul, 555681ad6265SDimitry Andric VReg result_reg_class, 555781ad6265SDimitry Andric RegisterClass op1_reg_class, 555881ad6265SDimitry Andric DAGOperand op2_kind> { 555981ad6265SDimitry Andric def : VPatTernaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type, 556081ad6265SDimitry Andric sew, vlmul, result_reg_class, op1_reg_class, 556181ad6265SDimitry Andric op2_kind>; 556281ad6265SDimitry Andric def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type, 556381ad6265SDimitry Andric mask_type, sew, vlmul, result_reg_class, op1_reg_class, 556481ad6265SDimitry Andric op2_kind>; 556581ad6265SDimitry Andric} 556681ad6265SDimitry Andric 5567349cc55cSDimitry Andricmulticlass VPatTernaryWithPolicy<string intrinsic, 5568349cc55cSDimitry Andric string inst, 5569349cc55cSDimitry Andric string kind, 5570349cc55cSDimitry Andric ValueType result_type, 5571349cc55cSDimitry Andric ValueType op1_type, 5572349cc55cSDimitry Andric ValueType op2_type, 5573349cc55cSDimitry Andric ValueType mask_type, 5574349cc55cSDimitry Andric int sew, 5575349cc55cSDimitry Andric LMULInfo vlmul, 5576349cc55cSDimitry Andric VReg result_reg_class, 5577349cc55cSDimitry Andric RegisterClass op1_reg_class, 5578349cc55cSDimitry Andric DAGOperand op2_kind> { 5579349cc55cSDimitry Andric def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type, 5580349cc55cSDimitry Andric op2_type, sew, vlmul, result_reg_class, 5581349cc55cSDimitry Andric op1_reg_class, op2_kind>; 558281ad6265SDimitry Andric def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type, 5583349cc55cSDimitry Andric mask_type, sew, vlmul, result_reg_class, op1_reg_class, 5584349cc55cSDimitry Andric op2_kind>; 5585349cc55cSDimitry Andric} 5586349cc55cSDimitry Andric 558706c3fb27SDimitry Andricmulticlass VPatTernaryWithPolicyRoundingMode<string intrinsic, 558806c3fb27SDimitry Andric string inst, 558906c3fb27SDimitry Andric string kind, 559006c3fb27SDimitry Andric ValueType result_type, 559106c3fb27SDimitry Andric ValueType op1_type, 559206c3fb27SDimitry Andric ValueType op2_type, 559306c3fb27SDimitry Andric ValueType mask_type, 559406c3fb27SDimitry Andric int sew, 559506c3fb27SDimitry Andric LMULInfo vlmul, 559606c3fb27SDimitry Andric VReg result_reg_class, 559706c3fb27SDimitry Andric RegisterClass op1_reg_class, 559806c3fb27SDimitry Andric DAGOperand op2_kind> { 559906c3fb27SDimitry Andric def : VPatTernaryNoMaskWithPolicyRoundingMode<intrinsic, inst, kind, result_type, 560006c3fb27SDimitry Andric op1_type, op2_type, sew, vlmul, 560106c3fb27SDimitry Andric result_reg_class, op1_reg_class, 560206c3fb27SDimitry Andric op2_kind>; 560306c3fb27SDimitry Andric def : VPatTernaryMaskPolicyRoundingMode<intrinsic, inst, kind, result_type, op1_type, 560406c3fb27SDimitry Andric op2_type, mask_type, sew, vlmul, 560506c3fb27SDimitry Andric result_reg_class, op1_reg_class, 560606c3fb27SDimitry Andric op2_kind>; 560706c3fb27SDimitry Andric} 560806c3fb27SDimitry Andric 560906c3fb27SDimitry Andricmulticlass VPatTernaryTA<string intrinsic, 561006c3fb27SDimitry Andric string inst, 561106c3fb27SDimitry Andric string kind, 561206c3fb27SDimitry Andric ValueType result_type, 561306c3fb27SDimitry Andric ValueType op1_type, 561406c3fb27SDimitry Andric ValueType op2_type, 561506c3fb27SDimitry Andric ValueType mask_type, 561606c3fb27SDimitry Andric int log2sew, 561706c3fb27SDimitry Andric LMULInfo vlmul, 561806c3fb27SDimitry Andric VReg result_reg_class, 561906c3fb27SDimitry Andric RegisterClass op1_reg_class, 562006c3fb27SDimitry Andric DAGOperand op2_kind> { 562106c3fb27SDimitry Andric def : VPatTernaryNoMaskTA<intrinsic, inst, kind, result_type, op1_type, 562206c3fb27SDimitry Andric op2_type, log2sew, vlmul, result_reg_class, 562306c3fb27SDimitry Andric op1_reg_class, op2_kind>; 562406c3fb27SDimitry Andric def : VPatTernaryMaskTA<intrinsic, inst, kind, result_type, op1_type, 562506c3fb27SDimitry Andric op2_type, mask_type, log2sew, vlmul, 562606c3fb27SDimitry Andric result_reg_class, op1_reg_class, op2_kind>; 562706c3fb27SDimitry Andric} 562806c3fb27SDimitry Andric 562906c3fb27SDimitry Andricmulticlass VPatTernaryTARoundingMode<string intrinsic, 563006c3fb27SDimitry Andric string inst, 563106c3fb27SDimitry Andric string kind, 563206c3fb27SDimitry Andric ValueType result_type, 563306c3fb27SDimitry Andric ValueType op1_type, 563406c3fb27SDimitry Andric ValueType op2_type, 563506c3fb27SDimitry Andric ValueType mask_type, 563606c3fb27SDimitry Andric int log2sew, 563706c3fb27SDimitry Andric LMULInfo vlmul, 563806c3fb27SDimitry Andric VReg result_reg_class, 563906c3fb27SDimitry Andric RegisterClass op1_reg_class, 564006c3fb27SDimitry Andric DAGOperand op2_kind> { 564106c3fb27SDimitry Andric def : VPatTernaryNoMaskTARoundingMode<intrinsic, inst, kind, result_type, op1_type, 564206c3fb27SDimitry Andric op2_type, log2sew, vlmul, result_reg_class, 564306c3fb27SDimitry Andric op1_reg_class, op2_kind>; 564406c3fb27SDimitry Andric def : VPatTernaryMaskTARoundingMode<intrinsic, inst, kind, result_type, op1_type, 564506c3fb27SDimitry Andric op2_type, mask_type, log2sew, vlmul, 564606c3fb27SDimitry Andric result_reg_class, op1_reg_class, op2_kind>; 564706c3fb27SDimitry Andric} 564806c3fb27SDimitry Andric 5649349cc55cSDimitry Andricmulticlass VPatTernaryV_VV_AAXA<string intrinsic, string instruction, 5650e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 5651e8d8bef9SDimitry Andric foreach vti = vtilist in 565206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5653349cc55cSDimitry Andric defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV", 5654e8d8bef9SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 5655fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 5656e8d8bef9SDimitry Andric vti.RegClass, vti.RegClass>; 5657e8d8bef9SDimitry Andric} 5658e8d8bef9SDimitry Andric 565906c3fb27SDimitry Andricmulticlass VPatTernaryV_VV_AAXA_RM<string intrinsic, string instruction, 566006c3fb27SDimitry Andric list<VTypeInfo> vtilist> { 566106c3fb27SDimitry Andric foreach vti = vtilist in 566206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 566306c3fb27SDimitry Andric defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, "VV", 566406c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 566506c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 566606c3fb27SDimitry Andric vti.RegClass, vti.RegClass>; 566706c3fb27SDimitry Andric} 566806c3fb27SDimitry Andric 5669e8d8bef9SDimitry Andricmulticlass VPatTernaryV_VX<string intrinsic, string instruction, 5670e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 5671e8d8bef9SDimitry Andric foreach vti = vtilist in 567206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 567381ad6265SDimitry Andric defm : VPatTernaryWithPolicy<intrinsic, instruction, "VX", 5674e8d8bef9SDimitry Andric vti.Vector, vti.Vector, XLenVT, vti.Mask, 5675fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 5676e8d8bef9SDimitry Andric vti.RegClass, GPR>; 5677e8d8bef9SDimitry Andric} 5678e8d8bef9SDimitry Andric 5679e8d8bef9SDimitry Andricmulticlass VPatTernaryV_VX_AAXA<string intrinsic, string instruction, 5680e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> { 5681e8d8bef9SDimitry Andric foreach vti = vtilist in 568206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 5683349cc55cSDimitry Andric defm : VPatTernaryWithPolicy<intrinsic, instruction, 5684e8d8bef9SDimitry Andric "V"#vti.ScalarSuffix, 5685e8d8bef9SDimitry Andric vti.Vector, vti.Scalar, vti.Vector, vti.Mask, 5686fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 5687e8d8bef9SDimitry Andric vti.ScalarRegClass, vti.RegClass>; 5688e8d8bef9SDimitry Andric} 5689e8d8bef9SDimitry Andric 569006c3fb27SDimitry Andricmulticlass VPatTernaryV_VX_AAXA_RM<string intrinsic, string instruction, 569106c3fb27SDimitry Andric list<VTypeInfo> vtilist> { 569206c3fb27SDimitry Andric foreach vti = vtilist in 569306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 569406c3fb27SDimitry Andric defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, 569506c3fb27SDimitry Andric "V"#vti.ScalarSuffix, 569606c3fb27SDimitry Andric vti.Vector, vti.Scalar, vti.Vector, vti.Mask, 569706c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 569806c3fb27SDimitry Andric vti.ScalarRegClass, vti.RegClass>; 569906c3fb27SDimitry Andric} 570006c3fb27SDimitry Andric 5701e8d8bef9SDimitry Andricmulticlass VPatTernaryV_VI<string intrinsic, string instruction, 5702e8d8bef9SDimitry Andric list<VTypeInfo> vtilist, Operand Imm_type> { 5703e8d8bef9SDimitry Andric foreach vti = vtilist in 570406c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 570581ad6265SDimitry Andric defm : VPatTernaryWithPolicy<intrinsic, instruction, "VI", 5706e8d8bef9SDimitry Andric vti.Vector, vti.Vector, XLenVT, vti.Mask, 5707fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 5708e8d8bef9SDimitry Andric vti.RegClass, Imm_type>; 5709e8d8bef9SDimitry Andric} 5710e8d8bef9SDimitry Andric 5711e8d8bef9SDimitry Andricmulticlass VPatTernaryW_VV<string intrinsic, string instruction, 5712e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5713e8d8bef9SDimitry Andric foreach vtiToWti = vtilist in { 5714e8d8bef9SDimitry Andric defvar vti = vtiToWti.Vti; 5715e8d8bef9SDimitry Andric defvar wti = vtiToWti.Wti; 571606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 571706c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 5718349cc55cSDimitry Andric defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV", 5719e8d8bef9SDimitry Andric wti.Vector, vti.Vector, vti.Vector, 5720fe6060f1SDimitry Andric vti.Mask, vti.Log2SEW, vti.LMul, 5721e8d8bef9SDimitry Andric wti.RegClass, vti.RegClass, vti.RegClass>; 5722e8d8bef9SDimitry Andric } 5723e8d8bef9SDimitry Andric} 5724e8d8bef9SDimitry Andric 572506c3fb27SDimitry Andricmulticlass VPatTernaryW_VV_RM<string intrinsic, string instruction, 572606c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 572706c3fb27SDimitry Andric foreach vtiToWti = vtilist in { 572806c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 572906c3fb27SDimitry Andric defvar wti = vtiToWti.Wti; 573006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 573106c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 573206c3fb27SDimitry Andric defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, "VV", 573306c3fb27SDimitry Andric wti.Vector, vti.Vector, vti.Vector, 573406c3fb27SDimitry Andric vti.Mask, vti.Log2SEW, vti.LMul, 573506c3fb27SDimitry Andric wti.RegClass, vti.RegClass, vti.RegClass>; 573606c3fb27SDimitry Andric } 573706c3fb27SDimitry Andric} 573806c3fb27SDimitry Andric 5739e8d8bef9SDimitry Andricmulticlass VPatTernaryW_VX<string intrinsic, string instruction, 5740e8d8bef9SDimitry Andric list<VTypeInfoToWide> vtilist> { 5741e8d8bef9SDimitry Andric foreach vtiToWti = vtilist in { 5742e8d8bef9SDimitry Andric defvar vti = vtiToWti.Vti; 5743e8d8bef9SDimitry Andric defvar wti = vtiToWti.Wti; 574406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 574506c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 5746349cc55cSDimitry Andric defm : VPatTernaryWithPolicy<intrinsic, instruction, 5747e8d8bef9SDimitry Andric "V"#vti.ScalarSuffix, 5748e8d8bef9SDimitry Andric wti.Vector, vti.Scalar, vti.Vector, 5749fe6060f1SDimitry Andric vti.Mask, vti.Log2SEW, vti.LMul, 5750e8d8bef9SDimitry Andric wti.RegClass, vti.ScalarRegClass, vti.RegClass>; 5751e8d8bef9SDimitry Andric } 5752e8d8bef9SDimitry Andric} 5753e8d8bef9SDimitry Andric 575406c3fb27SDimitry Andricmulticlass VPatTernaryW_VX_RM<string intrinsic, string instruction, 575506c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> { 575606c3fb27SDimitry Andric foreach vtiToWti = vtilist in { 575706c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 575806c3fb27SDimitry Andric defvar wti = vtiToWti.Wti; 575906c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 576006c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 576106c3fb27SDimitry Andric defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, 576206c3fb27SDimitry Andric "V"#vti.ScalarSuffix, 576306c3fb27SDimitry Andric wti.Vector, vti.Scalar, vti.Vector, 576406c3fb27SDimitry Andric vti.Mask, vti.Log2SEW, vti.LMul, 576506c3fb27SDimitry Andric wti.RegClass, vti.ScalarRegClass, 576606c3fb27SDimitry Andric vti.RegClass>; 576706c3fb27SDimitry Andric } 576806c3fb27SDimitry Andric} 576906c3fb27SDimitry Andric 5770e8d8bef9SDimitry Andricmulticlass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction, 5771fe6060f1SDimitry Andric list<VTypeInfo> vtilist> 5772349cc55cSDimitry Andric : VPatTernaryV_VV_AAXA<intrinsic, instruction, vtilist>, 5773fe6060f1SDimitry Andric VPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>; 5774e8d8bef9SDimitry Andric 577506c3fb27SDimitry Andricmulticlass VPatTernaryV_VV_VX_AAXA_RM<string intrinsic, string instruction, 577606c3fb27SDimitry Andric list<VTypeInfo> vtilist> 577706c3fb27SDimitry Andric : VPatTernaryV_VV_AAXA_RM<intrinsic, instruction, vtilist>, 577806c3fb27SDimitry Andric VPatTernaryV_VX_AAXA_RM<intrinsic, instruction, vtilist>; 577906c3fb27SDimitry Andric 5780e8d8bef9SDimitry Andricmulticlass VPatTernaryV_VX_VI<string intrinsic, string instruction, 5781fe6060f1SDimitry Andric list<VTypeInfo> vtilist, Operand Imm_type = simm5> 5782fe6060f1SDimitry Andric : VPatTernaryV_VX<intrinsic, instruction, vtilist>, 5783fe6060f1SDimitry Andric VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>; 5784e8d8bef9SDimitry Andric 578581ad6265SDimitry Andric 5786e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VV_VX_VI<string intrinsic, string instruction, 5787e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> 5788fe6060f1SDimitry Andric : VPatBinaryM_VV<intrinsic, instruction, vtilist>, 5789fe6060f1SDimitry Andric VPatBinaryM_VX<intrinsic, instruction, vtilist>, 5790fe6060f1SDimitry Andric VPatBinaryM_VI<intrinsic, instruction, vtilist>; 5791e8d8bef9SDimitry Andric 5792e8d8bef9SDimitry Andricmulticlass VPatTernaryW_VV_VX<string intrinsic, string instruction, 5793fe6060f1SDimitry Andric list<VTypeInfoToWide> vtilist> 5794fe6060f1SDimitry Andric : VPatTernaryW_VV<intrinsic, instruction, vtilist>, 5795fe6060f1SDimitry Andric VPatTernaryW_VX<intrinsic, instruction, vtilist>; 5796e8d8bef9SDimitry Andric 579706c3fb27SDimitry Andricmulticlass VPatTernaryW_VV_VX_RM<string intrinsic, string instruction, 579806c3fb27SDimitry Andric list<VTypeInfoToWide> vtilist> 579906c3fb27SDimitry Andric : VPatTernaryW_VV_RM<intrinsic, instruction, vtilist>, 580006c3fb27SDimitry Andric VPatTernaryW_VX_RM<intrinsic, instruction, vtilist>; 580106c3fb27SDimitry Andric 5802e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VV_VX<string intrinsic, string instruction, 5803e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> 5804fe6060f1SDimitry Andric : VPatBinaryM_VV<intrinsic, instruction, vtilist>, 5805fe6060f1SDimitry Andric VPatBinaryM_VX<intrinsic, instruction, vtilist>; 5806e8d8bef9SDimitry Andric 5807e8d8bef9SDimitry Andricmulticlass VPatBinaryM_VX_VI<string intrinsic, string instruction, 5808e8d8bef9SDimitry Andric list<VTypeInfo> vtilist> 5809fe6060f1SDimitry Andric : VPatBinaryM_VX<intrinsic, instruction, vtilist>, 5810fe6060f1SDimitry Andric VPatBinaryM_VI<intrinsic, instruction, vtilist>; 5811e8d8bef9SDimitry Andric 5812e8d8bef9SDimitry Andricmulticlass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction, 5813e8d8bef9SDimitry Andric list<VTypeInfo> vtilist, Operand ImmType = simm5> 5814fe6060f1SDimitry Andric : VPatBinaryV_VV_INT<intrinsic#"_vv", instruction, vtilist>, 5815fe6060f1SDimitry Andric VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>, 5816fe6060f1SDimitry Andric VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>; 5817e8d8bef9SDimitry Andric 5818e8d8bef9SDimitry Andricmulticlass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat = 0> { 581906c3fb27SDimitry Andric foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in { 5820e8d8bef9SDimitry Andric defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1"); 582106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 582206c3fb27SDimitry Andric defm : VPatTernaryTA<intrinsic, instruction, "VS", 5823e8d8bef9SDimitry Andric vectorM1.Vector, vti.Vector, 5824e8d8bef9SDimitry Andric vectorM1.Vector, vti.Mask, 5825fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5826e8d8bef9SDimitry Andric VR, vti.RegClass, VR>; 5827e8d8bef9SDimitry Andric } 582806c3fb27SDimitry Andric foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in { 582906c3fb27SDimitry Andric let Predicates = GetVTypePredicates<gvti>.Predicates in 583006c3fb27SDimitry Andric defm : VPatTernaryTA<intrinsic, instruction, "VS", 583106c3fb27SDimitry Andric gvti.VectorM1, gvti.Vector, 583206c3fb27SDimitry Andric gvti.VectorM1, gvti.Mask, 583306c3fb27SDimitry Andric gvti.Log2SEW, gvti.LMul, 583406c3fb27SDimitry Andric VR, gvti.RegClass, VR>; 583506c3fb27SDimitry Andric } 583606c3fb27SDimitry Andric} 583706c3fb27SDimitry Andric 583806c3fb27SDimitry Andricmulticlass VPatReductionV_VS_RM<string intrinsic, string instruction, bit IsFloat = 0> { 583906c3fb27SDimitry Andric foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in { 584006c3fb27SDimitry Andric defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1"); 584106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 584206c3fb27SDimitry Andric defm : VPatTernaryTARoundingMode<intrinsic, instruction, "VS", 584306c3fb27SDimitry Andric vectorM1.Vector, vti.Vector, 584406c3fb27SDimitry Andric vectorM1.Vector, vti.Mask, 584506c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, 584606c3fb27SDimitry Andric VR, vti.RegClass, VR>; 584706c3fb27SDimitry Andric } 584806c3fb27SDimitry Andric foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in { 584906c3fb27SDimitry Andric let Predicates = GetVTypePredicates<gvti>.Predicates in 585006c3fb27SDimitry Andric defm : VPatTernaryTARoundingMode<intrinsic, instruction, "VS", 5851e8d8bef9SDimitry Andric gvti.VectorM1, gvti.Vector, 5852e8d8bef9SDimitry Andric gvti.VectorM1, gvti.Mask, 5853fe6060f1SDimitry Andric gvti.Log2SEW, gvti.LMul, 5854e8d8bef9SDimitry Andric VR, gvti.RegClass, VR>; 5855e8d8bef9SDimitry Andric } 5856e8d8bef9SDimitry Andric} 5857e8d8bef9SDimitry Andric 5858e8d8bef9SDimitry Andricmulticlass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> { 585906c3fb27SDimitry Andric foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in { 5860e8d8bef9SDimitry Andric defvar wtiSEW = !mul(vti.SEW, 2); 5861e8d8bef9SDimitry Andric if !le(wtiSEW, 64) then { 5862e8d8bef9SDimitry Andric defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1"); 586306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 586406c3fb27SDimitry Andric defm : VPatTernaryTA<intrinsic, instruction, "VS", 586506c3fb27SDimitry Andric wtiM1.Vector, vti.Vector, 586606c3fb27SDimitry Andric wtiM1.Vector, vti.Mask, 586706c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, 586806c3fb27SDimitry Andric wtiM1.RegClass, vti.RegClass, 586906c3fb27SDimitry Andric wtiM1.RegClass>; 587006c3fb27SDimitry Andric } 587106c3fb27SDimitry Andric } 587206c3fb27SDimitry Andric} 587306c3fb27SDimitry Andric 587406c3fb27SDimitry Andricmulticlass VPatReductionW_VS_RM<string intrinsic, string instruction, bit IsFloat = 0> { 587506c3fb27SDimitry Andric foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in { 587606c3fb27SDimitry Andric defvar wtiSEW = !mul(vti.SEW, 2); 587706c3fb27SDimitry Andric if !le(wtiSEW, 64) then { 587806c3fb27SDimitry Andric defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1"); 587906c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 588006c3fb27SDimitry Andric defm : VPatTernaryTARoundingMode<intrinsic, instruction, "VS", 5881e8d8bef9SDimitry Andric wtiM1.Vector, vti.Vector, 5882e8d8bef9SDimitry Andric wtiM1.Vector, vti.Mask, 5883fe6060f1SDimitry Andric vti.Log2SEW, vti.LMul, 5884e8d8bef9SDimitry Andric wtiM1.RegClass, vti.RegClass, 5885e8d8bef9SDimitry Andric wtiM1.RegClass>; 5886e8d8bef9SDimitry Andric } 5887e8d8bef9SDimitry Andric } 5888e8d8bef9SDimitry Andric} 5889e8d8bef9SDimitry Andric 5890349cc55cSDimitry Andricmulticlass VPatConversionVI_VF<string intrinsic, 589106c3fb27SDimitry Andric string instruction> { 589206c3fb27SDimitry Andric foreach fvti = AllFloatVectors in { 5893349cc55cSDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 589406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 589506c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 5896349cc55cSDimitry Andric defm : VPatConversionTA<intrinsic, instruction, "V", 5897349cc55cSDimitry Andric ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW, 5898349cc55cSDimitry Andric fvti.LMul, ivti.RegClass, fvti.RegClass>; 5899349cc55cSDimitry Andric } 5900349cc55cSDimitry Andric} 5901349cc55cSDimitry Andric 590206c3fb27SDimitry Andricmulticlass VPatConversionVI_VF_RM<string intrinsic, 590306c3fb27SDimitry Andric string instruction> { 590406c3fb27SDimitry Andric foreach fvti = AllFloatVectors in { 5905e8d8bef9SDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 590606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 590706c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 590806c3fb27SDimitry Andric defm : VPatConversionTARoundingMode<intrinsic, instruction, "V", 590906c3fb27SDimitry Andric ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW, 591006c3fb27SDimitry Andric fvti.LMul, ivti.RegClass, fvti.RegClass>; 591106c3fb27SDimitry Andric } 591206c3fb27SDimitry Andric} 5913e8d8bef9SDimitry Andric 591406c3fb27SDimitry Andricmulticlass VPatConversionVF_VI_RM<string intrinsic, 591506c3fb27SDimitry Andric string instruction> { 591606c3fb27SDimitry Andric foreach fvti = AllFloatVectors in { 591706c3fb27SDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 591806c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 591906c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 592006c3fb27SDimitry Andric defm : VPatConversionTARoundingMode<intrinsic, instruction, "V", 5921fe6060f1SDimitry Andric fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW, 5922e8d8bef9SDimitry Andric ivti.LMul, fvti.RegClass, ivti.RegClass>; 5923e8d8bef9SDimitry Andric } 5924e8d8bef9SDimitry Andric} 5925e8d8bef9SDimitry Andric 5926e8d8bef9SDimitry Andricmulticlass VPatConversionWI_VF<string intrinsic, string instruction> { 592706c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 5928e8d8bef9SDimitry Andric defvar fvti = fvtiToFWti.Vti; 5929e8d8bef9SDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 593006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 593106c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 5932349cc55cSDimitry Andric defm : VPatConversionTA<intrinsic, instruction, "V", 5933fe6060f1SDimitry Andric iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW, 5934e8d8bef9SDimitry Andric fvti.LMul, iwti.RegClass, fvti.RegClass>; 5935e8d8bef9SDimitry Andric } 5936e8d8bef9SDimitry Andric} 5937e8d8bef9SDimitry Andric 593806c3fb27SDimitry Andricmulticlass VPatConversionWI_VF_RM<string intrinsic, string instruction> { 593906c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 594006c3fb27SDimitry Andric defvar fvti = fvtiToFWti.Vti; 594106c3fb27SDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 594206c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 594306c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 594406c3fb27SDimitry Andric defm : VPatConversionTARoundingMode<intrinsic, instruction, "V", 594506c3fb27SDimitry Andric iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW, 594606c3fb27SDimitry Andric fvti.LMul, iwti.RegClass, fvti.RegClass>; 594706c3fb27SDimitry Andric } 594806c3fb27SDimitry Andric} 594906c3fb27SDimitry Andric 5950e8d8bef9SDimitry Andricmulticlass VPatConversionWF_VI<string intrinsic, string instruction> { 595106c3fb27SDimitry Andric foreach vtiToWti = AllWidenableIntToFloatVectors in { 5952e8d8bef9SDimitry Andric defvar vti = vtiToWti.Vti; 5953e8d8bef9SDimitry Andric defvar fwti = vtiToWti.Wti; 595406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 595506c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 5956349cc55cSDimitry Andric defm : VPatConversionTA<intrinsic, instruction, "V", 5957fe6060f1SDimitry Andric fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW, 5958e8d8bef9SDimitry Andric vti.LMul, fwti.RegClass, vti.RegClass>; 5959e8d8bef9SDimitry Andric } 5960e8d8bef9SDimitry Andric} 5961e8d8bef9SDimitry Andric 5962e8d8bef9SDimitry Andricmulticlass VPatConversionWF_VF<string intrinsic, string instruction> { 596306c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 5964e8d8bef9SDimitry Andric defvar fvti = fvtiToFWti.Vti; 5965e8d8bef9SDimitry Andric defvar fwti = fvtiToFWti.Wti; 59665f757f3fSDimitry Andric // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable. 59675f757f3fSDimitry Andric let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal], 59685f757f3fSDimitry Andric !listconcat(GetVTypePredicates<fvti>.Predicates, 59695f757f3fSDimitry Andric GetVTypePredicates<fwti>.Predicates)) in 59705f757f3fSDimitry Andric defm : VPatConversionTA<intrinsic, instruction, "V", 59715f757f3fSDimitry Andric fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW, 59725f757f3fSDimitry Andric fvti.LMul, fwti.RegClass, fvti.RegClass>; 59735f757f3fSDimitry Andric } 59745f757f3fSDimitry Andric} 59755f757f3fSDimitry Andric 59765f757f3fSDimitry Andricmulticlass VPatConversionWF_VF_BF <string intrinsic, string instruction> { 59775f757f3fSDimitry Andric foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in 59785f757f3fSDimitry Andric { 59795f757f3fSDimitry Andric defvar fvti = fvtiToFWti.Vti; 59805f757f3fSDimitry Andric defvar fwti = fvtiToFWti.Wti; 598106c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 598206c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 5983349cc55cSDimitry Andric defm : VPatConversionTA<intrinsic, instruction, "V", 5984fe6060f1SDimitry Andric fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW, 5985e8d8bef9SDimitry Andric fvti.LMul, fwti.RegClass, fvti.RegClass>; 5986e8d8bef9SDimitry Andric } 5987e8d8bef9SDimitry Andric} 5988e8d8bef9SDimitry Andric 5989e8d8bef9SDimitry Andricmulticlass VPatConversionVI_WF <string intrinsic, string instruction> { 599006c3fb27SDimitry Andric foreach vtiToWti = AllWidenableIntToFloatVectors in { 5991e8d8bef9SDimitry Andric defvar vti = vtiToWti.Vti; 5992e8d8bef9SDimitry Andric defvar fwti = vtiToWti.Wti; 599306c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 599406c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 5995349cc55cSDimitry Andric defm : VPatConversionTA<intrinsic, instruction, "W", 5996fe6060f1SDimitry Andric vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW, 5997e8d8bef9SDimitry Andric vti.LMul, vti.RegClass, fwti.RegClass>; 5998e8d8bef9SDimitry Andric } 5999e8d8bef9SDimitry Andric} 6000e8d8bef9SDimitry Andric 600106c3fb27SDimitry Andricmulticlass VPatConversionVI_WF_RM <string intrinsic, string instruction> { 600206c3fb27SDimitry Andric foreach vtiToWti = AllWidenableIntToFloatVectors in { 600306c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 600406c3fb27SDimitry Andric defvar fwti = vtiToWti.Wti; 600506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 600606c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 600706c3fb27SDimitry Andric defm : VPatConversionTARoundingMode<intrinsic, instruction, "W", 600806c3fb27SDimitry Andric vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW, 600906c3fb27SDimitry Andric vti.LMul, vti.RegClass, fwti.RegClass>; 601006c3fb27SDimitry Andric } 601106c3fb27SDimitry Andric} 601206c3fb27SDimitry Andric 601306c3fb27SDimitry Andricmulticlass VPatConversionVF_WI_RM <string intrinsic, string instruction> { 601406c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 6015e8d8bef9SDimitry Andric defvar fvti = fvtiToFWti.Vti; 6016e8d8bef9SDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 601706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 601806c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 601906c3fb27SDimitry Andric defm : VPatConversionTARoundingMode<intrinsic, instruction, "W", 6020fe6060f1SDimitry Andric fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW, 6021e8d8bef9SDimitry Andric fvti.LMul, fvti.RegClass, iwti.RegClass>; 6022e8d8bef9SDimitry Andric } 6023e8d8bef9SDimitry Andric} 6024e8d8bef9SDimitry Andric 6025e8d8bef9SDimitry Andricmulticlass VPatConversionVF_WF <string intrinsic, string instruction> { 602606c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 6027e8d8bef9SDimitry Andric defvar fvti = fvtiToFWti.Vti; 6028e8d8bef9SDimitry Andric defvar fwti = fvtiToFWti.Wti; 602906c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 603006c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 6031349cc55cSDimitry Andric defm : VPatConversionTA<intrinsic, instruction, "W", 6032fe6060f1SDimitry Andric fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW, 6033e8d8bef9SDimitry Andric fvti.LMul, fvti.RegClass, fwti.RegClass>; 6034e8d8bef9SDimitry Andric } 6035e8d8bef9SDimitry Andric} 6036e8d8bef9SDimitry Andric 60375f757f3fSDimitry Andricmulticlass VPatConversionVF_WF_RM <string intrinsic, string instruction, 60385f757f3fSDimitry Andric list<VTypeInfoToWide> wlist = AllWidenableFloatVectors> { 60395f757f3fSDimitry Andric foreach fvtiToFWti = wlist in { 60405f757f3fSDimitry Andric defvar fvti = fvtiToFWti.Vti; 60415f757f3fSDimitry Andric defvar fwti = fvtiToFWti.Wti; 60425f757f3fSDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 60435f757f3fSDimitry Andric GetVTypePredicates<fwti>.Predicates) in 60445f757f3fSDimitry Andric defm : VPatConversionTARoundingMode<intrinsic, instruction, "W", 60455f757f3fSDimitry Andric fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW, 60465f757f3fSDimitry Andric fvti.LMul, fvti.RegClass, fwti.RegClass>; 60475f757f3fSDimitry Andric } 60485f757f3fSDimitry Andric} 60495f757f3fSDimitry Andric 60505f757f3fSDimitry Andricmulticlass VPatConversionVF_WF_BF_RM <string intrinsic, string instruction> { 60515f757f3fSDimitry Andric foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { 605206c3fb27SDimitry Andric defvar fvti = fvtiToFWti.Vti; 605306c3fb27SDimitry Andric defvar fwti = fvtiToFWti.Wti; 605406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 605506c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 605606c3fb27SDimitry Andric defm : VPatConversionTARoundingMode<intrinsic, instruction, "W", 605706c3fb27SDimitry Andric fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW, 605806c3fb27SDimitry Andric fvti.LMul, fvti.RegClass, fwti.RegClass>; 605906c3fb27SDimitry Andric } 606006c3fb27SDimitry Andric} 606106c3fb27SDimitry Andric 606204eeddc0SDimitry Andricmulticlass VPatCompare_VI<string intrinsic, string inst, 60631fd87a68SDimitry Andric ImmLeaf ImmType> { 606404eeddc0SDimitry Andric foreach vti = AllIntegerVectors in { 606504eeddc0SDimitry Andric defvar Intr = !cast<Intrinsic>(intrinsic); 606604eeddc0SDimitry Andric defvar Pseudo = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX); 606706c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 606804eeddc0SDimitry Andric def : Pat<(vti.Mask (Intr (vti.Vector vti.RegClass:$rs1), 606904eeddc0SDimitry Andric (vti.Scalar ImmType:$rs2), 607004eeddc0SDimitry Andric VLOpFrag)), 607104eeddc0SDimitry Andric (Pseudo vti.RegClass:$rs1, (DecImm ImmType:$rs2), 607204eeddc0SDimitry Andric GPR:$vl, vti.Log2SEW)>; 607304eeddc0SDimitry Andric defvar IntrMask = !cast<Intrinsic>(intrinsic # "_mask"); 607404eeddc0SDimitry Andric defvar PseudoMask = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX#"_MASK"); 607506c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 607604eeddc0SDimitry Andric def : Pat<(vti.Mask (IntrMask (vti.Mask VR:$merge), 607704eeddc0SDimitry Andric (vti.Vector vti.RegClass:$rs1), 607804eeddc0SDimitry Andric (vti.Scalar ImmType:$rs2), 607904eeddc0SDimitry Andric (vti.Mask V0), 608004eeddc0SDimitry Andric VLOpFrag)), 608104eeddc0SDimitry Andric (PseudoMask VR:$merge, vti.RegClass:$rs1, (DecImm ImmType:$rs2), 608204eeddc0SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 608304eeddc0SDimitry Andric } 608404eeddc0SDimitry Andric} 608504eeddc0SDimitry Andric 6086e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6087e8d8bef9SDimitry Andric// Pseudo instructions 6088e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6089e8d8bef9SDimitry Andric 6090349cc55cSDimitry Andriclet Predicates = [HasVInstructions] in { 6091e8d8bef9SDimitry Andric 6092e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6093e8d8bef9SDimitry Andric// Pseudo Instructions for CodeGen 6094e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6095e8d8bef9SDimitry Andric 6096e8d8bef9SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in { 6097e8d8bef9SDimitry Andric def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins), 6098bdd1243dSDimitry Andric [(set GPR:$rd, (riscv_read_vlenb))]>, 609906c3fb27SDimitry Andric PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVLENB.Encoding, X0)>, 6100bdd1243dSDimitry Andric Sched<[WriteRdVLENB]>; 6101e8d8bef9SDimitry Andric} 6102e8d8bef9SDimitry Andric 6103e8d8bef9SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, 6104e8d8bef9SDimitry Andric Uses = [VL] in 610506c3fb27SDimitry Andricdef PseudoReadVL : Pseudo<(outs GPR:$rd), (ins), []>, 610606c3fb27SDimitry Andric PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVL.Encoding, X0)>; 6107fe6060f1SDimitry Andric 610804eeddc0SDimitry Andricforeach lmul = MxList in { 6109fe6060f1SDimitry Andric foreach nf = NFSet<lmul>.L in { 6110fe6060f1SDimitry Andric defvar vreg = SegRegClass<lmul, nf>.RC; 61111fd87a68SDimitry Andric let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1, 61121fd87a68SDimitry Andric Size = !mul(4, !sub(!mul(nf, 2), 1)) in { 6113fe6060f1SDimitry Andric def "PseudoVSPILL" # nf # "_" # lmul.MX : 6114bdd1243dSDimitry Andric Pseudo<(outs), (ins vreg:$rs1, GPR:$rs2), []>; 6115fe6060f1SDimitry Andric } 61161fd87a68SDimitry Andric let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1, 61171fd87a68SDimitry Andric Size = !mul(4, !sub(!mul(nf, 2), 1)) in { 6118fe6060f1SDimitry Andric def "PseudoVRELOAD" # nf # "_" # lmul.MX : 6119bdd1243dSDimitry Andric Pseudo<(outs vreg:$rs1), (ins GPR:$rs2), []>; 6120fe6060f1SDimitry Andric } 6121fe6060f1SDimitry Andric } 6122fe6060f1SDimitry Andric} 6123e8d8bef9SDimitry Andric 612406c3fb27SDimitry Andric/// Empty pseudo for RISCVInitUndefPass 612506c3fb27SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 0, 612606c3fb27SDimitry Andric isCodeGenOnly = 1 in { 612706c3fb27SDimitry Andric def PseudoRVVInitUndefM1 : Pseudo<(outs VR:$vd), (ins), [], "">; 612806c3fb27SDimitry Andric def PseudoRVVInitUndefM2 : Pseudo<(outs VRM2:$vd), (ins), [], "">; 612906c3fb27SDimitry Andric def PseudoRVVInitUndefM4 : Pseudo<(outs VRM4:$vd), (ins), [], "">; 613006c3fb27SDimitry Andric def PseudoRVVInitUndefM8 : Pseudo<(outs VRM8:$vd), (ins), [], "">; 613106c3fb27SDimitry Andric} 613206c3fb27SDimitry Andric 6133e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6134e8d8bef9SDimitry Andric// 6. Configuration-Setting Instructions 6135e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6136e8d8bef9SDimitry Andric 6137e8d8bef9SDimitry Andric// Pseudos. 6138e8d8bef9SDimitry Andriclet hasSideEffects = 1, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in { 6139349cc55cSDimitry Andric// Due to rs1=X0 having special meaning, we need a GPRNoX0 register class for 6140349cc55cSDimitry Andric// the when we aren't using one of the special X0 encodings. Otherwise it could 6141349cc55cSDimitry Andric// be accidentally be made X0 by MachineIR optimizations. To satisfy the 6142349cc55cSDimitry Andric// verifier, we also need a GPRX0 instruction for the special encodings. 6143bdd1243dSDimitry Andricdef PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$rs1, VTypeIOp11:$vtypei), []>, 6144bdd1243dSDimitry Andric Sched<[WriteVSETVLI, ReadVSETVLI]>; 6145bdd1243dSDimitry Andricdef PseudoVSETVLIX0 : Pseudo<(outs GPR:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>, 6146bdd1243dSDimitry Andric Sched<[WriteVSETVLI, ReadVSETVLI]>; 6147bdd1243dSDimitry Andricdef PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp10:$vtypei), []>, 6148bdd1243dSDimitry Andric Sched<[WriteVSETIVLI]>; 6149e8d8bef9SDimitry Andric} 6150e8d8bef9SDimitry Andric 6151e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6152e8d8bef9SDimitry Andric// 7. Vector Loads and Stores 6153e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6154e8d8bef9SDimitry Andric 6155e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6156e8d8bef9SDimitry Andric// 7.4 Vector Unit-Stride Instructions 6157e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6158e8d8bef9SDimitry Andric 6159e8d8bef9SDimitry Andric// Pseudos Unit-Stride Loads and Stores 61600eae32dcSDimitry Andricdefm PseudoVL : VPseudoUSLoad; 6161fe6060f1SDimitry Andricdefm PseudoVS : VPseudoUSStore; 6162e8d8bef9SDimitry Andric 6163bdd1243dSDimitry Andricdefm PseudoVLM : VPseudoLoadMask; 6164bdd1243dSDimitry Andricdefm PseudoVSM : VPseudoStoreMask; 6165d409305fSDimitry Andric 6166e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6167e8d8bef9SDimitry Andric// 7.5 Vector Strided Instructions 6168e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6169e8d8bef9SDimitry Andric 6170e8d8bef9SDimitry Andric// Vector Strided Loads and Stores 6171fe6060f1SDimitry Andricdefm PseudoVLS : VPseudoSLoad; 6172fe6060f1SDimitry Andricdefm PseudoVSS : VPseudoSStore; 6173e8d8bef9SDimitry Andric 6174e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6175e8d8bef9SDimitry Andric// 7.6 Vector Indexed Instructions 6176e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6177e8d8bef9SDimitry Andric 6178e8d8bef9SDimitry Andric// Vector Indexed Loads and Stores 617906c3fb27SDimitry Andricdefm PseudoVLUX : VPseudoILoad<Ordered=false>; 618006c3fb27SDimitry Andricdefm PseudoVLOX : VPseudoILoad<Ordered=true>; 618106c3fb27SDimitry Andricdefm PseudoVSOX : VPseudoIStore<Ordered=true>; 618206c3fb27SDimitry Andricdefm PseudoVSUX : VPseudoIStore<Ordered=false>; 6183e8d8bef9SDimitry Andric 6184e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6185e8d8bef9SDimitry Andric// 7.7. Unit-stride Fault-Only-First Loads 6186e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6187e8d8bef9SDimitry Andric 6188e8d8bef9SDimitry Andric// vleff may update VL register 6189e8d8bef9SDimitry Andriclet hasSideEffects = 1, Defs = [VL] in 61900eae32dcSDimitry Andricdefm PseudoVL : VPseudoFFLoad; 6191e8d8bef9SDimitry Andric 6192e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6193e8d8bef9SDimitry Andric// 7.8. Vector Load/Store Segment Instructions 6194e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 619581ad6265SDimitry Andricdefm PseudoVLSEG : VPseudoUSSegLoad; 6196e8d8bef9SDimitry Andricdefm PseudoVLSSEG : VPseudoSSegLoad; 619706c3fb27SDimitry Andricdefm PseudoVLOXSEG : VPseudoISegLoad<Ordered=true>; 619806c3fb27SDimitry Andricdefm PseudoVLUXSEG : VPseudoISegLoad<Ordered=false>; 6199e8d8bef9SDimitry Andricdefm PseudoVSSEG : VPseudoUSSegStore; 6200e8d8bef9SDimitry Andricdefm PseudoVSSSEG : VPseudoSSegStore; 620106c3fb27SDimitry Andricdefm PseudoVSOXSEG : VPseudoISegStore<Ordered=true>; 620206c3fb27SDimitry Andricdefm PseudoVSUXSEG : VPseudoISegStore<Ordered=false>; 6203e8d8bef9SDimitry Andric 6204e8d8bef9SDimitry Andric// vlseg<nf>e<eew>ff.v may update VL register 620581ad6265SDimitry Andriclet hasSideEffects = 1, Defs = [VL] in { 620681ad6265SDimitry Andricdefm PseudoVLSEG : VPseudoUSSegLoadFF; 620781ad6265SDimitry Andric} 6208e8d8bef9SDimitry Andric 6209e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6210bdd1243dSDimitry Andric// 11. Vector Integer Arithmetic Instructions 6211e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6212e8d8bef9SDimitry Andric 6213e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6214bdd1243dSDimitry Andric// 11.1. Vector Single-Width Integer Add and Subtract 6215e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 62160eae32dcSDimitry Andricdefm PseudoVADD : VPseudoVALU_VV_VX_VI; 62170eae32dcSDimitry Andricdefm PseudoVSUB : VPseudoVALU_VV_VX; 62180eae32dcSDimitry Andricdefm PseudoVRSUB : VPseudoVALU_VX_VI; 6219e8d8bef9SDimitry Andric 6220fe6060f1SDimitry Andricforeach vti = AllIntegerVectors in { 6221fe6060f1SDimitry Andric // Match vrsub with 2 vector operands to vsub.vv by swapping operands. This 6222fe6060f1SDimitry Andric // Occurs when legalizing vrsub.vx intrinsics for i64 on RV32 since we need 6223fe6060f1SDimitry Andric // to use a more complex splat sequence. Add the pattern for all VTs for 6224fe6060f1SDimitry Andric // consistency. 622506c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 622681ad6265SDimitry Andric def : Pat<(vti.Vector (int_riscv_vrsub (vti.Vector vti.RegClass:$merge), 622781ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs2), 622881ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs1), 622981ad6265SDimitry Andric VLOpFrag)), 623006c3fb27SDimitry Andric (!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX) 623181ad6265SDimitry Andric vti.RegClass:$merge, 623281ad6265SDimitry Andric vti.RegClass:$rs1, 623381ad6265SDimitry Andric vti.RegClass:$rs2, 623481ad6265SDimitry Andric GPR:$vl, 623506c3fb27SDimitry Andric vti.Log2SEW, TU_MU)>; 6236fe6060f1SDimitry Andric def : Pat<(vti.Vector (int_riscv_vrsub_mask (vti.Vector vti.RegClass:$merge), 6237fe6060f1SDimitry Andric (vti.Vector vti.RegClass:$rs2), 6238fe6060f1SDimitry Andric (vti.Vector vti.RegClass:$rs1), 6239fe6060f1SDimitry Andric (vti.Mask V0), 6240349cc55cSDimitry Andric VLOpFrag, 6241349cc55cSDimitry Andric (XLenVT timm:$policy))), 6242fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX#"_MASK") 6243fe6060f1SDimitry Andric vti.RegClass:$merge, 6244fe6060f1SDimitry Andric vti.RegClass:$rs1, 6245fe6060f1SDimitry Andric vti.RegClass:$rs2, 6246fe6060f1SDimitry Andric (vti.Mask V0), 6247fe6060f1SDimitry Andric GPR:$vl, 6248349cc55cSDimitry Andric vti.Log2SEW, 6249349cc55cSDimitry Andric (XLenVT timm:$policy))>; 6250fe6060f1SDimitry Andric 6251fe6060f1SDimitry Andric // Match VSUB with a small immediate to vadd.vi by negating the immediate. 625281ad6265SDimitry Andric def : Pat<(vti.Vector (int_riscv_vsub (vti.Vector (undef)), 625381ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs1), 6254fe6060f1SDimitry Andric (vti.Scalar simm5_plus1:$rs2), 6255fe6060f1SDimitry Andric VLOpFrag)), 625606c3fb27SDimitry Andric (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX) (vti.Vector (IMPLICIT_DEF)), 625706c3fb27SDimitry Andric vti.RegClass:$rs1, 6258fe6060f1SDimitry Andric (NegImm simm5_plus1:$rs2), 6259fe6060f1SDimitry Andric GPR:$vl, 62605f757f3fSDimitry Andric vti.Log2SEW, TA_MA)>; 6261fe6060f1SDimitry Andric def : Pat<(vti.Vector (int_riscv_vsub_mask (vti.Vector vti.RegClass:$merge), 6262fe6060f1SDimitry Andric (vti.Vector vti.RegClass:$rs1), 6263fe6060f1SDimitry Andric (vti.Scalar simm5_plus1:$rs2), 6264fe6060f1SDimitry Andric (vti.Mask V0), 6265349cc55cSDimitry Andric VLOpFrag, 6266349cc55cSDimitry Andric (XLenVT timm:$policy))), 6267fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX#"_MASK") 6268fe6060f1SDimitry Andric vti.RegClass:$merge, 6269fe6060f1SDimitry Andric vti.RegClass:$rs1, 6270fe6060f1SDimitry Andric (NegImm simm5_plus1:$rs2), 6271fe6060f1SDimitry Andric (vti.Mask V0), 6272fe6060f1SDimitry Andric GPR:$vl, 6273349cc55cSDimitry Andric vti.Log2SEW, 6274349cc55cSDimitry Andric (XLenVT timm:$policy))>; 6275fe6060f1SDimitry Andric } 627606c3fb27SDimitry Andric} 6277fe6060f1SDimitry Andric 6278e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6279bdd1243dSDimitry Andric// 11.2. Vector Widening Integer Add/Subtract 6280e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 62810eae32dcSDimitry Andricdefm PseudoVWADDU : VPseudoVWALU_VV_VX; 62820eae32dcSDimitry Andricdefm PseudoVWSUBU : VPseudoVWALU_VV_VX; 62830eae32dcSDimitry Andricdefm PseudoVWADD : VPseudoVWALU_VV_VX; 62840eae32dcSDimitry Andricdefm PseudoVWSUB : VPseudoVWALU_VV_VX; 62850eae32dcSDimitry Andricdefm PseudoVWADDU : VPseudoVWALU_WV_WX; 62860eae32dcSDimitry Andricdefm PseudoVWSUBU : VPseudoVWALU_WV_WX; 62870eae32dcSDimitry Andricdefm PseudoVWADD : VPseudoVWALU_WV_WX; 62880eae32dcSDimitry Andricdefm PseudoVWSUB : VPseudoVWALU_WV_WX; 6289e8d8bef9SDimitry Andric 6290e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6291bdd1243dSDimitry Andric// 11.3. Vector Integer Extension 6292e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 62930eae32dcSDimitry Andricdefm PseudoVZEXT_VF2 : PseudoVEXT_VF2; 62940eae32dcSDimitry Andricdefm PseudoVZEXT_VF4 : PseudoVEXT_VF4; 62950eae32dcSDimitry Andricdefm PseudoVZEXT_VF8 : PseudoVEXT_VF8; 62960eae32dcSDimitry Andricdefm PseudoVSEXT_VF2 : PseudoVEXT_VF2; 62970eae32dcSDimitry Andricdefm PseudoVSEXT_VF4 : PseudoVEXT_VF4; 62980eae32dcSDimitry Andricdefm PseudoVSEXT_VF8 : PseudoVEXT_VF8; 6299e8d8bef9SDimitry Andric 6300e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6301bdd1243dSDimitry Andric// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions 6302e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63030eae32dcSDimitry Andricdefm PseudoVADC : VPseudoVCALU_VM_XM_IM; 63040eae32dcSDimitry Andricdefm PseudoVMADC : VPseudoVCALUM_VM_XM_IM<"@earlyclobber $rd">; 63050eae32dcSDimitry Andricdefm PseudoVMADC : VPseudoVCALUM_V_X_I<"@earlyclobber $rd">; 6306e8d8bef9SDimitry Andric 63070eae32dcSDimitry Andricdefm PseudoVSBC : VPseudoVCALU_VM_XM; 63080eae32dcSDimitry Andricdefm PseudoVMSBC : VPseudoVCALUM_VM_XM<"@earlyclobber $rd">; 63090eae32dcSDimitry Andricdefm PseudoVMSBC : VPseudoVCALUM_V_X<"@earlyclobber $rd">; 6310e8d8bef9SDimitry Andric 6311e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6312bdd1243dSDimitry Andric// 11.5. Vector Bitwise Logical Instructions 6313e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63140eae32dcSDimitry Andricdefm PseudoVAND : VPseudoVALU_VV_VX_VI; 63150eae32dcSDimitry Andricdefm PseudoVOR : VPseudoVALU_VV_VX_VI; 63160eae32dcSDimitry Andricdefm PseudoVXOR : VPseudoVALU_VV_VX_VI; 6317e8d8bef9SDimitry Andric 6318e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6319bdd1243dSDimitry Andric// 11.6. Vector Single-Width Bit Shift Instructions 6320e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63210eae32dcSDimitry Andricdefm PseudoVSLL : VPseudoVSHT_VV_VX_VI<uimm5>; 63220eae32dcSDimitry Andricdefm PseudoVSRL : VPseudoVSHT_VV_VX_VI<uimm5>; 63230eae32dcSDimitry Andricdefm PseudoVSRA : VPseudoVSHT_VV_VX_VI<uimm5>; 6324e8d8bef9SDimitry Andric 6325e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6326bdd1243dSDimitry Andric// 11.7. Vector Narrowing Integer Right Shift Instructions 6327e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63280eae32dcSDimitry Andricdefm PseudoVNSRL : VPseudoVNSHT_WV_WX_WI; 63290eae32dcSDimitry Andricdefm PseudoVNSRA : VPseudoVNSHT_WV_WX_WI; 6330e8d8bef9SDimitry Andric 6331e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6332bdd1243dSDimitry Andric// 11.8. Vector Integer Comparison Instructions 6333e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63340eae32dcSDimitry Andricdefm PseudoVMSEQ : VPseudoVCMPM_VV_VX_VI; 63350eae32dcSDimitry Andricdefm PseudoVMSNE : VPseudoVCMPM_VV_VX_VI; 63360eae32dcSDimitry Andricdefm PseudoVMSLTU : VPseudoVCMPM_VV_VX; 63370eae32dcSDimitry Andricdefm PseudoVMSLT : VPseudoVCMPM_VV_VX; 63380eae32dcSDimitry Andricdefm PseudoVMSLEU : VPseudoVCMPM_VV_VX_VI; 63390eae32dcSDimitry Andricdefm PseudoVMSLE : VPseudoVCMPM_VV_VX_VI; 63400eae32dcSDimitry Andricdefm PseudoVMSGTU : VPseudoVCMPM_VX_VI; 63410eae32dcSDimitry Andricdefm PseudoVMSGT : VPseudoVCMPM_VX_VI; 6342e8d8bef9SDimitry Andric 6343e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6344bdd1243dSDimitry Andric// 11.9. Vector Integer Min/Max Instructions 6345e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63460eae32dcSDimitry Andricdefm PseudoVMINU : VPseudoVMINMAX_VV_VX; 63470eae32dcSDimitry Andricdefm PseudoVMIN : VPseudoVMINMAX_VV_VX; 63480eae32dcSDimitry Andricdefm PseudoVMAXU : VPseudoVMINMAX_VV_VX; 63490eae32dcSDimitry Andricdefm PseudoVMAX : VPseudoVMINMAX_VV_VX; 6350e8d8bef9SDimitry Andric 6351e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6352bdd1243dSDimitry Andric// 11.10. Vector Single-Width Integer Multiply Instructions 6353e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63540eae32dcSDimitry Andricdefm PseudoVMUL : VPseudoVMUL_VV_VX; 63550eae32dcSDimitry Andricdefm PseudoVMULH : VPseudoVMUL_VV_VX; 63560eae32dcSDimitry Andricdefm PseudoVMULHU : VPseudoVMUL_VV_VX; 63570eae32dcSDimitry Andricdefm PseudoVMULHSU : VPseudoVMUL_VV_VX; 6358e8d8bef9SDimitry Andric 6359e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6360bdd1243dSDimitry Andric// 11.11. Vector Integer Divide Instructions 6361e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63620eae32dcSDimitry Andricdefm PseudoVDIVU : VPseudoVDIV_VV_VX; 63630eae32dcSDimitry Andricdefm PseudoVDIV : VPseudoVDIV_VV_VX; 63640eae32dcSDimitry Andricdefm PseudoVREMU : VPseudoVDIV_VV_VX; 63650eae32dcSDimitry Andricdefm PseudoVREM : VPseudoVDIV_VV_VX; 6366e8d8bef9SDimitry Andric 6367e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6368bdd1243dSDimitry Andric// 11.12. Vector Widening Integer Multiply Instructions 6369e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63700eae32dcSDimitry Andricdefm PseudoVWMUL : VPseudoVWMUL_VV_VX; 63710eae32dcSDimitry Andricdefm PseudoVWMULU : VPseudoVWMUL_VV_VX; 63720eae32dcSDimitry Andricdefm PseudoVWMULSU : VPseudoVWMUL_VV_VX; 6373e8d8bef9SDimitry Andric 6374e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6375bdd1243dSDimitry Andric// 11.13. Vector Single-Width Integer Multiply-Add Instructions 6376e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63770eae32dcSDimitry Andricdefm PseudoVMACC : VPseudoVMAC_VV_VX_AAXA; 63780eae32dcSDimitry Andricdefm PseudoVNMSAC : VPseudoVMAC_VV_VX_AAXA; 63790eae32dcSDimitry Andricdefm PseudoVMADD : VPseudoVMAC_VV_VX_AAXA; 63800eae32dcSDimitry Andricdefm PseudoVNMSUB : VPseudoVMAC_VV_VX_AAXA; 6381e8d8bef9SDimitry Andric 6382e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6383bdd1243dSDimitry Andric// 11.14. Vector Widening Integer Multiply-Add Instructions 6384e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63850eae32dcSDimitry Andricdefm PseudoVWMACCU : VPseudoVWMAC_VV_VX; 63860eae32dcSDimitry Andricdefm PseudoVWMACC : VPseudoVWMAC_VV_VX; 63870eae32dcSDimitry Andricdefm PseudoVWMACCSU : VPseudoVWMAC_VV_VX; 63880eae32dcSDimitry Andricdefm PseudoVWMACCUS : VPseudoVWMAC_VX; 6389e8d8bef9SDimitry Andric 6390e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6391bdd1243dSDimitry Andric// 11.15. Vector Integer Merge Instructions 6392e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63930eae32dcSDimitry Andricdefm PseudoVMERGE : VPseudoVMRG_VM_XM_IM; 6394e8d8bef9SDimitry Andric 6395e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6396bdd1243dSDimitry Andric// 11.16. Vector Integer Move Instructions 6397e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 63980eae32dcSDimitry Andricdefm PseudoVMV_V : VPseudoUnaryVMV_V_X_I; 6399e8d8bef9SDimitry Andric 6400e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6401bdd1243dSDimitry Andric// 12. Vector Fixed-Point Arithmetic Instructions 6402bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 6403bdd1243dSDimitry Andric 6404bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 6405bdd1243dSDimitry Andric// 12.1. Vector Single-Width Saturating Add and Subtract 6406e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6407e8d8bef9SDimitry Andriclet Defs = [VXSAT], hasSideEffects = 1 in { 64080eae32dcSDimitry Andric defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI; 64090eae32dcSDimitry Andric defm PseudoVSADD : VPseudoVSALU_VV_VX_VI; 64100eae32dcSDimitry Andric defm PseudoVSSUBU : VPseudoVSALU_VV_VX; 64110eae32dcSDimitry Andric defm PseudoVSSUB : VPseudoVSALU_VV_VX; 6412e8d8bef9SDimitry Andric} 6413e8d8bef9SDimitry Andric 6414e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6415bdd1243dSDimitry Andric// 12.2. Vector Single-Width Averaging Add and Subtract 6416e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 641706c3fb27SDimitry Andricdefm PseudoVAADDU : VPseudoVAALU_VV_VX_RM; 641806c3fb27SDimitry Andricdefm PseudoVAADD : VPseudoVAALU_VV_VX_RM; 641906c3fb27SDimitry Andricdefm PseudoVASUBU : VPseudoVAALU_VV_VX_RM; 642006c3fb27SDimitry Andricdefm PseudoVASUB : VPseudoVAALU_VV_VX_RM; 6421e8d8bef9SDimitry Andric 6422e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6423bdd1243dSDimitry Andric// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 6424e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 642506c3fb27SDimitry Andriclet Defs = [VXSAT], hasSideEffects = 1 in { 642606c3fb27SDimitry Andric defm PseudoVSMUL : VPseudoVSMUL_VV_VX_RM; 6427e8d8bef9SDimitry Andric} 6428e8d8bef9SDimitry Andric 6429e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6430bdd1243dSDimitry Andric// 12.4. Vector Single-Width Scaling Shift Instructions 6431e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 643206c3fb27SDimitry Andricdefm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI_RM<uimm5>; 643306c3fb27SDimitry Andricdefm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM<uimm5>; 6434e8d8bef9SDimitry Andric 6435e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6436bdd1243dSDimitry Andric// 12.5. Vector Narrowing Fixed-Point Clip Instructions 6437e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 643806c3fb27SDimitry Andriclet Defs = [VXSAT], hasSideEffects = 1 in { 643906c3fb27SDimitry Andric defm PseudoVNCLIP : VPseudoVNCLP_WV_WX_WI_RM; 644006c3fb27SDimitry Andric defm PseudoVNCLIPU : VPseudoVNCLP_WV_WX_WI_RM; 6441e8d8bef9SDimitry Andric} 6442e8d8bef9SDimitry Andric 6443349cc55cSDimitry Andric} // Predicates = [HasVInstructions] 6444e8d8bef9SDimitry Andric 6445bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 6446bdd1243dSDimitry Andric// 13. Vector Floating-Point Instructions 6447bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 6448bdd1243dSDimitry Andric 6449349cc55cSDimitry Andriclet Predicates = [HasVInstructionsAnyF] in { 6450e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6451bdd1243dSDimitry Andric// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 6452e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 645306c3fb27SDimitry Andriclet mayRaiseFPException = true, hasPostISelHook = 1 in { 645406c3fb27SDimitry Andricdefm PseudoVFADD : VPseudoVALU_VV_VF_RM; 645506c3fb27SDimitry Andricdefm PseudoVFSUB : VPseudoVALU_VV_VF_RM; 645606c3fb27SDimitry Andricdefm PseudoVFRSUB : VPseudoVALU_VF_RM; 645781ad6265SDimitry Andric} 6458e8d8bef9SDimitry Andric 6459e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6460bdd1243dSDimitry Andric// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 6461e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 646206c3fb27SDimitry Andriclet mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { 646306c3fb27SDimitry Andricdefm PseudoVFWADD : VPseudoVFWALU_VV_VF_RM; 646406c3fb27SDimitry Andricdefm PseudoVFWSUB : VPseudoVFWALU_VV_VF_RM; 646506c3fb27SDimitry Andricdefm PseudoVFWADD : VPseudoVFWALU_WV_WF_RM; 646606c3fb27SDimitry Andricdefm PseudoVFWSUB : VPseudoVFWALU_WV_WF_RM; 646781ad6265SDimitry Andric} 6468e8d8bef9SDimitry Andric 6469e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6470bdd1243dSDimitry Andric// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 6471e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 647206c3fb27SDimitry Andriclet mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { 647306c3fb27SDimitry Andricdefm PseudoVFMUL : VPseudoVFMUL_VV_VF_RM; 647406c3fb27SDimitry Andricdefm PseudoVFDIV : VPseudoVFDIV_VV_VF_RM; 647506c3fb27SDimitry Andricdefm PseudoVFRDIV : VPseudoVFRDIV_VF_RM; 647681ad6265SDimitry Andric} 6477e8d8bef9SDimitry Andric 6478e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6479bdd1243dSDimitry Andric// 13.5. Vector Widening Floating-Point Multiply 6480e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 648106c3fb27SDimitry Andriclet mayRaiseFPException = true, hasSideEffects = 0 in { 648206c3fb27SDimitry Andricdefm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM; 648381ad6265SDimitry Andric} 6484e8d8bef9SDimitry Andric 6485e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6486bdd1243dSDimitry Andric// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 6487e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 648806c3fb27SDimitry Andriclet mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { 648906c3fb27SDimitry Andricdefm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA_RM; 649006c3fb27SDimitry Andricdefm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA_RM; 649106c3fb27SDimitry Andricdefm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA_RM; 649206c3fb27SDimitry Andricdefm PseudoVFNMSAC : VPseudoVMAC_VV_VF_AAXA_RM; 649306c3fb27SDimitry Andricdefm PseudoVFMADD : VPseudoVMAC_VV_VF_AAXA_RM; 649406c3fb27SDimitry Andricdefm PseudoVFNMADD : VPseudoVMAC_VV_VF_AAXA_RM; 649506c3fb27SDimitry Andricdefm PseudoVFMSUB : VPseudoVMAC_VV_VF_AAXA_RM; 649606c3fb27SDimitry Andricdefm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA_RM; 649781ad6265SDimitry Andric} 6498e8d8bef9SDimitry Andric 6499e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6500bdd1243dSDimitry Andric// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 6501e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 650206c3fb27SDimitry Andriclet mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { 650306c3fb27SDimitry Andricdefm PseudoVFWMACC : VPseudoVWMAC_VV_VF_RM; 650406c3fb27SDimitry Andricdefm PseudoVFWNMACC : VPseudoVWMAC_VV_VF_RM; 650506c3fb27SDimitry Andricdefm PseudoVFWMSAC : VPseudoVWMAC_VV_VF_RM; 650606c3fb27SDimitry Andricdefm PseudoVFWNMSAC : VPseudoVWMAC_VV_VF_RM; 65075f757f3fSDimitry Andriclet Predicates = [HasStdExtZvfbfwma] in 65085f757f3fSDimitry Andricdefm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM; 650981ad6265SDimitry Andric} 6510e8d8bef9SDimitry Andric 6511e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6512bdd1243dSDimitry Andric// 13.8. Vector Floating-Point Square-Root Instruction 6513e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 651406c3fb27SDimitry Andriclet mayRaiseFPException = true, hasSideEffects = 0 in 651506c3fb27SDimitry Andricdefm PseudoVFSQRT : VPseudoVSQR_V_RM; 6516e8d8bef9SDimitry Andric 6517e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6518bdd1243dSDimitry Andric// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 6519e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 652081ad6265SDimitry Andriclet mayRaiseFPException = true in 65210eae32dcSDimitry Andricdefm PseudoVFRSQRT7 : VPseudoVRCP_V; 6522e8d8bef9SDimitry Andric 6523e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6524bdd1243dSDimitry Andric// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 6525e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 652606c3fb27SDimitry Andriclet mayRaiseFPException = true, hasSideEffects = 0 in 652706c3fb27SDimitry Andricdefm PseudoVFREC7 : VPseudoVRCP_V_RM; 6528e8d8bef9SDimitry Andric 6529e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6530bdd1243dSDimitry Andric// 13.11. Vector Floating-Point Min/Max Instructions 6531e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 653281ad6265SDimitry Andriclet mayRaiseFPException = true in { 65330eae32dcSDimitry Andricdefm PseudoVFMIN : VPseudoVMAX_VV_VF; 65340eae32dcSDimitry Andricdefm PseudoVFMAX : VPseudoVMAX_VV_VF; 653581ad6265SDimitry Andric} 6536e8d8bef9SDimitry Andric 6537e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6538bdd1243dSDimitry Andric// 13.12. Vector Floating-Point Sign-Injection Instructions 6539e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 65400eae32dcSDimitry Andricdefm PseudoVFSGNJ : VPseudoVSGNJ_VV_VF; 65410eae32dcSDimitry Andricdefm PseudoVFSGNJN : VPseudoVSGNJ_VV_VF; 65420eae32dcSDimitry Andricdefm PseudoVFSGNJX : VPseudoVSGNJ_VV_VF; 6543e8d8bef9SDimitry Andric 6544e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6545bdd1243dSDimitry Andric// 13.13. Vector Floating-Point Compare Instructions 6546e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 654781ad6265SDimitry Andriclet mayRaiseFPException = true in { 65480eae32dcSDimitry Andricdefm PseudoVMFEQ : VPseudoVCMPM_VV_VF; 65490eae32dcSDimitry Andricdefm PseudoVMFNE : VPseudoVCMPM_VV_VF; 65500eae32dcSDimitry Andricdefm PseudoVMFLT : VPseudoVCMPM_VV_VF; 65510eae32dcSDimitry Andricdefm PseudoVMFLE : VPseudoVCMPM_VV_VF; 65520eae32dcSDimitry Andricdefm PseudoVMFGT : VPseudoVCMPM_VF; 65530eae32dcSDimitry Andricdefm PseudoVMFGE : VPseudoVCMPM_VF; 655481ad6265SDimitry Andric} 6555e8d8bef9SDimitry Andric 6556e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6557bdd1243dSDimitry Andric// 13.14. Vector Floating-Point Classify Instruction 6558e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 65590eae32dcSDimitry Andricdefm PseudoVFCLASS : VPseudoVCLS_V; 6560e8d8bef9SDimitry Andric 6561e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6562bdd1243dSDimitry Andric// 13.15. Vector Floating-Point Merge Instruction 6563e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 65640eae32dcSDimitry Andricdefm PseudoVFMERGE : VPseudoVMRG_FM; 6565e8d8bef9SDimitry Andric 6566e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6567bdd1243dSDimitry Andric// 13.16. Vector Floating-Point Move Instruction 6568e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 65690eae32dcSDimitry Andricdefm PseudoVFMV_V : VPseudoVMV_F; 6570e8d8bef9SDimitry Andric 6571e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6572bdd1243dSDimitry Andric// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 6573e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6574bdd1243dSDimitry Andriclet mayRaiseFPException = true in { 657506c3fb27SDimitry Andriclet hasSideEffects = 0, hasPostISelHook = 1 in { 657606c3fb27SDimitry Andricdefm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM; 657706c3fb27SDimitry Andricdefm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM; 6578bdd1243dSDimitry Andric} 6579bdd1243dSDimitry Andric 6580bdd1243dSDimitry Andricdefm PseudoVFCVT_RM_XU_F : VPseudoVCVTI_RM_V; 6581bdd1243dSDimitry Andricdefm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V; 6582bdd1243dSDimitry Andric 65830eae32dcSDimitry Andricdefm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V; 65840eae32dcSDimitry Andricdefm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V; 6585bdd1243dSDimitry Andric 6586bdd1243dSDimitry Andricdefm PseudoVFROUND_NOEXCEPT : VPseudoVFROUND_NOEXCEPT_V; 658706c3fb27SDimitry Andriclet hasSideEffects = 0, hasPostISelHook = 1 in { 658806c3fb27SDimitry Andricdefm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM; 658906c3fb27SDimitry Andricdefm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM; 6590bdd1243dSDimitry Andric} 6591bdd1243dSDimitry Andricdefm PseudoVFCVT_RM_F_XU : VPseudoVCVTF_RM_V; 6592bdd1243dSDimitry Andricdefm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V; 6593bdd1243dSDimitry Andric} // mayRaiseFPException = true 6594e8d8bef9SDimitry Andric 6595e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6596bdd1243dSDimitry Andric// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 6597e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6598bdd1243dSDimitry Andriclet mayRaiseFPException = true in { 659906c3fb27SDimitry Andriclet hasSideEffects = 0, hasPostISelHook = 1 in { 660006c3fb27SDimitry Andricdefm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM; 660106c3fb27SDimitry Andricdefm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM; 6602bdd1243dSDimitry Andric} 6603bdd1243dSDimitry Andricdefm PseudoVFWCVT_RM_XU_F : VPseudoVWCVTI_RM_V; 6604bdd1243dSDimitry Andricdefm PseudoVFWCVT_RM_X_F : VPseudoVWCVTI_RM_V; 6605bdd1243dSDimitry Andric 66060eae32dcSDimitry Andricdefm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V; 66070eae32dcSDimitry Andricdefm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V; 6608bdd1243dSDimitry Andric 66090eae32dcSDimitry Andricdefm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V; 66100eae32dcSDimitry Andricdefm PseudoVFWCVT_F_X : VPseudoVWCVTF_V; 6611bdd1243dSDimitry Andric 66120eae32dcSDimitry Andricdefm PseudoVFWCVT_F_F : VPseudoVWCVTD_V; 66135f757f3fSDimitry Andricdefm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V; 6614bdd1243dSDimitry Andric} // mayRaiseFPException = true 6615e8d8bef9SDimitry Andric 6616e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6617bdd1243dSDimitry Andric// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 6618e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6619bdd1243dSDimitry Andriclet mayRaiseFPException = true in { 662006c3fb27SDimitry Andriclet hasSideEffects = 0, hasPostISelHook = 1 in { 662106c3fb27SDimitry Andricdefm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM; 662206c3fb27SDimitry Andricdefm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM; 6623bdd1243dSDimitry Andric} 6624bdd1243dSDimitry Andricdefm PseudoVFNCVT_RM_XU_F : VPseudoVNCVTI_RM_W; 6625bdd1243dSDimitry Andricdefm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W; 6626bdd1243dSDimitry Andric 66270eae32dcSDimitry Andricdefm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W; 66280eae32dcSDimitry Andricdefm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W; 6629bdd1243dSDimitry Andric 663006c3fb27SDimitry Andriclet hasSideEffects = 0, hasPostISelHook = 1 in { 663106c3fb27SDimitry Andricdefm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM; 663206c3fb27SDimitry Andricdefm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM; 6633bdd1243dSDimitry Andric} 6634bdd1243dSDimitry Andricdefm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W; 6635bdd1243dSDimitry Andricdefm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W; 6636bdd1243dSDimitry Andric 663706c3fb27SDimitry Andriclet hasSideEffects = 0, hasPostISelHook = 1 in 663806c3fb27SDimitry Andricdefm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM; 66395f757f3fSDimitry Andricdefm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM; 6640bdd1243dSDimitry Andric 66410eae32dcSDimitry Andricdefm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W; 6642bdd1243dSDimitry Andric} // mayRaiseFPException = true 6643349cc55cSDimitry Andric} // Predicates = [HasVInstructionsAnyF] 6644e8d8bef9SDimitry Andric 6645bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 6646bdd1243dSDimitry Andric// 14. Vector Reduction Operations 6647bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 6648bdd1243dSDimitry Andric 6649349cc55cSDimitry Andriclet Predicates = [HasVInstructions] in { 6650e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6651bdd1243dSDimitry Andric// 14.1. Vector Single-Width Integer Reduction Instructions 6652e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 66530eae32dcSDimitry Andricdefm PseudoVREDSUM : VPseudoVRED_VS; 66540eae32dcSDimitry Andricdefm PseudoVREDAND : VPseudoVRED_VS; 66550eae32dcSDimitry Andricdefm PseudoVREDOR : VPseudoVRED_VS; 66560eae32dcSDimitry Andricdefm PseudoVREDXOR : VPseudoVRED_VS; 665706c3fb27SDimitry Andricdefm PseudoVREDMINU : VPseudoVREDMINMAX_VS; 665806c3fb27SDimitry Andricdefm PseudoVREDMIN : VPseudoVREDMINMAX_VS; 665906c3fb27SDimitry Andricdefm PseudoVREDMAXU : VPseudoVREDMINMAX_VS; 666006c3fb27SDimitry Andricdefm PseudoVREDMAX : VPseudoVREDMINMAX_VS; 6661e8d8bef9SDimitry Andric 6662e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6663bdd1243dSDimitry Andric// 14.2. Vector Widening Integer Reduction Instructions 6664e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6665349cc55cSDimitry Andriclet IsRVVWideningReduction = 1 in { 66660eae32dcSDimitry Andricdefm PseudoVWREDSUMU : VPseudoVWRED_VS; 66670eae32dcSDimitry Andricdefm PseudoVWREDSUM : VPseudoVWRED_VS; 6668349cc55cSDimitry Andric} 6669349cc55cSDimitry Andric} // Predicates = [HasVInstructions] 6670e8d8bef9SDimitry Andric 6671349cc55cSDimitry Andriclet Predicates = [HasVInstructionsAnyF] in { 6672e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6673bdd1243dSDimitry Andric// 14.3. Vector Single-Width Floating-Point Reduction Instructions 6674e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 667506c3fb27SDimitry Andriclet mayRaiseFPException = true, 667606c3fb27SDimitry Andric hasSideEffects = 0 in { 667706c3fb27SDimitry Andricdefm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM; 667806c3fb27SDimitry Andricdefm PseudoVFREDUSUM : VPseudoVFRED_VS_RM; 667981ad6265SDimitry Andric} 668081ad6265SDimitry Andriclet mayRaiseFPException = true in { 668106c3fb27SDimitry Andricdefm PseudoVFREDMIN : VPseudoVFREDMINMAX_VS; 668206c3fb27SDimitry Andricdefm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS; 668381ad6265SDimitry Andric} 6684e8d8bef9SDimitry Andric 6685e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6686bdd1243dSDimitry Andric// 14.4. Vector Widening Floating-Point Reduction Instructions 6687e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 668881ad6265SDimitry Andriclet IsRVVWideningReduction = 1, 668906c3fb27SDimitry Andric hasSideEffects = 0, 669081ad6265SDimitry Andric mayRaiseFPException = true in { 669106c3fb27SDimitry Andricdefm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM; 66925f757f3fSDimitry Andricdefm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM; 6693349cc55cSDimitry Andric} 6694e8d8bef9SDimitry Andric 6695349cc55cSDimitry Andric} // Predicates = [HasVInstructionsAnyF] 6696e8d8bef9SDimitry Andric 6697e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6698bdd1243dSDimitry Andric// 15. Vector Mask Instructions 6699e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6700e8d8bef9SDimitry Andric 6701e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6702bdd1243dSDimitry Andric// 15.1 Vector Mask-Register Logical Instructions 6703e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6704e8d8bef9SDimitry Andric 67055f757f3fSDimitry Andricdefm PseudoVMAND: VPseudoVALU_MM<Commutable=1>; 67065f757f3fSDimitry Andricdefm PseudoVMNAND: VPseudoVALU_MM<Commutable=1>; 67070eae32dcSDimitry Andricdefm PseudoVMANDN: VPseudoVALU_MM; 67085f757f3fSDimitry Andricdefm PseudoVMXOR: VPseudoVALU_MM<Commutable=1>; 67095f757f3fSDimitry Andricdefm PseudoVMOR: VPseudoVALU_MM<Commutable=1>; 67105f757f3fSDimitry Andricdefm PseudoVMNOR: VPseudoVALU_MM<Commutable=1>; 67110eae32dcSDimitry Andricdefm PseudoVMORN: VPseudoVALU_MM; 67125f757f3fSDimitry Andricdefm PseudoVMXNOR: VPseudoVALU_MM<Commutable=1>; 6713e8d8bef9SDimitry Andric 6714fe6060f1SDimitry Andric// Pseudo instructions 6715bdd1243dSDimitry Andricdefm PseudoVMCLR : VPseudoNullaryPseudoM<"VMXOR">; 6716bdd1243dSDimitry Andricdefm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">; 6717e8d8bef9SDimitry Andric 6718e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6719bdd1243dSDimitry Andric// 15.2. Vector mask population count vcpop 6720e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6721e8d8bef9SDimitry Andric 67221db9f3b2SDimitry Andriclet IsSignExtendingOpW = 1 in 67230eae32dcSDimitry Andricdefm PseudoVCPOP: VPseudoVPOP_M; 6724e8d8bef9SDimitry Andric 6725e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6726bdd1243dSDimitry Andric// 15.3. vfirst find-first-set mask bit 6727e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6728e8d8bef9SDimitry Andric 67291db9f3b2SDimitry Andriclet IsSignExtendingOpW = 1 in 67300eae32dcSDimitry Andricdefm PseudoVFIRST: VPseudoV1ST_M; 6731e8d8bef9SDimitry Andric 6732e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6733bdd1243dSDimitry Andric// 15.4. vmsbf.m set-before-first mask bit 6734e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 67350eae32dcSDimitry Andricdefm PseudoVMSBF: VPseudoVSFS_M; 6736e8d8bef9SDimitry Andric 6737e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6738bdd1243dSDimitry Andric// 15.5. vmsif.m set-including-first mask bit 6739e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 67400eae32dcSDimitry Andricdefm PseudoVMSIF: VPseudoVSFS_M; 6741e8d8bef9SDimitry Andric 6742e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6743bdd1243dSDimitry Andric// 15.6. vmsof.m set-only-first mask bit 6744e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 67450eae32dcSDimitry Andricdefm PseudoVMSOF: VPseudoVSFS_M; 6746e8d8bef9SDimitry Andric 6747e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6748bdd1243dSDimitry Andric// 15.8. Vector Iota Instruction 6749e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 67500eae32dcSDimitry Andricdefm PseudoVIOTA_M: VPseudoVIOT_M; 6751e8d8bef9SDimitry Andric 6752e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6753bdd1243dSDimitry Andric// 15.9. Vector Element Index Instruction 6754e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 67550eae32dcSDimitry Andricdefm PseudoVID : VPseudoVID_V; 6756e8d8bef9SDimitry Andric 6757e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6758bdd1243dSDimitry Andric// 16. Vector Permutation Instructions 6759e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6760e8d8bef9SDimitry Andric 6761e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6762bdd1243dSDimitry Andric// 16.1. Integer Scalar Move Instructions 6763e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6764e8d8bef9SDimitry Andric 6765349cc55cSDimitry Andriclet Predicates = [HasVInstructions] in { 6766fe6060f1SDimitry Andriclet mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 6767e8d8bef9SDimitry Andric let HasSEWOp = 1, BaseInstr = VMV_X_S in 6768*7a6dacacSDimitry Andric def PseudoVMV_X_S: 6769*7a6dacacSDimitry Andric Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>, 677006c3fb27SDimitry Andric Sched<[WriteVIMovVX, ReadVIMovVX]>, 67710eae32dcSDimitry Andric RISCVVPseudo; 6772fe6060f1SDimitry Andric let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, 6773e8d8bef9SDimitry Andric Constraints = "$rd = $rs1" in 6774*7a6dacacSDimitry Andric def PseudoVMV_S_X: Pseudo<(outs VR:$rd), 6775*7a6dacacSDimitry Andric (ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew), 67760eae32dcSDimitry Andric []>, 677706c3fb27SDimitry Andric Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>, 67780eae32dcSDimitry Andric RISCVVPseudo; 6779e8d8bef9SDimitry Andric} 6780349cc55cSDimitry Andric} // Predicates = [HasVInstructions] 6781e8d8bef9SDimitry Andric 6782e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6783bdd1243dSDimitry Andric// 16.2. Floating-Point Scalar Move Instructions 6784e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6785e8d8bef9SDimitry Andric 6786349cc55cSDimitry Andriclet Predicates = [HasVInstructionsAnyF] in { 6787fe6060f1SDimitry Andriclet mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 678804eeddc0SDimitry Andric foreach f = FPList in { 678904eeddc0SDimitry Andric foreach m = f.MxList in { 6790bdd1243dSDimitry Andric defvar mx = m.MX; 6791e8d8bef9SDimitry Andric let VLMul = m.value in { 6792e8d8bef9SDimitry Andric let HasSEWOp = 1, BaseInstr = VFMV_F_S in 6793bdd1243dSDimitry Andric def "PseudoVFMV_" # f.FX # "_S_" # mx : 6794e8d8bef9SDimitry Andric Pseudo<(outs f.fprclass:$rd), 67950eae32dcSDimitry Andric (ins m.vrclass:$rs2, ixlenimm:$sew), []>, 679606c3fb27SDimitry Andric Sched<[WriteVFMovVF, ReadVFMovVF]>, 67970eae32dcSDimitry Andric RISCVVPseudo; 6798fe6060f1SDimitry Andric let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, 6799e8d8bef9SDimitry Andric Constraints = "$rd = $rs1" in 6800bdd1243dSDimitry Andric def "PseudoVFMV_S_" # f.FX # "_" # mx : 6801e8d8bef9SDimitry Andric Pseudo<(outs m.vrclass:$rd), 6802e8d8bef9SDimitry Andric (ins m.vrclass:$rs1, f.fprclass:$rs2, 6803fe6060f1SDimitry Andric AVL:$vl, ixlenimm:$sew), 68040eae32dcSDimitry Andric []>, 680506c3fb27SDimitry Andric Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>, 68060eae32dcSDimitry Andric RISCVVPseudo; 6807e8d8bef9SDimitry Andric } 6808e8d8bef9SDimitry Andric } 6809e8d8bef9SDimitry Andric } 6810e8d8bef9SDimitry Andric} 6811349cc55cSDimitry Andric} // Predicates = [HasVInstructionsAnyF] 6812e8d8bef9SDimitry Andric 6813e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6814bdd1243dSDimitry Andric// 16.3. Vector Slide Instructions 6815e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6816349cc55cSDimitry Andriclet Predicates = [HasVInstructions] in { 68170eae32dcSDimitry Andric defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI<uimm5, "@earlyclobber $rd">; 68180eae32dcSDimitry Andric defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI<uimm5>; 68190eae32dcSDimitry Andric defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">; 68200eae32dcSDimitry Andric defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX; 6821349cc55cSDimitry Andric} // Predicates = [HasVInstructions] 6822e8d8bef9SDimitry Andric 6823349cc55cSDimitry Andriclet Predicates = [HasVInstructionsAnyF] in { 68240eae32dcSDimitry Andric defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF<"@earlyclobber $rd">; 68250eae32dcSDimitry Andric defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF; 6826349cc55cSDimitry Andric} // Predicates = [HasVInstructionsAnyF] 6827e8d8bef9SDimitry Andric 6828e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6829bdd1243dSDimitry Andric// 16.4. Vector Register Gather Instructions 6830e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 68310eae32dcSDimitry Andricdefm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<uimm5, "@earlyclobber $rd">; 683206c3fb27SDimitry Andricdefm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW<eew=16, 683306c3fb27SDimitry Andric Constraint="@earlyclobber $rd">; 6834e8d8bef9SDimitry Andric 6835e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6836bdd1243dSDimitry Andric// 16.5. Vector Compress Instruction 6837e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 68380eae32dcSDimitry Andricdefm PseudoVCOMPRESS : VPseudoVCPR_V; 6839e8d8bef9SDimitry Andric 6840e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6841e8d8bef9SDimitry Andric// Patterns. 6842e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6843e8d8bef9SDimitry Andric 6844e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6845bdd1243dSDimitry Andric// 11. Vector Integer Arithmetic Instructions 6846e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6847e8d8bef9SDimitry Andric 6848e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6849bdd1243dSDimitry Andric// 11.1. Vector Single-Width Integer Add and Subtract 6850e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6851fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vadd", "PseudoVADD", AllIntegerVectors>; 6852fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vsub", "PseudoVSUB", AllIntegerVectors>; 6853fe6060f1SDimitry Andricdefm : VPatBinaryV_VX_VI<"int_riscv_vrsub", "PseudoVRSUB", AllIntegerVectors>; 6854e8d8bef9SDimitry Andric 6855e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6856bdd1243dSDimitry Andric// 11.2. Vector Widening Integer Add/Subtract 6857e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6858fe6060f1SDimitry Andricdefm : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU", AllWidenableIntVectors>; 6859fe6060f1SDimitry Andricdefm : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU", AllWidenableIntVectors>; 6860fe6060f1SDimitry Andricdefm : VPatBinaryW_VV_VX<"int_riscv_vwadd", "PseudoVWADD", AllWidenableIntVectors>; 6861fe6060f1SDimitry Andricdefm : VPatBinaryW_VV_VX<"int_riscv_vwsub", "PseudoVWSUB", AllWidenableIntVectors>; 6862fe6060f1SDimitry Andricdefm : VPatBinaryW_WV_WX<"int_riscv_vwaddu_w", "PseudoVWADDU", AllWidenableIntVectors>; 6863fe6060f1SDimitry Andricdefm : VPatBinaryW_WV_WX<"int_riscv_vwsubu_w", "PseudoVWSUBU", AllWidenableIntVectors>; 6864fe6060f1SDimitry Andricdefm : VPatBinaryW_WV_WX<"int_riscv_vwadd_w", "PseudoVWADD", AllWidenableIntVectors>; 6865fe6060f1SDimitry Andricdefm : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB", AllWidenableIntVectors>; 6866e8d8bef9SDimitry Andric 6867e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6868bdd1243dSDimitry Andric// 11.3. Vector Integer Extension 6869e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6870fe6060f1SDimitry Andricdefm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF2", 6871e8d8bef9SDimitry Andric AllFractionableVF2IntVectors>; 6872fe6060f1SDimitry Andricdefm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF4", 6873e8d8bef9SDimitry Andric AllFractionableVF4IntVectors>; 6874fe6060f1SDimitry Andricdefm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF8", 6875e8d8bef9SDimitry Andric AllFractionableVF8IntVectors>; 6876fe6060f1SDimitry Andricdefm : VPatUnaryV_VF<"int_riscv_vsext", "PseudoVSEXT", "VF2", 6877e8d8bef9SDimitry Andric AllFractionableVF2IntVectors>; 6878fe6060f1SDimitry Andricdefm : VPatUnaryV_VF<"int_riscv_vsext", "PseudoVSEXT", "VF4", 6879e8d8bef9SDimitry Andric AllFractionableVF4IntVectors>; 6880fe6060f1SDimitry Andricdefm : VPatUnaryV_VF<"int_riscv_vsext", "PseudoVSEXT", "VF8", 6881e8d8bef9SDimitry Andric AllFractionableVF8IntVectors>; 6882e8d8bef9SDimitry Andric 6883e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6884bdd1243dSDimitry Andric// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions 6885e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6886fe6060f1SDimitry Andricdefm : VPatBinaryV_VM_XM_IM<"int_riscv_vadc", "PseudoVADC">; 6887fe6060f1SDimitry Andricdefm : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">; 6888fe6060f1SDimitry Andricdefm : VPatBinaryM_V_X_I<"int_riscv_vmadc", "PseudoVMADC">; 6889e8d8bef9SDimitry Andric 6890fe6060f1SDimitry Andricdefm : VPatBinaryV_VM_XM<"int_riscv_vsbc", "PseudoVSBC">; 6891fe6060f1SDimitry Andricdefm : VPatBinaryM_VM_XM<"int_riscv_vmsbc_borrow_in", "PseudoVMSBC">; 6892fe6060f1SDimitry Andricdefm : VPatBinaryM_V_X<"int_riscv_vmsbc", "PseudoVMSBC">; 6893e8d8bef9SDimitry Andric 6894e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6895bdd1243dSDimitry Andric// 11.5. Vector Bitwise Logical Instructions 6896e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6897fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vand", "PseudoVAND", AllIntegerVectors>; 6898fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vor", "PseudoVOR", AllIntegerVectors>; 6899fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vxor", "PseudoVXOR", AllIntegerVectors>; 6900e8d8bef9SDimitry Andric 6901e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6902bdd1243dSDimitry Andric// 11.6. Vector Single-Width Bit Shift Instructions 6903e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6904fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors, 6905e8d8bef9SDimitry Andric uimm5>; 6906fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors, 6907e8d8bef9SDimitry Andric uimm5>; 6908fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors, 6909e8d8bef9SDimitry Andric uimm5>; 6910e8d8bef9SDimitry Andric 691104eeddc0SDimitry Andricforeach vti = AllIntegerVectors in { 691204eeddc0SDimitry Andric // Emit shift by 1 as an add since it might be faster. 691306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 691481ad6265SDimitry Andric def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector undef), 691581ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs1), 691604eeddc0SDimitry Andric (XLenVT 1), VLOpFrag)), 691706c3fb27SDimitry Andric (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX) 691806c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, 69195f757f3fSDimitry Andric vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>; 692004eeddc0SDimitry Andric def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$merge), 692104eeddc0SDimitry Andric (vti.Vector vti.RegClass:$rs1), 692204eeddc0SDimitry Andric (XLenVT 1), 692304eeddc0SDimitry Andric (vti.Mask V0), 692404eeddc0SDimitry Andric VLOpFrag, 692504eeddc0SDimitry Andric (XLenVT timm:$policy))), 692604eeddc0SDimitry Andric (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX#"_MASK") 692704eeddc0SDimitry Andric vti.RegClass:$merge, 692804eeddc0SDimitry Andric vti.RegClass:$rs1, 692904eeddc0SDimitry Andric vti.RegClass:$rs1, 693004eeddc0SDimitry Andric (vti.Mask V0), 693104eeddc0SDimitry Andric GPR:$vl, 693204eeddc0SDimitry Andric vti.Log2SEW, 693304eeddc0SDimitry Andric (XLenVT timm:$policy))>; 693404eeddc0SDimitry Andric } 693506c3fb27SDimitry Andric} 693604eeddc0SDimitry Andric 6937e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6938bdd1243dSDimitry Andric// 11.7. Vector Narrowing Integer Right Shift Instructions 6939e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6940fe6060f1SDimitry Andricdefm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>; 6941fe6060f1SDimitry Andricdefm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>; 6942e8d8bef9SDimitry Andric 6943e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6944bdd1243dSDimitry Andric// 11.8. Vector Integer Comparison Instructions 6945e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6946fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX_VI<"int_riscv_vmseq", "PseudoVMSEQ", AllIntegerVectors>; 6947fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX_VI<"int_riscv_vmsne", "PseudoVMSNE", AllIntegerVectors>; 6948fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX<"int_riscv_vmsltu", "PseudoVMSLTU", AllIntegerVectors>; 6949fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX<"int_riscv_vmslt", "PseudoVMSLT", AllIntegerVectors>; 6950fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX_VI<"int_riscv_vmsleu", "PseudoVMSLEU", AllIntegerVectors>; 6951fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX_VI<"int_riscv_vmsle", "PseudoVMSLE", AllIntegerVectors>; 6952e8d8bef9SDimitry Andric 6953fe6060f1SDimitry Andricdefm : VPatBinaryM_VX_VI<"int_riscv_vmsgtu", "PseudoVMSGTU", AllIntegerVectors>; 6954fe6060f1SDimitry Andricdefm : VPatBinaryM_VX_VI<"int_riscv_vmsgt", "PseudoVMSGT", AllIntegerVectors>; 6955fe6060f1SDimitry Andric 6956fe6060f1SDimitry Andric// Match vmsgt with 2 vector operands to vmslt with the operands swapped. 6957fe6060f1SDimitry Andricdefm : VPatBinarySwappedM_VV<"int_riscv_vmsgtu", "PseudoVMSLTU", AllIntegerVectors>; 6958fe6060f1SDimitry Andricdefm : VPatBinarySwappedM_VV<"int_riscv_vmsgt", "PseudoVMSLT", AllIntegerVectors>; 6959fe6060f1SDimitry Andric 6960fe6060f1SDimitry Andricdefm : VPatBinarySwappedM_VV<"int_riscv_vmsgeu", "PseudoVMSLEU", AllIntegerVectors>; 6961fe6060f1SDimitry Andricdefm : VPatBinarySwappedM_VV<"int_riscv_vmsge", "PseudoVMSLE", AllIntegerVectors>; 6962e8d8bef9SDimitry Andric 69631fd87a68SDimitry Andric// Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16 and 69641fd87a68SDimitry Andric// non-zero. Zero can be .vx with x0. This avoids the user needing to know that 69651fd87a68SDimitry Andric// there is no vmslt(u).vi instruction. Similar for vmsge(u).vx intrinsics 69661fd87a68SDimitry Andric// using vmslt(u).vi. 69671fd87a68SDimitry Andricdefm : VPatCompare_VI<"int_riscv_vmslt", "PseudoVMSLE", simm5_plus1_nonzero>; 696804eeddc0SDimitry Andricdefm : VPatCompare_VI<"int_riscv_vmsltu", "PseudoVMSLEU", simm5_plus1_nonzero>; 6969e8d8bef9SDimitry Andric 69701fd87a68SDimitry Andric// We need to handle 0 for vmsge.vi using vmslt.vi because there is no vmsge.vx. 69711fd87a68SDimitry Andricdefm : VPatCompare_VI<"int_riscv_vmsge", "PseudoVMSGT", simm5_plus1>; 697204eeddc0SDimitry Andricdefm : VPatCompare_VI<"int_riscv_vmsgeu", "PseudoVMSGTU", simm5_plus1_nonzero>; 6973e8d8bef9SDimitry Andric 6974e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6975bdd1243dSDimitry Andric// 11.9. Vector Integer Min/Max Instructions 6976e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6977fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vminu", "PseudoVMINU", AllIntegerVectors>; 6978fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vmin", "PseudoVMIN", AllIntegerVectors>; 6979fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vmaxu", "PseudoVMAXU", AllIntegerVectors>; 6980fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vmax", "PseudoVMAX", AllIntegerVectors>; 6981e8d8bef9SDimitry Andric 6982e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6983bdd1243dSDimitry Andric// 11.10. Vector Single-Width Integer Multiply Instructions 6984e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 6985fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vmul", "PseudoVMUL", AllIntegerVectors>; 698606c3fb27SDimitry Andric 698706c3fb27SDimitry Andricdefvar IntegerVectorsExceptI64 = !filter(vti, AllIntegerVectors, 698806c3fb27SDimitry Andric !ne(vti.SEW, 64)); 698906c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vmulh", "PseudoVMULH", 699006c3fb27SDimitry Andric IntegerVectorsExceptI64>; 699106c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vmulhu", "PseudoVMULHU", 699206c3fb27SDimitry Andric IntegerVectorsExceptI64>; 699306c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vmulhsu", "PseudoVMULHSU", 699406c3fb27SDimitry Andric IntegerVectorsExceptI64>; 699506c3fb27SDimitry Andric 699606c3fb27SDimitry Andric// vmulh, vmulhu, vmulhsu are not included for EEW=64 in Zve64*. 699706c3fb27SDimitry Andricdefvar I64IntegerVectors = !filter(vti, AllIntegerVectors, !eq(vti.SEW, 64)); 699806c3fb27SDimitry Andriclet Predicates = [HasVInstructionsFullMultiply] in { 699906c3fb27SDimitry Andric defm : VPatBinaryV_VV_VX<"int_riscv_vmulh", "PseudoVMULH", 700006c3fb27SDimitry Andric I64IntegerVectors>; 700106c3fb27SDimitry Andric defm : VPatBinaryV_VV_VX<"int_riscv_vmulhu", "PseudoVMULHU", 700206c3fb27SDimitry Andric I64IntegerVectors>; 700306c3fb27SDimitry Andric defm : VPatBinaryV_VV_VX<"int_riscv_vmulhsu", "PseudoVMULHSU", 700406c3fb27SDimitry Andric I64IntegerVectors>; 700506c3fb27SDimitry Andric} 7006e8d8bef9SDimitry Andric 7007e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7008bdd1243dSDimitry Andric// 11.11. Vector Integer Divide Instructions 7009e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 701006c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors, isSEWAware=1>; 701106c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors, isSEWAware=1>; 701206c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors, isSEWAware=1>; 701306c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors, isSEWAware=1>; 7014e8d8bef9SDimitry Andric 7015e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7016bdd1243dSDimitry Andric// 11.12. Vector Widening Integer Multiply Instructions 7017e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7018fe6060f1SDimitry Andricdefm : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL", AllWidenableIntVectors>; 7019fe6060f1SDimitry Andricdefm : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU", AllWidenableIntVectors>; 7020fe6060f1SDimitry Andricdefm : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU", AllWidenableIntVectors>; 7021e8d8bef9SDimitry Andric 7022e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7023bdd1243dSDimitry Andric// 11.13. Vector Single-Width Integer Multiply-Add Instructions 7024e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7025fe6060f1SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vmadd", "PseudoVMADD", AllIntegerVectors>; 7026fe6060f1SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsub", "PseudoVNMSUB", AllIntegerVectors>; 7027fe6060f1SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vmacc", "PseudoVMACC", AllIntegerVectors>; 7028fe6060f1SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsac", "PseudoVNMSAC", AllIntegerVectors>; 7029e8d8bef9SDimitry Andric 7030e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7031bdd1243dSDimitry Andric// 11.14. Vector Widening Integer Multiply-Add Instructions 7032e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7033fe6060f1SDimitry Andricdefm : VPatTernaryW_VV_VX<"int_riscv_vwmaccu", "PseudoVWMACCU", AllWidenableIntVectors>; 7034fe6060f1SDimitry Andricdefm : VPatTernaryW_VV_VX<"int_riscv_vwmacc", "PseudoVWMACC", AllWidenableIntVectors>; 7035fe6060f1SDimitry Andricdefm : VPatTernaryW_VV_VX<"int_riscv_vwmaccsu", "PseudoVWMACCSU", AllWidenableIntVectors>; 7036fe6060f1SDimitry Andricdefm : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>; 7037e8d8bef9SDimitry Andric 7038e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7039bdd1243dSDimitry Andric// 11.15. Vector Integer Merge Instructions 7040e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7041fe6060f1SDimitry Andricdefm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">; 7042e8d8bef9SDimitry Andric 7043e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7044bdd1243dSDimitry Andric// 11.16. Vector Integer Move Instructions 7045e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7046e8d8bef9SDimitry Andricforeach vti = AllVectors in { 704706c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 704881ad6265SDimitry Andric def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$passthru), 704981ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs1), 705081ad6265SDimitry Andric VLOpFrag)), 705106c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX) 705206c3fb27SDimitry Andric $passthru, $rs1, GPR:$vl, vti.Log2SEW, TU_MU)>; 7053e8d8bef9SDimitry Andric 7054fe6060f1SDimitry Andric // vmv.v.x/vmv.v.i are handled in RISCInstrVInstrInfoVVLPatterns.td 7055e8d8bef9SDimitry Andric } 705606c3fb27SDimitry Andric} 7057e8d8bef9SDimitry Andric 7058e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7059bdd1243dSDimitry Andric// 12. Vector Fixed-Point Arithmetic Instructions 7060bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 7061bdd1243dSDimitry Andric 7062bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 7063bdd1243dSDimitry Andric// 12.1. Vector Single-Width Saturating Add and Subtract 7064e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7065fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vsaddu", "PseudoVSADDU", AllIntegerVectors>; 7066fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vsadd", "PseudoVSADD", AllIntegerVectors>; 7067fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vssubu", "PseudoVSSUBU", AllIntegerVectors>; 7068fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vssub", "PseudoVSSUB", AllIntegerVectors>; 7069e8d8bef9SDimitry Andric 7070e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7071bdd1243dSDimitry Andric// 12.2. Vector Single-Width Averaging Add and Subtract 7072e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 707306c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vaaddu", "PseudoVAADDU", 707406c3fb27SDimitry Andric AllIntegerVectors>; 707506c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vasubu", "PseudoVASUBU", 707606c3fb27SDimitry Andric AllIntegerVectors>; 707706c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vasub", "PseudoVASUB", 707806c3fb27SDimitry Andric AllIntegerVectors>; 707906c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vaadd", "PseudoVAADD", 708006c3fb27SDimitry Andric AllIntegerVectors>; 7081e8d8bef9SDimitry Andric 7082e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7083bdd1243dSDimitry Andric// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 7084e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 708506c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vsmul", "PseudoVSMUL", 708606c3fb27SDimitry Andric IntegerVectorsExceptI64>; 708706c3fb27SDimitry Andric// vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*. 708806c3fb27SDimitry Andriclet Predicates = [HasVInstructionsFullMultiply] in 708906c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vsmul", "PseudoVSMUL", 709006c3fb27SDimitry Andric I64IntegerVectors>; 7091e8d8bef9SDimitry Andric 7092e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7093bdd1243dSDimitry Andric// 12.4. Vector Single-Width Scaling Shift Instructions 7094e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 709506c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_VI_RM<"int_riscv_vssrl", "PseudoVSSRL", 709606c3fb27SDimitry Andric AllIntegerVectors, uimm5>; 709706c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_VI_RM<"int_riscv_vssra", "PseudoVSSRA", 709806c3fb27SDimitry Andric AllIntegerVectors, uimm5>; 7099e8d8bef9SDimitry Andric 7100e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7101bdd1243dSDimitry Andric// 12.5. Vector Narrowing Fixed-Point Clip Instructions 7102e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 710306c3fb27SDimitry Andricdefm : VPatBinaryV_WV_WX_WI_RM<"int_riscv_vnclipu", "PseudoVNCLIPU", 710406c3fb27SDimitry Andric AllWidenableIntVectors>; 710506c3fb27SDimitry Andricdefm : VPatBinaryV_WV_WX_WI_RM<"int_riscv_vnclip", "PseudoVNCLIP", 710606c3fb27SDimitry Andric AllWidenableIntVectors>; 7107e8d8bef9SDimitry Andric 7108bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 7109bdd1243dSDimitry Andric// 13. Vector Floating-Point Instructions 7110bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 7111bdd1243dSDimitry Andric 7112e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7113bdd1243dSDimitry Andric// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 7114e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 711506c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vfadd", "PseudoVFADD", 711606c3fb27SDimitry Andric AllFloatVectors>; 711706c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vfsub", "PseudoVFSUB", 711806c3fb27SDimitry Andric AllFloatVectors>; 711906c3fb27SDimitry Andricdefm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>; 7120e8d8bef9SDimitry Andric 7121e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7122bdd1243dSDimitry Andric// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 7123e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 712406c3fb27SDimitry Andricdefm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwadd", "PseudoVFWADD", 712506c3fb27SDimitry Andric AllWidenableFloatVectors>; 712606c3fb27SDimitry Andricdefm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwsub", "PseudoVFWSUB", 712706c3fb27SDimitry Andric AllWidenableFloatVectors>; 712806c3fb27SDimitry Andricdefm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwadd_w", "PseudoVFWADD", 712906c3fb27SDimitry Andric AllWidenableFloatVectors>; 713006c3fb27SDimitry Andricdefm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB", 713106c3fb27SDimitry Andric AllWidenableFloatVectors>; 7132e8d8bef9SDimitry Andric 7133e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7134bdd1243dSDimitry Andric// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 7135e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 713606c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL", 713706c3fb27SDimitry Andric AllFloatVectors>; 713806c3fb27SDimitry Andricdefm : VPatBinaryV_VV_VX_RM<"int_riscv_vfdiv", "PseudoVFDIV", 713906c3fb27SDimitry Andric AllFloatVectors, isSEWAware=1>; 714006c3fb27SDimitry Andricdefm : VPatBinaryV_VX_RM<"int_riscv_vfrdiv", "PseudoVFRDIV", 714106c3fb27SDimitry Andric AllFloatVectors, isSEWAware=1>; 7142e8d8bef9SDimitry Andric 7143e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7144bdd1243dSDimitry Andric// 13.5. Vector Widening Floating-Point Multiply 7145e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 714606c3fb27SDimitry Andricdefm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwmul", "PseudoVFWMUL", 714706c3fb27SDimitry Andric AllWidenableFloatVectors>; 7148e8d8bef9SDimitry Andric 7149e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7150bdd1243dSDimitry Andric// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 7151e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 715206c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmacc", "PseudoVFMACC", AllFloatVectors>; 715306c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmacc", "PseudoVFNMACC", AllFloatVectors>; 715406c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsac", "PseudoVFMSAC", AllFloatVectors>; 715506c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsac", "PseudoVFNMSAC", AllFloatVectors>; 715606c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmadd", "PseudoVFMADD", AllFloatVectors>; 715706c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmadd", "PseudoVFNMADD", AllFloatVectors>; 715806c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsub", "PseudoVFMSUB", AllFloatVectors>; 715906c3fb27SDimitry Andricdefm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>; 7160e8d8bef9SDimitry Andric 7161e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7162bdd1243dSDimitry Andric// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 7163e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 716406c3fb27SDimitry Andricdefm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmacc", "PseudoVFWMACC", 716506c3fb27SDimitry Andric AllWidenableFloatVectors>; 716606c3fb27SDimitry Andricdefm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmacc", "PseudoVFWNMACC", 716706c3fb27SDimitry Andric AllWidenableFloatVectors>; 716806c3fb27SDimitry Andricdefm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC", 716906c3fb27SDimitry Andric AllWidenableFloatVectors>; 717006c3fb27SDimitry Andricdefm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", 717106c3fb27SDimitry Andric AllWidenableFloatVectors>; 71725f757f3fSDimitry Andriclet Predicates = [HasStdExtZvfbfwma] in 71735f757f3fSDimitry Andricdefm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16", 71745f757f3fSDimitry Andric AllWidenableBFloatToFloatVectors>; 7175e8d8bef9SDimitry Andric 7176e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7177bdd1243dSDimitry Andric// 13.8. Vector Floating-Point Square-Root Instruction 7178e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 717906c3fb27SDimitry Andricdefm : VPatUnaryV_V_RM<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors, isSEWAware=1>; 7180e8d8bef9SDimitry Andric 7181e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7182bdd1243dSDimitry Andric// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 7183e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7184fe6060f1SDimitry Andricdefm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7", AllFloatVectors>; 7185e8d8bef9SDimitry Andric 7186e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7187bdd1243dSDimitry Andric// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 7188e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 718906c3fb27SDimitry Andricdefm : VPatUnaryV_V_RM<"int_riscv_vfrec7", "PseudoVFREC7", AllFloatVectors>; 7190e8d8bef9SDimitry Andric 7191e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7192bdd1243dSDimitry Andric// 13.11. Vector Floating-Point Min/Max Instructions 7193e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7194fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>; 7195fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors>; 7196e8d8bef9SDimitry Andric 7197e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7198bdd1243dSDimitry Andric// 13.12. Vector Floating-Point Sign-Injection Instructions 7199e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7200fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vfsgnj", "PseudoVFSGNJ", AllFloatVectors>; 7201fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjn", "PseudoVFSGNJN", AllFloatVectors>; 7202fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjx", "PseudoVFSGNJX", AllFloatVectors>; 7203e8d8bef9SDimitry Andric 7204e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7205bdd1243dSDimitry Andric// 13.13. Vector Floating-Point Compare Instructions 7206e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7207fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ", AllFloatVectors>; 7208fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE", AllFloatVectors>; 7209fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX<"int_riscv_vmflt", "PseudoVMFLT", AllFloatVectors>; 7210fe6060f1SDimitry Andricdefm : VPatBinaryM_VV_VX<"int_riscv_vmfne", "PseudoVMFNE", AllFloatVectors>; 7211fe6060f1SDimitry Andricdefm : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT", AllFloatVectors>; 7212fe6060f1SDimitry Andricdefm : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>; 7213fe6060f1SDimitry Andricdefm : VPatBinarySwappedM_VV<"int_riscv_vmfgt", "PseudoVMFLT", AllFloatVectors>; 7214fe6060f1SDimitry Andricdefm : VPatBinarySwappedM_VV<"int_riscv_vmfge", "PseudoVMFLE", AllFloatVectors>; 7215e8d8bef9SDimitry Andric 7216e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7217bdd1243dSDimitry Andric// 13.14. Vector Floating-Point Classify Instruction 7218e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 721981ad6265SDimitry Andricdefm : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">; 7220e8d8bef9SDimitry Andric 7221e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7222bdd1243dSDimitry Andric// 13.15. Vector Floating-Point Merge Instruction 7223e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7224e8d8bef9SDimitry Andric// We can use vmerge.vvm to support vector-vector vfmerge. 7225349cc55cSDimitry Andric// NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses 7226349cc55cSDimitry Andric// int_riscv_vmerge. Support both for compatibility. 722706c3fb27SDimitry Andricforeach vti = AllFloatVectors in { 722806c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 722906c3fb27SDimitry Andric defm : VPatBinaryCarryInTAIL<"int_riscv_vmerge", "PseudoVMERGE", "VVM", 723006c3fb27SDimitry Andric vti.Vector, 723106c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Mask, 723206c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 723306c3fb27SDimitry Andric vti.RegClass, vti.RegClass>; 723406c3fb27SDimitry Andric defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVMERGE", "VVM", 723506c3fb27SDimitry Andric vti.Vector, 723606c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Mask, 723706c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 723806c3fb27SDimitry Andric vti.RegClass, vti.RegClass>; 723906c3fb27SDimitry Andric defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVFMERGE", 724006c3fb27SDimitry Andric "V"#vti.ScalarSuffix#"M", 724106c3fb27SDimitry Andric vti.Vector, 724206c3fb27SDimitry Andric vti.Vector, vti.Scalar, vti.Mask, 724306c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, 724406c3fb27SDimitry Andric vti.RegClass, vti.ScalarRegClass>; 724506c3fb27SDimitry Andric } 724606c3fb27SDimitry Andric} 7247e8d8bef9SDimitry Andric 7248e8d8bef9SDimitry Andricforeach fvti = AllFloatVectors in { 7249e8d8bef9SDimitry Andric defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX); 725006c3fb27SDimitry Andric let Predicates = GetVTypePredicates<fvti>.Predicates in 725181ad6265SDimitry Andric def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$merge), 725281ad6265SDimitry Andric (fvti.Vector fvti.RegClass:$rs2), 725381ad6265SDimitry Andric (fvti.Scalar (fpimm0)), 725481ad6265SDimitry Andric (fvti.Mask V0), VLOpFrag)), 725506c3fb27SDimitry Andric (instr fvti.RegClass:$merge, fvti.RegClass:$rs2, 0, 725681ad6265SDimitry Andric (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 7257e8d8bef9SDimitry Andric} 7258e8d8bef9SDimitry Andric 7259e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7260bdd1243dSDimitry Andric// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 7261e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 726206c3fb27SDimitry Andricdefm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_X_F">; 726306c3fb27SDimitry Andricdefm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_XU_F">; 7264fe6060f1SDimitry Andricdefm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_xu_f_v", "PseudoVFCVT_RTZ_XU_F">; 7265fe6060f1SDimitry Andricdefm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_x_f_v", "PseudoVFCVT_RTZ_X_F">; 726606c3fb27SDimitry Andricdefm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_x_v", "PseudoVFCVT_F_X">; 726706c3fb27SDimitry Andricdefm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU">; 7268e8d8bef9SDimitry Andric 7269e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7270bdd1243dSDimitry Andric// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 7271e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 727206c3fb27SDimitry Andricdefm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_XU_F">; 727306c3fb27SDimitry Andricdefm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_X_F">; 7274fe6060f1SDimitry Andricdefm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_xu_f_v", "PseudoVFWCVT_RTZ_XU_F">; 7275fe6060f1SDimitry Andricdefm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_x_f_v", "PseudoVFWCVT_RTZ_X_F">; 7276fe6060f1SDimitry Andricdefm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU">; 7277fe6060f1SDimitry Andricdefm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X">; 7278fe6060f1SDimitry Andricdefm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F">; 72795f757f3fSDimitry Andricdefm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v", 72805f757f3fSDimitry Andric "PseudoVFWCVTBF16_F_F">; 7281e8d8bef9SDimitry Andric 7282e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7283bdd1243dSDimitry Andric// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 7284e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 728506c3fb27SDimitry Andricdefm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">; 728606c3fb27SDimitry Andricdefm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">; 7287fe6060f1SDimitry Andricdefm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">; 7288fe6060f1SDimitry Andricdefm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">; 728906c3fb27SDimitry Andricdefm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">; 729006c3fb27SDimitry Andricdefm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">; 72915f757f3fSDimitry Andricdefvar WidenableFloatVectorsExceptF16 = !filter(fvtiToFWti, AllWidenableFloatVectors, 72925f757f3fSDimitry Andric !ne(fvtiToFWti.Vti.Scalar, f16)); 72935f757f3fSDimitry Andricdefm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F", 72945f757f3fSDimitry Andric WidenableFloatVectorsExceptF16>; 72955f757f3fSDimitry Andric// Define vfncvt.f.f.w for f16 when Zvfhmin is enable. 72965f757f3fSDimitry Andricdefvar F16WidenableFloatVectors = !filter(fvtiToFWti, AllWidenableFloatVectors, 72975f757f3fSDimitry Andric !eq(fvtiToFWti.Vti.Scalar, f16)); 72985f757f3fSDimitry Andriclet Predicates = [HasVInstructionsF16Minimal] in 72995f757f3fSDimitry Andricdefm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F", 73005f757f3fSDimitry Andric F16WidenableFloatVectors>; 73015f757f3fSDimitry Andricdefm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w", 73025f757f3fSDimitry Andric "PseudoVFNCVTBF16_F_F">; 7303fe6060f1SDimitry Andricdefm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">; 7304e8d8bef9SDimitry Andric 7305bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 7306bdd1243dSDimitry Andric// 14. Vector Reduction Operations 7307bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 7308bdd1243dSDimitry Andric 7309e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7310bdd1243dSDimitry Andric// 14.1. Vector Single-Width Integer Reduction Instructions 7311e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7312fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredsum", "PseudoVREDSUM">; 7313fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredand", "PseudoVREDAND">; 7314fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredor", "PseudoVREDOR">; 7315fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredxor", "PseudoVREDXOR">; 7316fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredminu", "PseudoVREDMINU">; 7317fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredmin", "PseudoVREDMIN">; 7318fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredmaxu", "PseudoVREDMAXU">; 7319fe6060f1SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vredmax", "PseudoVREDMAX">; 7320e8d8bef9SDimitry Andric 7321e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7322bdd1243dSDimitry Andric// 14.2. Vector Widening Integer Reduction Instructions 7323e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7324fe6060f1SDimitry Andricdefm : VPatReductionW_VS<"int_riscv_vwredsumu", "PseudoVWREDSUMU">; 7325fe6060f1SDimitry Andricdefm : VPatReductionW_VS<"int_riscv_vwredsum", "PseudoVWREDSUM">; 7326e8d8bef9SDimitry Andric 7327e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7328bdd1243dSDimitry Andric// 14.3. Vector Single-Width Floating-Point Reduction Instructions 7329e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 733006c3fb27SDimitry Andricdefm : VPatReductionV_VS_RM<"int_riscv_vfredosum", "PseudoVFREDOSUM", IsFloat=1>; 733106c3fb27SDimitry Andricdefm : VPatReductionV_VS_RM<"int_riscv_vfredusum", "PseudoVFREDUSUM", IsFloat=1>; 733206c3fb27SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", IsFloat=1>; 733306c3fb27SDimitry Andricdefm : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", IsFloat=1>; 7334e8d8bef9SDimitry Andric 7335e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7336bdd1243dSDimitry Andric// 14.4. Vector Widening Floating-Point Reduction Instructions 7337e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 733806c3fb27SDimitry Andricdefm : VPatReductionW_VS_RM<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", IsFloat=1>; 733906c3fb27SDimitry Andricdefm : VPatReductionW_VS_RM<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", IsFloat=1>; 7340e8d8bef9SDimitry Andric 7341e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7342bdd1243dSDimitry Andric// 15. Vector Mask Instructions 7343e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7344e8d8bef9SDimitry Andric 7345e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7346bdd1243dSDimitry Andric// 15.1 Vector Mask-Register Logical Instructions 7347e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7348fe6060f1SDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmand", "PseudoVMAND">; 7349fe6060f1SDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmnand", "PseudoVMNAND">; 7350349cc55cSDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmandn", "PseudoVMANDN">; 7351fe6060f1SDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmxor", "PseudoVMXOR">; 7352fe6060f1SDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmor", "PseudoVMOR">; 7353fe6060f1SDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmnor", "PseudoVMNOR">; 7354349cc55cSDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmorn", "PseudoVMORN">; 7355fe6060f1SDimitry Andricdefm : VPatBinaryM_MM<"int_riscv_vmxnor", "PseudoVMXNOR">; 7356e8d8bef9SDimitry Andric 7357e8d8bef9SDimitry Andric// pseudo instructions 7358fe6060f1SDimitry Andricdefm : VPatNullaryM<"int_riscv_vmclr", "PseudoVMCLR">; 7359fe6060f1SDimitry Andricdefm : VPatNullaryM<"int_riscv_vmset", "PseudoVMSET">; 7360e8d8bef9SDimitry Andric 7361e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7362bdd1243dSDimitry Andric// 15.2. Vector count population in mask vcpop.m 7363e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7364349cc55cSDimitry Andricdefm : VPatUnaryS_M<"int_riscv_vcpop", "PseudoVCPOP">; 7365e8d8bef9SDimitry Andric 7366e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7367bdd1243dSDimitry Andric// 15.3. vfirst find-first-set mask bit 7368e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7369fe6060f1SDimitry Andricdefm : VPatUnaryS_M<"int_riscv_vfirst", "PseudoVFIRST">; 7370e8d8bef9SDimitry Andric 7371e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7372bdd1243dSDimitry Andric// 15.4. vmsbf.m set-before-first mask bit 7373e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7374fe6060f1SDimitry Andricdefm : VPatUnaryM_M<"int_riscv_vmsbf", "PseudoVMSBF">; 7375e8d8bef9SDimitry Andric 7376e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7377bdd1243dSDimitry Andric// 15.5. vmsif.m set-including-first mask bit 7378e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7379fe6060f1SDimitry Andricdefm : VPatUnaryM_M<"int_riscv_vmsif", "PseudoVMSIF">; 7380e8d8bef9SDimitry Andric 7381e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7382bdd1243dSDimitry Andric// 15.6. vmsof.m set-only-first mask bit 7383e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7384fe6060f1SDimitry Andricdefm : VPatUnaryM_M<"int_riscv_vmsof", "PseudoVMSOF">; 7385e8d8bef9SDimitry Andric 7386e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7387bdd1243dSDimitry Andric// 15.8. Vector Iota Instruction 7388e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7389fe6060f1SDimitry Andricdefm : VPatUnaryV_M<"int_riscv_viota", "PseudoVIOTA">; 7390e8d8bef9SDimitry Andric 7391e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7392bdd1243dSDimitry Andric// 15.9. Vector Element Index Instruction 7393e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7394fe6060f1SDimitry Andricdefm : VPatNullaryV<"int_riscv_vid", "PseudoVID">; 7395e8d8bef9SDimitry Andric 7396e8d8bef9SDimitry Andric 7397e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7398bdd1243dSDimitry Andric// 16. Vector Permutation Instructions 7399e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7400e8d8bef9SDimitry Andric 7401e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7402bdd1243dSDimitry Andric// 16.1. Integer Scalar Move Instructions 7403e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7404e8d8bef9SDimitry Andric 7405*7a6dacacSDimitry Andricforeach vti = NoGroupIntegerVectors in { 740606c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 740706c3fb27SDimitry Andric def : Pat<(XLenVT (riscv_vmv_x_s (vti.Vector vti.RegClass:$rs2))), 7408*7a6dacacSDimitry Andric (PseudoVMV_X_S $rs2, vti.Log2SEW)>; 7409fe6060f1SDimitry Andric // vmv.s.x is handled with a custom node in RISCVInstrInfoVVLPatterns.td 7410e8d8bef9SDimitry Andric} 7411e8d8bef9SDimitry Andric 7412e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7413bdd1243dSDimitry Andric// 16.3. Vector Slide Instructions 7414e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7415fe6060f1SDimitry Andricdefm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllIntegerVectors, uimm5>; 7416fe6060f1SDimitry Andricdefm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllIntegerVectors, uimm5>; 7417fe6060f1SDimitry Andricdefm : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>; 7418fe6060f1SDimitry Andricdefm : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>; 7419e8d8bef9SDimitry Andric 7420fe6060f1SDimitry Andricdefm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectors, uimm5>; 7421fe6060f1SDimitry Andricdefm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVectors, uimm5>; 7422fe6060f1SDimitry Andricdefm : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP", AllFloatVectors>; 7423fe6060f1SDimitry Andricdefm : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN", AllFloatVectors>; 7424e8d8bef9SDimitry Andric 7425e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7426bdd1243dSDimitry Andric// 16.4. Vector Register Gather Instructions 7427e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7428fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER", 7429e8d8bef9SDimitry Andric AllIntegerVectors, uimm5>; 7430fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16", 743106c3fb27SDimitry Andric eew=16, vtilist=AllIntegerVectors>; 7432e8d8bef9SDimitry Andric 7433fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER", 7434e8d8bef9SDimitry Andric AllFloatVectors, uimm5>; 7435fe6060f1SDimitry Andricdefm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16", 743606c3fb27SDimitry Andric eew=16, vtilist=AllFloatVectors>; 7437e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7438bdd1243dSDimitry Andric// 16.5. Vector Compress Instruction 7439e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 7440fe6060f1SDimitry Andricdefm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllIntegerVectors>; 744106c3fb27SDimitry Andricdefm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFloatVectors>; 7442e8d8bef9SDimitry Andric 7443e8d8bef9SDimitry Andric// Include the non-intrinsic ISel patterns 7444fe6060f1SDimitry Andricinclude "RISCVInstrInfoVVLPatterns.td" 744581ad6265SDimitry Andricinclude "RISCVInstrInfoVSDPatterns.td" 7446