1fe6060f1SDimitry Andric//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2fe6060f1SDimitry Andric// 3fe6060f1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4fe6060f1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5fe6060f1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6fe6060f1SDimitry Andric// 7fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 8fe6060f1SDimitry Andric/// 9fe6060f1SDimitry Andric/// This file contains the required infrastructure and VL patterns to 10fe6060f1SDimitry Andric/// support code generation for the standard 'V' (Vector) extension, version 1181ad6265SDimitry Andric/// version 1.0. 12fe6060f1SDimitry Andric/// 13fe6060f1SDimitry Andric/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 14fe6060f1SDimitry Andric/// 15fe6060f1SDimitry Andric/// Note: the patterns for RVV intrinsics are found in 16fe6060f1SDimitry Andric/// RISCVInstrInfoVPseudos.td. 17fe6060f1SDimitry Andric/// 18fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 19fe6060f1SDimitry Andric 20fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 21fe6060f1SDimitry Andric// Helpers to define the VL patterns. 22fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 23fe6060f1SDimitry Andric 2406c3fb27SDimitry Andricdef SDT_RISCVIntUnOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 2506c3fb27SDimitry Andric SDTCisSameAs<0, 2>, 2606c3fb27SDimitry Andric SDTCisVec<0>, SDTCisInt<0>, 2706c3fb27SDimitry Andric SDTCVecEltisVT<3, i1>, 2806c3fb27SDimitry Andric SDTCisSameNumEltsAs<0, 3>, 2906c3fb27SDimitry Andric SDTCisVT<4, XLenVT>]>; 3006c3fb27SDimitry Andric 31bdd1243dSDimitry Andricdef SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 32fe6060f1SDimitry Andric SDTCisSameAs<0, 2>, 33fe6060f1SDimitry Andric SDTCisVec<0>, SDTCisInt<0>, 34bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 35bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 36bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 4>, 37bdd1243dSDimitry Andric SDTCisVT<5, XLenVT>]>; 38fe6060f1SDimitry Andric 39fe6060f1SDimitry Andricdef SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 40fe6060f1SDimitry Andric SDTCisVec<0>, SDTCisFP<0>, 41fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, 42fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 2>, 43fe6060f1SDimitry Andric SDTCisVT<3, XLenVT>]>; 44bdd1243dSDimitry Andricdef SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 45fe6060f1SDimitry Andric SDTCisSameAs<0, 2>, 46fe6060f1SDimitry Andric SDTCisVec<0>, SDTCisFP<0>, 47bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 48bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 49bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 4>, 50bdd1243dSDimitry Andric SDTCisVT<5, XLenVT>]>; 51bdd1243dSDimitry Andric 52bdd1243dSDimitry Andricdef SDT_RISCVCopySign_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 53bdd1243dSDimitry Andric SDTCisSameAs<0, 2>, 54bdd1243dSDimitry Andric SDTCisVec<0>, SDTCisFP<0>, 55bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 56bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 57bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 4>, 58bdd1243dSDimitry Andric SDTCisVT<5, XLenVT>]>; 59fe6060f1SDimitry Andric 6006c3fb27SDimitry Andricdef riscv_vmv_v_v_vl : SDNode<"RISCVISD::VMV_V_V_VL", 6106c3fb27SDimitry Andric SDTypeProfile<1, 3, [SDTCisVec<0>, 6206c3fb27SDimitry Andric SDTCisSameAs<0, 1>, 6306c3fb27SDimitry Andric SDTCisSameAs<0, 2>, 6406c3fb27SDimitry Andric SDTCisVT<3, XLenVT>]>>; 65fe6060f1SDimitry Andricdef riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 6681ad6265SDimitry Andric SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, 6781ad6265SDimitry Andric SDTCisSameAs<0, 1>, 6881ad6265SDimitry Andric SDTCisVT<2, XLenVT>, 6981ad6265SDimitry Andric SDTCisVT<3, XLenVT>]>>; 70fe6060f1SDimitry Andricdef riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 7181ad6265SDimitry Andric SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 7281ad6265SDimitry Andric SDTCisSameAs<0, 1>, 7381ad6265SDimitry Andric SDTCisEltOfVec<2, 0>, 7481ad6265SDimitry Andric SDTCisVT<3, XLenVT>]>>; 75fe6060f1SDimitry Andricdef riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 76fe6060f1SDimitry Andric SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 77fe6060f1SDimitry Andric SDTCisInt<0>, 78fe6060f1SDimitry Andric SDTCisVT<2, XLenVT>, 79fe6060f1SDimitry Andric SDTCisVT<3, XLenVT>]>>; 80fe6060f1SDimitry Andricdef riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 81fe6060f1SDimitry Andric SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 82fe6060f1SDimitry Andric SDTCisFP<0>, 83fe6060f1SDimitry Andric SDTCisEltOfVec<2, 0>, 84fe6060f1SDimitry Andric SDTCisVT<3, XLenVT>]>>; 85fe6060f1SDimitry Andric 86fe6060f1SDimitry Andricdef riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 87fe6060f1SDimitry Andricdef riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 88fe6060f1SDimitry Andricdef riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 89fe6060f1SDimitry Andricdef riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 90fe6060f1SDimitry Andricdef riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 91fe6060f1SDimitry Andricdef riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 92fe6060f1SDimitry Andricdef riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 93fe6060f1SDimitry Andricdef riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 94fe6060f1SDimitry Andricdef riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 95fe6060f1SDimitry Andricdef riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 96fe6060f1SDimitry Andricdef riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 97fe6060f1SDimitry Andricdef riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 98fe6060f1SDimitry Andricdef riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 99fe6060f1SDimitry Andricdef riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 100fe6060f1SDimitry Andricdef riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 1015f757f3fSDimitry Andricdef riscv_rotl_vl : SDNode<"RISCVISD::ROTL_VL", SDT_RISCVIntBinOp_VL>; 1025f757f3fSDimitry Andricdef riscv_rotr_vl : SDNode<"RISCVISD::ROTR_VL", SDT_RISCVIntBinOp_VL>; 103753f127fSDimitry Andricdef riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 104753f127fSDimitry Andricdef riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 105753f127fSDimitry Andricdef riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 106753f127fSDimitry Andricdef riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 107fe6060f1SDimitry Andric 10806c3fb27SDimitry Andricdef riscv_bitreverse_vl : SDNode<"RISCVISD::BITREVERSE_VL", SDT_RISCVIntUnOp_VL>; 10906c3fb27SDimitry Andricdef riscv_bswap_vl : SDNode<"RISCVISD::BSWAP_VL", SDT_RISCVIntUnOp_VL>; 11006c3fb27SDimitry Andricdef riscv_ctlz_vl : SDNode<"RISCVISD::CTLZ_VL", SDT_RISCVIntUnOp_VL>; 11106c3fb27SDimitry Andricdef riscv_cttz_vl : SDNode<"RISCVISD::CTTZ_VL", SDT_RISCVIntUnOp_VL>; 11206c3fb27SDimitry Andricdef riscv_ctpop_vl : SDNode<"RISCVISD::CTPOP_VL", SDT_RISCVIntUnOp_VL>; 11306c3fb27SDimitry Andric 1141db9f3b2SDimitry Andricdef riscv_avgflooru_vl : SDNode<"RISCVISD::AVGFLOORU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 115297eecfbSDimitry Andricdef riscv_avgceilu_vl : SDNode<"RISCVISD::AVGCEILU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 116753f127fSDimitry Andricdef riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 117753f127fSDimitry Andricdef riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 118fe6060f1SDimitry Andricdef riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 119fe6060f1SDimitry Andricdef riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 120fe6060f1SDimitry Andric 121fe6060f1SDimitry Andricdef riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 122fe6060f1SDimitry Andricdef riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 123fe6060f1SDimitry Andricdef riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 124fe6060f1SDimitry Andricdef riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 125fe6060f1SDimitry Andricdef riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 126fe6060f1SDimitry Andricdef riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 127fe6060f1SDimitry Andricdef riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 128bdd1243dSDimitry Andricdef riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVCopySign_VL>; 1295f757f3fSDimitry Andricdef riscv_vfmin_vl : SDNode<"RISCVISD::VFMIN_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 1305f757f3fSDimitry Andricdef riscv_vfmax_vl : SDNode<"RISCVISD::VFMAX_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 131fe6060f1SDimitry Andric 13206c3fb27SDimitry Andricdef riscv_strict_fadd_vl : SDNode<"RISCVISD::STRICT_FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative, SDNPHasChain]>; 13306c3fb27SDimitry Andricdef riscv_strict_fsub_vl : SDNode<"RISCVISD::STRICT_FSUB_VL", SDT_RISCVFPBinOp_VL, [SDNPHasChain]>; 13406c3fb27SDimitry Andricdef riscv_strict_fmul_vl : SDNode<"RISCVISD::STRICT_FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative, SDNPHasChain]>; 13506c3fb27SDimitry Andricdef riscv_strict_fdiv_vl : SDNode<"RISCVISD::STRICT_FDIV_VL", SDT_RISCVFPBinOp_VL, [SDNPHasChain]>; 13606c3fb27SDimitry Andricdef riscv_strict_fsqrt_vl : SDNode<"RISCVISD::STRICT_FSQRT_VL", SDT_RISCVFPUnOp_VL, [SDNPHasChain]>; 13706c3fb27SDimitry Andric 13806c3fb27SDimitry Andricdef any_riscv_fadd_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 13906c3fb27SDimitry Andric [(riscv_fadd_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 14006c3fb27SDimitry Andric (riscv_strict_fadd_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl)]>; 14106c3fb27SDimitry Andricdef any_riscv_fsub_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 14206c3fb27SDimitry Andric [(riscv_fsub_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 14306c3fb27SDimitry Andric (riscv_strict_fsub_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl)]>; 14406c3fb27SDimitry Andricdef any_riscv_fmul_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 14506c3fb27SDimitry Andric [(riscv_fmul_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 14606c3fb27SDimitry Andric (riscv_strict_fmul_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl)]>; 14706c3fb27SDimitry Andricdef any_riscv_fdiv_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 14806c3fb27SDimitry Andric [(riscv_fdiv_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl), 14906c3fb27SDimitry Andric (riscv_strict_fdiv_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl)]>; 15006c3fb27SDimitry Andricdef any_riscv_fsqrt_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 15106c3fb27SDimitry Andric [(riscv_fsqrt_vl node:$src, node:$mask, node:$vl), 15206c3fb27SDimitry Andric (riscv_strict_fsqrt_vl node:$src, node:$mask, node:$vl)]>; 15306c3fb27SDimitry Andric 15406c3fb27SDimitry Andricdef riscv_fclass_vl : SDNode<"RISCVISD::FCLASS_VL", 15506c3fb27SDimitry Andric SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 15606c3fb27SDimitry Andric SDTCisFP<1>, SDTCisVec<1>, 15706c3fb27SDimitry Andric SDTCisSameSizeAs<0, 1>, 15806c3fb27SDimitry Andric SDTCisSameNumEltsAs<0, 1>, 15906c3fb27SDimitry Andric SDTCVecEltisVT<2, i1>, 16006c3fb27SDimitry Andric SDTCisSameNumEltsAs<0, 2>, 16106c3fb27SDimitry Andric SDTCisVT<3, XLenVT>]>>; 16206c3fb27SDimitry Andric 163fe6060f1SDimitry Andricdef SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 164fe6060f1SDimitry Andric SDTCisSameAs<0, 2>, 165fe6060f1SDimitry Andric SDTCisSameAs<0, 3>, 166fe6060f1SDimitry Andric SDTCisVec<0>, SDTCisFP<0>, 167fe6060f1SDimitry Andric SDTCVecEltisVT<4, i1>, 168fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 4>, 169fe6060f1SDimitry Andric SDTCisVT<5, XLenVT>]>; 17081ad6265SDimitry Andricdef riscv_vfmadd_vl : SDNode<"RISCVISD::VFMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 17181ad6265SDimitry Andricdef riscv_vfnmadd_vl : SDNode<"RISCVISD::VFNMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 17281ad6265SDimitry Andricdef riscv_vfmsub_vl : SDNode<"RISCVISD::VFMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 17381ad6265SDimitry Andricdef riscv_vfnmsub_vl : SDNode<"RISCVISD::VFNMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 174fe6060f1SDimitry Andric 17506c3fb27SDimitry Andricdef SDT_RISCVWVecFMA_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>, 17606c3fb27SDimitry Andric SDTCisVec<1>, SDTCisFP<1>, 17706c3fb27SDimitry Andric SDTCisOpSmallerThanOp<1, 0>, 17806c3fb27SDimitry Andric SDTCisSameNumEltsAs<0, 1>, 17906c3fb27SDimitry Andric SDTCisSameAs<1, 2>, 18006c3fb27SDimitry Andric SDTCisSameAs<0, 3>, 18106c3fb27SDimitry Andric SDTCVecEltisVT<4, i1>, 18206c3fb27SDimitry Andric SDTCisSameNumEltsAs<0, 4>, 18306c3fb27SDimitry Andric SDTCisVT<5, XLenVT>]>; 18406c3fb27SDimitry Andricdef riscv_vfwmadd_vl : SDNode<"RISCVISD::VFWMADD_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>; 18506c3fb27SDimitry Andricdef riscv_vfwnmadd_vl : SDNode<"RISCVISD::VFWNMADD_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>; 18606c3fb27SDimitry Andricdef riscv_vfwmsub_vl : SDNode<"RISCVISD::VFWMSUB_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>; 18706c3fb27SDimitry Andricdef riscv_vfwnmsub_vl : SDNode<"RISCVISD::VFWNMSUB_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>; 18806c3fb27SDimitry Andric 18906c3fb27SDimitry Andricdef riscv_strict_vfmadd_vl : SDNode<"RISCVISD::STRICT_VFMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>; 19006c3fb27SDimitry Andricdef riscv_strict_vfnmadd_vl : SDNode<"RISCVISD::STRICT_VFNMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>; 19106c3fb27SDimitry Andricdef riscv_strict_vfmsub_vl : SDNode<"RISCVISD::STRICT_VFMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>; 19206c3fb27SDimitry Andricdef riscv_strict_vfnmsub_vl : SDNode<"RISCVISD::STRICT_VFNMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>; 19306c3fb27SDimitry Andric 19406c3fb27SDimitry Andricdef any_riscv_vfmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 19506c3fb27SDimitry Andric [(riscv_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 19606c3fb27SDimitry Andric (riscv_strict_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>; 19706c3fb27SDimitry Andricdef any_riscv_vfnmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 19806c3fb27SDimitry Andric [(riscv_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 19906c3fb27SDimitry Andric (riscv_strict_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>; 20006c3fb27SDimitry Andricdef any_riscv_vfmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 20106c3fb27SDimitry Andric [(riscv_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 20206c3fb27SDimitry Andric (riscv_strict_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>; 20306c3fb27SDimitry Andricdef any_riscv_vfnmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 20406c3fb27SDimitry Andric [(riscv_vfnmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl), 20506c3fb27SDimitry Andric (riscv_strict_vfnmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>; 20606c3fb27SDimitry Andric 207fe6060f1SDimitry Andricdef SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 208fe6060f1SDimitry Andric SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 209fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 210fe6060f1SDimitry Andric]>; 211fe6060f1SDimitry Andricdef SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 212fe6060f1SDimitry Andric SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 213fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 214fe6060f1SDimitry Andric]>; 215fe6060f1SDimitry Andric 216fe6060f1SDimitry Andricdef riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 21706c3fb27SDimitry Andricdef riscv_strict_fpround_vl : SDNode<"RISCVISD::STRICT_FP_ROUND_VL", SDT_RISCVFPRoundOp_VL, [SDNPHasChain]>; 218fe6060f1SDimitry Andricdef riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 21906c3fb27SDimitry Andricdef riscv_strict_fpextend_vl : SDNode<"RISCVISD::STRICT_FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL, [SDNPHasChain]>; 220fe6060f1SDimitry Andricdef riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 22106c3fb27SDimitry Andricdef riscv_strict_fncvt_rod_vl : SDNode<"RISCVISD::STRICT_VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL, [SDNPHasChain]>; 22206c3fb27SDimitry Andric 22306c3fb27SDimitry Andricdef any_riscv_fpround_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 22406c3fb27SDimitry Andric [(riscv_fpround_vl node:$src, node:$mask, node:$vl), 22506c3fb27SDimitry Andric (riscv_strict_fpround_vl node:$src, node:$mask, node:$vl)]>; 22606c3fb27SDimitry Andricdef any_riscv_fpextend_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 22706c3fb27SDimitry Andric [(riscv_fpextend_vl node:$src, node:$mask, node:$vl), 22806c3fb27SDimitry Andric (riscv_strict_fpextend_vl node:$src, node:$mask, node:$vl)]>; 22906c3fb27SDimitry Andricdef any_riscv_fncvt_rod_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 23006c3fb27SDimitry Andric [(riscv_fncvt_rod_vl node:$src, node:$mask, node:$vl), 23106c3fb27SDimitry Andric (riscv_strict_fncvt_rod_vl node:$src, node:$mask, node:$vl)]>; 232fe6060f1SDimitry Andric 233fe6060f1SDimitry Andricdef SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 234fe6060f1SDimitry Andric SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 235fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 236fe6060f1SDimitry Andric]>; 237bdd1243dSDimitry Andricdef SDT_RISCVFP2IOp_RM_VL : SDTypeProfile<1, 4, [ 238bdd1243dSDimitry Andric SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 239bdd1243dSDimitry Andric SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>, 240bdd1243dSDimitry Andric SDTCisVT<4, XLenVT> // Rounding mode 241bdd1243dSDimitry Andric]>; 242bdd1243dSDimitry Andric 243fe6060f1SDimitry Andricdef SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 244fe6060f1SDimitry Andric SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 245fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 246fe6060f1SDimitry Andric]>; 247bdd1243dSDimitry Andricdef SDT_RISCVI2FPOp_RM_VL : SDTypeProfile<1, 4, [ 248bdd1243dSDimitry Andric SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 249bdd1243dSDimitry Andric SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>, 250bdd1243dSDimitry Andric SDTCisVT<4, XLenVT> // Rounding mode 251bdd1243dSDimitry Andric]>; 252fe6060f1SDimitry Andric 25306c3fb27SDimitry Andricdef SDT_RISCVSETCCOP_VL : SDTypeProfile<1, 6, [ 25406c3fb27SDimitry Andric SDTCVecEltisVT<0, i1>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, 25506c3fb27SDimitry Andric SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>, SDTCisSameAs<0, 4>, 25606c3fb27SDimitry Andric SDTCisSameAs<0, 5>, SDTCisVT<6, XLenVT>]>; 25706c3fb27SDimitry Andric 258bdd1243dSDimitry Andric// Float -> Int 259bdd1243dSDimitry Andricdef riscv_vfcvt_xu_f_vl : SDNode<"RISCVISD::VFCVT_XU_F_VL", SDT_RISCVFP2IOp_VL>; 260bdd1243dSDimitry Andricdef riscv_vfcvt_x_f_vl : SDNode<"RISCVISD::VFCVT_X_F_VL", SDT_RISCVFP2IOp_VL>; 261bdd1243dSDimitry Andricdef riscv_vfcvt_rm_xu_f_vl : SDNode<"RISCVISD::VFCVT_RM_XU_F_VL", SDT_RISCVFP2IOp_RM_VL>; 262bdd1243dSDimitry Andricdef riscv_vfcvt_rm_x_f_vl : SDNode<"RISCVISD::VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL>; 263bdd1243dSDimitry Andric 264bdd1243dSDimitry Andricdef riscv_vfcvt_rtz_xu_f_vl : SDNode<"RISCVISD::VFCVT_RTZ_XU_F_VL", SDT_RISCVFP2IOp_VL>; 265bdd1243dSDimitry Andricdef riscv_vfcvt_rtz_x_f_vl : SDNode<"RISCVISD::VFCVT_RTZ_X_F_VL", SDT_RISCVFP2IOp_VL>; 266bdd1243dSDimitry Andric 26706c3fb27SDimitry Andricdef riscv_strict_vfcvt_rm_x_f_vl : SDNode<"RISCVISD::STRICT_VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL, [SDNPHasChain]>; 26806c3fb27SDimitry Andricdef riscv_strict_vfcvt_rtz_xu_f_vl : SDNode<"RISCVISD::STRICT_VFCVT_RTZ_XU_F_VL", SDT_RISCVFP2IOp_VL, [SDNPHasChain]>; 26906c3fb27SDimitry Andricdef riscv_strict_vfcvt_rtz_x_f_vl : SDNode<"RISCVISD::STRICT_VFCVT_RTZ_X_F_VL", SDT_RISCVFP2IOp_VL, [SDNPHasChain]>; 27006c3fb27SDimitry Andric 27106c3fb27SDimitry Andricdef any_riscv_vfcvt_rm_x_f_vl : PatFrags<(ops node:$src, node:$mask, node:$vl, node:$rm), 27206c3fb27SDimitry Andric [(riscv_vfcvt_rm_x_f_vl node:$src, node:$mask, node:$vl, node:$rm), 27306c3fb27SDimitry Andric (riscv_strict_vfcvt_rm_x_f_vl node:$src, node:$mask, node:$vl, node:$rm)]>; 27406c3fb27SDimitry Andricdef any_riscv_vfcvt_rtz_xu_f_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 27506c3fb27SDimitry Andric [(riscv_vfcvt_rtz_xu_f_vl node:$src, node:$mask, node:$vl), 27606c3fb27SDimitry Andric (riscv_strict_vfcvt_rtz_xu_f_vl node:$src, node:$mask, node:$vl)]>; 27706c3fb27SDimitry Andricdef any_riscv_vfcvt_rtz_x_f_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 27806c3fb27SDimitry Andric [(riscv_vfcvt_rtz_x_f_vl node:$src, node:$mask, node:$vl), 27906c3fb27SDimitry Andric (riscv_strict_vfcvt_rtz_x_f_vl node:$src, node:$mask, node:$vl)]>; 28006c3fb27SDimitry Andric 281bdd1243dSDimitry Andric// Int -> Float 282fe6060f1SDimitry Andricdef riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 283fe6060f1SDimitry Andricdef riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 284bdd1243dSDimitry Andricdef riscv_vfcvt_rm_f_xu_vl : SDNode<"RISCVISD::VFCVT_RM_F_XU_VL", SDT_RISCVI2FPOp_RM_VL>; 285bdd1243dSDimitry Andricdef riscv_vfcvt_rm_f_x_vl : SDNode<"RISCVISD::VFCVT_RM_F_X_VL", SDT_RISCVI2FPOp_RM_VL>; 286bdd1243dSDimitry Andric 28706c3fb27SDimitry Andricdef riscv_strict_sint_to_fp_vl : SDNode<"RISCVISD::STRICT_SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL, [SDNPHasChain]>; 28806c3fb27SDimitry Andricdef riscv_strict_uint_to_fp_vl : SDNode<"RISCVISD::STRICT_UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL, [SDNPHasChain]>; 28906c3fb27SDimitry Andric 29006c3fb27SDimitry Andricdef any_riscv_sint_to_fp_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 29106c3fb27SDimitry Andric [(riscv_sint_to_fp_vl node:$src, node:$mask, node:$vl), 29206c3fb27SDimitry Andric (riscv_strict_sint_to_fp_vl node:$src, node:$mask, node:$vl)]>; 29306c3fb27SDimitry Andricdef any_riscv_uint_to_fp_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 29406c3fb27SDimitry Andric [(riscv_uint_to_fp_vl node:$src, node:$mask, node:$vl), 29506c3fb27SDimitry Andric (riscv_strict_uint_to_fp_vl node:$src, node:$mask, node:$vl)]>; 296bdd1243dSDimitry Andric 297bdd1243dSDimitry Andricdef riscv_vfround_noexcept_vl: SDNode<"RISCVISD::VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL>; 29806c3fb27SDimitry Andricdef riscv_strict_vfround_noexcept_vl: SDNode<"RISCVISD::STRICT_VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL, [SDNPHasChain]>; 299fe6060f1SDimitry Andric 30006c3fb27SDimitry Andricdef any_riscv_vfround_noexcept_vl : PatFrags<(ops node:$src, node:$mask, node:$vl), 30106c3fb27SDimitry Andric [(riscv_vfround_noexcept_vl node:$src, node:$mask, node:$vl), 30206c3fb27SDimitry Andric (riscv_strict_vfround_noexcept_vl node:$src, node:$mask, node:$vl)]>; 30306c3fb27SDimitry Andric 30406c3fb27SDimitry Andricdef riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", SDT_RISCVSETCCOP_VL>; 30506c3fb27SDimitry Andricdef riscv_strict_fsetcc_vl : SDNode<"RISCVISD::STRICT_FSETCC_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>; 30606c3fb27SDimitry Andricdef riscv_strict_fsetccs_vl : SDNode<"RISCVISD::STRICT_FSETCCS_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>; 30706c3fb27SDimitry Andricdef any_riscv_fsetcc_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$cc, node:$merge, node:$mask, node:$vl), 30806c3fb27SDimitry Andric [(riscv_setcc_vl node:$lhs, node:$rhs, node:$cc, node:$merge, node:$mask, node:$vl), 30906c3fb27SDimitry Andric (riscv_strict_fsetcc_vl node:$lhs, node:$rhs, node:$cc, node:$merge, node:$mask, node:$vl)]>; 31006c3fb27SDimitry Andricdef any_riscv_fsetccs_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$cc, node:$merge, node:$mask, node:$vl), 31106c3fb27SDimitry Andric [(riscv_setcc_vl node:$lhs, node:$rhs, node:$cc, node:$merge, node:$mask, node:$vl), 31206c3fb27SDimitry Andric (riscv_strict_fsetccs_vl node:$lhs, node:$rhs, node:$cc, node:$merge, node:$mask, node:$vl)]>; 313fe6060f1SDimitry Andric 314fe6060f1SDimitry Andricdef riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 31581ad6265SDimitry Andric SDTypeProfile<1, 5, [SDTCisVec<0>, 316fe6060f1SDimitry Andric SDTCisSameAs<0, 1>, 317fe6060f1SDimitry Andric SDTCisVT<2, XLenVT>, 318bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 319bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 320bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 4>, 32181ad6265SDimitry Andric SDTCisVT<5, XLenVT>]>>; 322fe6060f1SDimitry Andricdef riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 32381ad6265SDimitry Andric SDTypeProfile<1, 5, [SDTCisVec<0>, 324fe6060f1SDimitry Andric SDTCisSameAs<0, 1>, 325fe6060f1SDimitry Andric SDTCisInt<2>, 326fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 2>, 327fe6060f1SDimitry Andric SDTCisSameSizeAs<0, 2>, 328bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 329bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 330bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 4>, 33181ad6265SDimitry Andric SDTCisVT<5, XLenVT>]>>; 332fe6060f1SDimitry Andricdef riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 33381ad6265SDimitry Andric SDTypeProfile<1, 5, [SDTCisVec<0>, 334fe6060f1SDimitry Andric SDTCisSameAs<0, 1>, 335fe6060f1SDimitry Andric SDTCisInt<2>, 336fe6060f1SDimitry Andric SDTCVecEltisVT<2, i16>, 337fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 2>, 338bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 339bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 340bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 4>, 34181ad6265SDimitry Andric SDTCisVT<5, XLenVT>]>>; 342fe6060f1SDimitry Andric 343cb14a3feSDimitry Andricdef SDT_RISCVVMERGE_VL : SDTypeProfile<1, 5, [ 344cb14a3feSDimitry Andric SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>, 345cb14a3feSDimitry Andric SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameAs<0, 4>, 346cb14a3feSDimitry Andric SDTCisVT<5, XLenVT> 347cb14a3feSDimitry Andric]>; 348cb14a3feSDimitry Andric 349cb14a3feSDimitry Andricdef riscv_vmerge_vl : SDNode<"RISCVISD::VMERGE_VL", SDT_RISCVVMERGE_VL>; 350fe6060f1SDimitry Andric 35181ad6265SDimitry Andricdef SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, 35281ad6265SDimitry Andric SDTCisVT<1, XLenVT>]>; 35381ad6265SDimitry Andricdef riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; 35481ad6265SDimitry Andricdef riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; 35581ad6265SDimitry Andric 356fe6060f1SDimitry Andricdef SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 357fe6060f1SDimitry Andric SDTCisSameAs<0, 2>, 358fe6060f1SDimitry Andric SDTCVecEltisVT<0, i1>, 359fe6060f1SDimitry Andric SDTCisVT<3, XLenVT>]>; 360fe6060f1SDimitry Andricdef riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 361fe6060f1SDimitry Andricdef riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 362fe6060f1SDimitry Andricdef riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 363fe6060f1SDimitry Andric 364fe6060f1SDimitry Andricdef true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 365fe6060f1SDimitry Andric 366fe6060f1SDimitry Andricdef riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 367fe6060f1SDimitry Andric (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 368fe6060f1SDimitry Andric 369349cc55cSDimitry Andricdef riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 370fe6060f1SDimitry Andric SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 371fe6060f1SDimitry Andric SDTCisVec<1>, SDTCisInt<1>, 372fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, 373fe6060f1SDimitry Andric SDTCisSameNumEltsAs<1, 2>, 374fe6060f1SDimitry Andric SDTCisVT<3, XLenVT>]>>; 375fe6060f1SDimitry Andric 376bdd1243dSDimitry Andricdef riscv_vfirst_vl : SDNode<"RISCVISD::VFIRST_VL", 377bdd1243dSDimitry Andric SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 378bdd1243dSDimitry Andric SDTCisVec<1>, SDTCisInt<1>, 379bdd1243dSDimitry Andric SDTCVecEltisVT<2, i1>, 380bdd1243dSDimitry Andric SDTCisSameNumEltsAs<1, 2>, 381bdd1243dSDimitry Andric SDTCisVT<3, XLenVT>]>>; 382bdd1243dSDimitry Andric 383fe6060f1SDimitry Andricdef SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 384fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 1>, 385fe6060f1SDimitry Andric SDTCisSameNumEltsAs<1, 2>, 386fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, 387fe6060f1SDimitry Andric SDTCisVT<3, XLenVT>]>; 388fe6060f1SDimitry Andricdef riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 389fe6060f1SDimitry Andricdef riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 390fe6060f1SDimitry Andric 391fe6060f1SDimitry Andricdef riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 392fe6060f1SDimitry Andric SDTypeProfile<1, 3, [SDTCisVec<0>, 39304eeddc0SDimitry Andric SDTCisSameNumEltsAs<0, 1>, 394fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 2>, 395fe6060f1SDimitry Andric SDTCVecEltisVT<2, i1>, 396fe6060f1SDimitry Andric SDTCisVT<3, XLenVT>]>>; 397fe6060f1SDimitry Andric 39806c3fb27SDimitry Andricdef SDT_RISCVVWIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>, 39906c3fb27SDimitry Andric SDTCisInt<1>, 400fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 1>, 40106c3fb27SDimitry Andric SDTCisOpSmallerThanOp<1, 0>, 402fe6060f1SDimitry Andric SDTCisSameAs<1, 2>, 403bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 404bdd1243dSDimitry Andric SDTCisSameNumEltsAs<1, 4>, 405bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 406bdd1243dSDimitry Andric SDTCisVT<5, XLenVT>]>; 40706c3fb27SDimitry Andricdef riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>; 40806c3fb27SDimitry Andricdef riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>; 40906c3fb27SDimitry Andricdef riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWIntBinOp_VL>; 41006c3fb27SDimitry Andricdef riscv_vwadd_vl : SDNode<"RISCVISD::VWADD_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>; 41106c3fb27SDimitry Andricdef riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>; 41206c3fb27SDimitry Andricdef riscv_vwsub_vl : SDNode<"RISCVISD::VWSUB_VL", SDT_RISCVVWIntBinOp_VL, []>; 41306c3fb27SDimitry Andricdef riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWIntBinOp_VL, []>; 4145f757f3fSDimitry Andricdef riscv_vwsll_vl : SDNode<"RISCVISD::VWSLL_VL", SDT_RISCVVWIntBinOp_VL, []>; 41581ad6265SDimitry Andric 41606c3fb27SDimitry Andricdef SDT_RISCVVWIntTernOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>, 41706c3fb27SDimitry Andric SDTCisInt<1>, 41806c3fb27SDimitry Andric SDTCisSameNumEltsAs<0, 1>, 41906c3fb27SDimitry Andric SDTCisOpSmallerThanOp<1, 0>, 42006c3fb27SDimitry Andric SDTCisSameAs<1, 2>, 42106c3fb27SDimitry Andric SDTCisSameAs<0, 3>, 42206c3fb27SDimitry Andric SDTCisSameNumEltsAs<1, 4>, 42306c3fb27SDimitry Andric SDTCVecEltisVT<4, i1>, 42406c3fb27SDimitry Andric SDTCisVT<5, XLenVT>]>; 42506c3fb27SDimitry Andricdef riscv_vwmacc_vl : SDNode<"RISCVISD::VWMACC_VL", SDT_RISCVVWIntTernOp_VL, [SDNPCommutative]>; 42606c3fb27SDimitry Andricdef riscv_vwmaccu_vl : SDNode<"RISCVISD::VWMACCU_VL", SDT_RISCVVWIntTernOp_VL, [SDNPCommutative]>; 42706c3fb27SDimitry Andricdef riscv_vwmaccsu_vl : SDNode<"RISCVISD::VWMACCSU_VL", SDT_RISCVVWIntTernOp_VL, []>; 42806c3fb27SDimitry Andric 42906c3fb27SDimitry Andricdef SDT_RISCVVWFPBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>, 43006c3fb27SDimitry Andric SDTCisFP<1>, 43106c3fb27SDimitry Andric SDTCisSameNumEltsAs<0, 1>, 43206c3fb27SDimitry Andric SDTCisOpSmallerThanOp<1, 0>, 43306c3fb27SDimitry Andric SDTCisSameAs<1, 2>, 43406c3fb27SDimitry Andric SDTCisSameAs<0, 3>, 43506c3fb27SDimitry Andric SDTCisSameNumEltsAs<1, 4>, 43606c3fb27SDimitry Andric SDTCVecEltisVT<4, i1>, 43706c3fb27SDimitry Andric SDTCisVT<5, XLenVT>]>; 43806c3fb27SDimitry Andricdef riscv_vfwmul_vl : SDNode<"RISCVISD::VFWMUL_VL", SDT_RISCVVWFPBinOp_VL, [SDNPCommutative]>; 43906c3fb27SDimitry Andricdef riscv_vfwadd_vl : SDNode<"RISCVISD::VFWADD_VL", SDT_RISCVVWFPBinOp_VL, [SDNPCommutative]>; 44006c3fb27SDimitry Andricdef riscv_vfwsub_vl : SDNode<"RISCVISD::VFWSUB_VL", SDT_RISCVVWFPBinOp_VL, []>; 44106c3fb27SDimitry Andric 44206c3fb27SDimitry Andricdef SDT_RISCVVNIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>, 44306c3fb27SDimitry Andric SDTCisInt<1>, 444bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 1>, 445bdd1243dSDimitry Andric SDTCisOpSmallerThanOp<0, 1>, 446bdd1243dSDimitry Andric SDTCisSameAs<0, 2>, 447bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 448bdd1243dSDimitry Andric SDTCisSameNumEltsAs<0, 4>, 449bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 450bdd1243dSDimitry Andric SDTCisVT<5, XLenVT>]>; 45106c3fb27SDimitry Andricdef riscv_vnsrl_vl : SDNode<"RISCVISD::VNSRL_VL", SDT_RISCVVNIntBinOp_VL>; 452bdd1243dSDimitry Andric 45306c3fb27SDimitry Andricdef SDT_RISCVVWIntBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>, 45481ad6265SDimitry Andric SDTCisSameAs<0, 1>, 45506c3fb27SDimitry Andric SDTCisInt<2>, 45681ad6265SDimitry Andric SDTCisSameNumEltsAs<1, 2>, 45781ad6265SDimitry Andric SDTCisOpSmallerThanOp<2, 1>, 458bdd1243dSDimitry Andric SDTCisSameAs<0, 3>, 459bdd1243dSDimitry Andric SDTCisSameNumEltsAs<1, 4>, 460bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, 461bdd1243dSDimitry Andric SDTCisVT<5, XLenVT>]>; 46206c3fb27SDimitry Andricdef riscv_vwadd_w_vl : SDNode<"RISCVISD::VWADD_W_VL", SDT_RISCVVWIntBinOpW_VL>; 46306c3fb27SDimitry Andricdef riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWIntBinOpW_VL>; 46406c3fb27SDimitry Andricdef riscv_vwsub_w_vl : SDNode<"RISCVISD::VWSUB_W_VL", SDT_RISCVVWIntBinOpW_VL>; 46506c3fb27SDimitry Andricdef riscv_vwsubu_w_vl : SDNode<"RISCVISD::VWSUBU_W_VL", SDT_RISCVVWIntBinOpW_VL>; 466fe6060f1SDimitry Andric 46706c3fb27SDimitry Andricdef SDT_RISCVVWFPBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>, 46806c3fb27SDimitry Andric SDTCisSameAs<0, 1>, 46906c3fb27SDimitry Andric SDTCisFP<2>, 47006c3fb27SDimitry Andric SDTCisSameNumEltsAs<1, 2>, 47106c3fb27SDimitry Andric SDTCisOpSmallerThanOp<2, 1>, 47206c3fb27SDimitry Andric SDTCisSameAs<0, 3>, 47306c3fb27SDimitry Andric SDTCisSameNumEltsAs<1, 4>, 47406c3fb27SDimitry Andric SDTCVecEltisVT<4, i1>, 47506c3fb27SDimitry Andric SDTCisVT<5, XLenVT>]>; 47606c3fb27SDimitry Andric 47706c3fb27SDimitry Andricdef riscv_vfwadd_w_vl : SDNode<"RISCVISD::VFWADD_W_VL", SDT_RISCVVWFPBinOpW_VL>; 47806c3fb27SDimitry Andricdef riscv_vfwsub_w_vl : SDNode<"RISCVISD::VFWSUB_W_VL", SDT_RISCVVWFPBinOpW_VL>; 47906c3fb27SDimitry Andric 48006c3fb27SDimitry Andricdef SDTRVVVecReduce : SDTypeProfile<1, 6, [ 481349cc55cSDimitry Andric SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 48206c3fb27SDimitry Andric SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT>, 48306c3fb27SDimitry Andric SDTCisVT<6, XLenVT> 484fe6060f1SDimitry Andric]>; 485fe6060f1SDimitry Andric 486bdd1243dSDimitry Andricdef riscv_add_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 487bdd1243dSDimitry Andric node:$E), 488bdd1243dSDimitry Andric (riscv_add_vl node:$A, node:$B, node:$C, 489bdd1243dSDimitry Andric node:$D, node:$E), [{ 490bdd1243dSDimitry Andric return N->hasOneUse(); 491bdd1243dSDimitry Andric}]>; 492bdd1243dSDimitry Andric 493bdd1243dSDimitry Andricdef riscv_sub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 494bdd1243dSDimitry Andric node:$E), 495bdd1243dSDimitry Andric (riscv_sub_vl node:$A, node:$B, node:$C, 496bdd1243dSDimitry Andric node:$D, node:$E), [{ 497bdd1243dSDimitry Andric return N->hasOneUse(); 498bdd1243dSDimitry Andric}]>; 499bdd1243dSDimitry Andric 500bdd1243dSDimitry Andricdef riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 501bdd1243dSDimitry Andric node:$E), 502fe6060f1SDimitry Andric (riscv_mul_vl node:$A, node:$B, node:$C, 503bdd1243dSDimitry Andric node:$D, node:$E), [{ 504fe6060f1SDimitry Andric return N->hasOneUse(); 505fe6060f1SDimitry Andric}]>; 506fe6060f1SDimitry Andric 507bdd1243dSDimitry Andricdef riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 508bdd1243dSDimitry Andric node:$E), 509fe6060f1SDimitry Andric (riscv_vwmul_vl node:$A, node:$B, node:$C, 510bdd1243dSDimitry Andric node:$D, node:$E), [{ 511fe6060f1SDimitry Andric return N->hasOneUse(); 512fe6060f1SDimitry Andric}]>; 513fe6060f1SDimitry Andric 514bdd1243dSDimitry Andricdef riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 515bdd1243dSDimitry Andric node:$E), 516fe6060f1SDimitry Andric (riscv_vwmulu_vl node:$A, node:$B, node:$C, 517bdd1243dSDimitry Andric node:$D, node:$E), [{ 518fe6060f1SDimitry Andric return N->hasOneUse(); 519fe6060f1SDimitry Andric}]>; 520fe6060f1SDimitry Andric 521bdd1243dSDimitry Andricdef riscv_vwmulsu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 522bdd1243dSDimitry Andric node:$E), 52381ad6265SDimitry Andric (riscv_vwmulsu_vl node:$A, node:$B, node:$C, 524bdd1243dSDimitry Andric node:$D, node:$E), [{ 52581ad6265SDimitry Andric return N->hasOneUse(); 52681ad6265SDimitry Andric}]>; 52781ad6265SDimitry Andric 52881ad6265SDimitry Andricdef riscv_sext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 52981ad6265SDimitry Andric (riscv_sext_vl node:$A, node:$B, node:$C), [{ 53081ad6265SDimitry Andric return N->hasOneUse(); 53181ad6265SDimitry Andric}]>; 53281ad6265SDimitry Andric 53381ad6265SDimitry Andricdef riscv_zext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 53481ad6265SDimitry Andric (riscv_zext_vl node:$A, node:$B, node:$C), [{ 53581ad6265SDimitry Andric return N->hasOneUse(); 53681ad6265SDimitry Andric}]>; 53781ad6265SDimitry Andric 53881ad6265SDimitry Andricdef riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 53981ad6265SDimitry Andric (riscv_fpextend_vl node:$A, node:$B, node:$C), [{ 54081ad6265SDimitry Andric return N->hasOneUse(); 54181ad6265SDimitry Andric}]>; 54281ad6265SDimitry Andric 543bdd1243dSDimitry Andricdef riscv_vfmadd_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 544bdd1243dSDimitry Andric node:$E), 545bdd1243dSDimitry Andric (riscv_vfmadd_vl node:$A, node:$B, 546bdd1243dSDimitry Andric node:$C, node:$D, node:$E), [{ 547bdd1243dSDimitry Andric return N->hasOneUse(); 548bdd1243dSDimitry Andric}]>; 549bdd1243dSDimitry Andric 550bdd1243dSDimitry Andricdef riscv_vfnmadd_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 551bdd1243dSDimitry Andric node:$E), 552bdd1243dSDimitry Andric (riscv_vfnmadd_vl node:$A, node:$B, 553bdd1243dSDimitry Andric node:$C, node:$D, node:$E), [{ 554bdd1243dSDimitry Andric return N->hasOneUse(); 555bdd1243dSDimitry Andric}]>; 556bdd1243dSDimitry Andric 557bdd1243dSDimitry Andricdef riscv_vfmsub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 558bdd1243dSDimitry Andric node:$E), 559bdd1243dSDimitry Andric (riscv_vfmsub_vl node:$A, node:$B, 560bdd1243dSDimitry Andric node:$C, node:$D, node:$E), [{ 561bdd1243dSDimitry Andric return N->hasOneUse(); 562bdd1243dSDimitry Andric}]>; 563bdd1243dSDimitry Andric 564bdd1243dSDimitry Andricdef riscv_vfnmsub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D, 565bdd1243dSDimitry Andric node:$E), 566bdd1243dSDimitry Andric (riscv_vfnmsub_vl node:$A, node:$B, 567bdd1243dSDimitry Andric node:$C, node:$D, node:$E), [{ 568bdd1243dSDimitry Andric return N->hasOneUse(); 569bdd1243dSDimitry Andric}]>; 570bdd1243dSDimitry Andric 571fe6060f1SDimitry Andricforeach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 572fe6060f1SDimitry Andric "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 573fe6060f1SDimitry Andric def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 574fe6060f1SDimitry Andric 57581ad6265SDimitry Andric// Give explicit Complexity to prefer simm5/uimm5. 57681ad6265SDimitry Andricdef SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; 57706c3fb27SDimitry Andricdef SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 3>; 57806c3fb27SDimitry Andricdef SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<5>", [], [], 3>; 57906c3fb27SDimitry Andricdef SplatPat_uimm6 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<6>", [], [], 3>; 58081ad6265SDimitry Andricdef SplatPat_simm5_plus1 58106c3fb27SDimitry Andric : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 3>; 58281ad6265SDimitry Andricdef SplatPat_simm5_plus1_nonzero 58306c3fb27SDimitry Andric : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 3>; 58406c3fb27SDimitry Andric 5855f757f3fSDimitry Andric// Selects extends or truncates of splats where we only care about the lowest 8 5865f757f3fSDimitry Andric// bits of each element. 5875f757f3fSDimitry Andricdef Low8BitsSplatPat 5885f757f3fSDimitry Andric : ComplexPattern<vAny, 1, "selectLow8BitsVSplat", [], [], 2>; 58906c3fb27SDimitry Andric 5905f757f3fSDimitry Andric// Ignore the vl operand on vmv_v_f, and vmv_s_f. 5915f757f3fSDimitry Andricdef SplatFPOp : PatFrags<(ops node:$op), 5925f757f3fSDimitry Andric [(riscv_vfmv_v_f_vl undef, node:$op, srcvalue), 5935f757f3fSDimitry Andric (riscv_vfmv_s_f_vl undef, node:$op, srcvalue)]>; 594fe6060f1SDimitry Andric 595fe6060f1SDimitry Andricdef sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 596fe6060f1SDimitry Andricdef sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 597fe6060f1SDimitry Andricdef sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 598fe6060f1SDimitry Andricdef sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 599fe6060f1SDimitry Andric 60006c3fb27SDimitry Andricclass VPatBinaryVL_V<SDPatternOperator vop, 601fe6060f1SDimitry Andric string instruction_name, 60281ad6265SDimitry Andric string suffix, 603fe6060f1SDimitry Andric ValueType result_type, 60481ad6265SDimitry Andric ValueType op1_type, 60581ad6265SDimitry Andric ValueType op2_type, 606fe6060f1SDimitry Andric ValueType mask_type, 60706c3fb27SDimitry Andric int log2sew, 608fe6060f1SDimitry Andric LMULInfo vlmul, 609bdd1243dSDimitry Andric VReg result_reg_class, 61081ad6265SDimitry Andric VReg op1_reg_class, 61106c3fb27SDimitry Andric VReg op2_reg_class, 61206c3fb27SDimitry Andric bit isSEWAware = 0> 61306c3fb27SDimitry Andric : Pat<(result_type (vop 61481ad6265SDimitry Andric (op1_type op1_reg_class:$rs1), 61581ad6265SDimitry Andric (op2_type op2_reg_class:$rs2), 616bdd1243dSDimitry Andric (result_type result_reg_class:$merge), 617349cc55cSDimitry Andric (mask_type V0), 618fe6060f1SDimitry Andric VLOpFrag)), 61906c3fb27SDimitry Andric (!cast<Instruction>( 62006c3fb27SDimitry Andric !if(isSEWAware, 62106c3fb27SDimitry Andric instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK", 62206c3fb27SDimitry Andric instruction_name#"_"#suffix#"_"#vlmul.MX#"_MASK")) 623bdd1243dSDimitry Andric result_reg_class:$merge, 62481ad6265SDimitry Andric op1_reg_class:$rs1, 62581ad6265SDimitry Andric op2_reg_class:$rs2, 62606c3fb27SDimitry Andric (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 62706c3fb27SDimitry Andric 62806c3fb27SDimitry Andricclass VPatBinaryVL_V_RM<SDPatternOperator vop, 62906c3fb27SDimitry Andric string instruction_name, 63006c3fb27SDimitry Andric string suffix, 63106c3fb27SDimitry Andric ValueType result_type, 63206c3fb27SDimitry Andric ValueType op1_type, 63306c3fb27SDimitry Andric ValueType op2_type, 63406c3fb27SDimitry Andric ValueType mask_type, 63506c3fb27SDimitry Andric int log2sew, 63606c3fb27SDimitry Andric LMULInfo vlmul, 63706c3fb27SDimitry Andric VReg result_reg_class, 63806c3fb27SDimitry Andric VReg op1_reg_class, 63906c3fb27SDimitry Andric VReg op2_reg_class, 64006c3fb27SDimitry Andric bit isSEWAware = 0> 64106c3fb27SDimitry Andric : Pat<(result_type (vop 64206c3fb27SDimitry Andric (op1_type op1_reg_class:$rs1), 64306c3fb27SDimitry Andric (op2_type op2_reg_class:$rs2), 64406c3fb27SDimitry Andric (result_type result_reg_class:$merge), 64506c3fb27SDimitry Andric (mask_type V0), 64606c3fb27SDimitry Andric VLOpFrag)), 64706c3fb27SDimitry Andric (!cast<Instruction>( 64806c3fb27SDimitry Andric !if(isSEWAware, 64906c3fb27SDimitry Andric instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK", 65006c3fb27SDimitry Andric instruction_name#"_"#suffix#"_"#vlmul.MX#"_MASK")) 65106c3fb27SDimitry Andric result_reg_class:$merge, 65206c3fb27SDimitry Andric op1_reg_class:$rs1, 65306c3fb27SDimitry Andric op2_reg_class:$rs2, 65406c3fb27SDimitry Andric (mask_type V0), 65506c3fb27SDimitry Andric // Value to indicate no rounding mode change in 65606c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 65706c3fb27SDimitry Andric FRM_DYN, 65806c3fb27SDimitry Andric GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 659fe6060f1SDimitry Andric 660bdd1243dSDimitry Andricmulticlass VPatTiedBinaryNoMaskVL_V<SDNode vop, 661bdd1243dSDimitry Andric string instruction_name, 662bdd1243dSDimitry Andric string suffix, 663bdd1243dSDimitry Andric ValueType result_type, 664bdd1243dSDimitry Andric ValueType op2_type, 665bdd1243dSDimitry Andric int sew, 666bdd1243dSDimitry Andric LMULInfo vlmul, 667bdd1243dSDimitry Andric VReg result_reg_class, 668bdd1243dSDimitry Andric VReg op2_reg_class> { 669bdd1243dSDimitry Andric def : Pat<(result_type (vop 670bdd1243dSDimitry Andric (result_type result_reg_class:$rs1), 671bdd1243dSDimitry Andric (op2_type op2_reg_class:$rs2), 672bdd1243dSDimitry Andric srcvalue, 673bdd1243dSDimitry Andric true_mask, 674bdd1243dSDimitry Andric VLOpFrag)), 675bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED") 676bdd1243dSDimitry Andric result_reg_class:$rs1, 677bdd1243dSDimitry Andric op2_reg_class:$rs2, 678bdd1243dSDimitry Andric GPR:$vl, sew, TAIL_AGNOSTIC)>; 679bdd1243dSDimitry Andric // Tail undisturbed 680cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl true_mask, 681bdd1243dSDimitry Andric (result_type (vop 682bdd1243dSDimitry Andric result_reg_class:$rs1, 683bdd1243dSDimitry Andric (op2_type op2_reg_class:$rs2), 684bdd1243dSDimitry Andric srcvalue, 685bdd1243dSDimitry Andric true_mask, 686bdd1243dSDimitry Andric VLOpFrag)), 687cb14a3feSDimitry Andric result_reg_class:$rs1, result_reg_class:$rs1, VLOpFrag), 688bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED") 689bdd1243dSDimitry Andric result_reg_class:$rs1, 690bdd1243dSDimitry Andric op2_reg_class:$rs2, 69106c3fb27SDimitry Andric GPR:$vl, sew, TU_MU)>; 692bdd1243dSDimitry Andric} 693bdd1243dSDimitry Andric 69406c3fb27SDimitry Andricmulticlass VPatTiedBinaryNoMaskVL_V_RM<SDNode vop, 69506c3fb27SDimitry Andric string instruction_name, 69606c3fb27SDimitry Andric string suffix, 69706c3fb27SDimitry Andric ValueType result_type, 69806c3fb27SDimitry Andric ValueType op2_type, 69906c3fb27SDimitry Andric int sew, 70006c3fb27SDimitry Andric LMULInfo vlmul, 70106c3fb27SDimitry Andric VReg result_reg_class, 70206c3fb27SDimitry Andric VReg op2_reg_class> { 70306c3fb27SDimitry Andric def : Pat<(result_type (vop 70406c3fb27SDimitry Andric (result_type result_reg_class:$rs1), 70506c3fb27SDimitry Andric (op2_type op2_reg_class:$rs2), 70606c3fb27SDimitry Andric srcvalue, 70706c3fb27SDimitry Andric true_mask, 70806c3fb27SDimitry Andric VLOpFrag)), 70906c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED") 71006c3fb27SDimitry Andric result_reg_class:$rs1, 71106c3fb27SDimitry Andric op2_reg_class:$rs2, 71206c3fb27SDimitry Andric // Value to indicate no rounding mode change in 71306c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 71406c3fb27SDimitry Andric FRM_DYN, 71506c3fb27SDimitry Andric GPR:$vl, sew, TAIL_AGNOSTIC)>; 71606c3fb27SDimitry Andric // Tail undisturbed 717cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl true_mask, 71806c3fb27SDimitry Andric (result_type (vop 71906c3fb27SDimitry Andric result_reg_class:$rs1, 72006c3fb27SDimitry Andric (op2_type op2_reg_class:$rs2), 72106c3fb27SDimitry Andric srcvalue, 72206c3fb27SDimitry Andric true_mask, 72306c3fb27SDimitry Andric VLOpFrag)), 724cb14a3feSDimitry Andric result_reg_class:$rs1, result_reg_class:$rs1, VLOpFrag), 72506c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED") 72606c3fb27SDimitry Andric result_reg_class:$rs1, 72706c3fb27SDimitry Andric op2_reg_class:$rs2, 72806c3fb27SDimitry Andric // Value to indicate no rounding mode change in 72906c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 73006c3fb27SDimitry Andric FRM_DYN, 73106c3fb27SDimitry Andric GPR:$vl, sew, TU_MU)>; 73206c3fb27SDimitry Andric} 73306c3fb27SDimitry Andric 73406c3fb27SDimitry Andricclass VPatBinaryVL_XI<SDPatternOperator vop, 735fe6060f1SDimitry Andric string instruction_name, 736fe6060f1SDimitry Andric string suffix, 737fe6060f1SDimitry Andric ValueType result_type, 73881ad6265SDimitry Andric ValueType vop1_type, 73981ad6265SDimitry Andric ValueType vop2_type, 740fe6060f1SDimitry Andric ValueType mask_type, 74106c3fb27SDimitry Andric int log2sew, 742fe6060f1SDimitry Andric LMULInfo vlmul, 743bdd1243dSDimitry Andric VReg result_reg_class, 744fe6060f1SDimitry Andric VReg vop_reg_class, 745fe6060f1SDimitry Andric ComplexPattern SplatPatKind, 74606c3fb27SDimitry Andric DAGOperand xop_kind, 74706c3fb27SDimitry Andric bit isSEWAware = 0> 74806c3fb27SDimitry Andric : Pat<(result_type (vop 74981ad6265SDimitry Andric (vop1_type vop_reg_class:$rs1), 75081ad6265SDimitry Andric (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))), 751bdd1243dSDimitry Andric (result_type result_reg_class:$merge), 752349cc55cSDimitry Andric (mask_type V0), 753fe6060f1SDimitry Andric VLOpFrag)), 75406c3fb27SDimitry Andric (!cast<Instruction>( 75506c3fb27SDimitry Andric !if(isSEWAware, 75606c3fb27SDimitry Andric instruction_name#_#suffix#_#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK", 75706c3fb27SDimitry Andric instruction_name#_#suffix#_#vlmul.MX#"_MASK")) 758bdd1243dSDimitry Andric result_reg_class:$merge, 759fe6060f1SDimitry Andric vop_reg_class:$rs1, 760fe6060f1SDimitry Andric xop_kind:$rs2, 76106c3fb27SDimitry Andric (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 762fe6060f1SDimitry Andric 76306c3fb27SDimitry Andricmulticlass VPatBinaryVL_VV_VX<SDPatternOperator vop, string instruction_name, 76406c3fb27SDimitry Andric list<VTypeInfo> vtilist = AllIntegerVectors, 76506c3fb27SDimitry Andric bit isSEWAware = 0> { 76606c3fb27SDimitry Andric foreach vti = vtilist in { 76706c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 76806c3fb27SDimitry Andric def : VPatBinaryVL_V<vop, instruction_name, "VV", 76981ad6265SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 770bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass, 77106c3fb27SDimitry Andric vti.RegClass, isSEWAware>; 77206c3fb27SDimitry Andric def : VPatBinaryVL_XI<vop, instruction_name, "VX", 77381ad6265SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 774bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass, 77506c3fb27SDimitry Andric SplatPat, GPR, isSEWAware>; 77606c3fb27SDimitry Andric } 777fe6060f1SDimitry Andric } 778fe6060f1SDimitry Andric} 779fe6060f1SDimitry Andric 78006c3fb27SDimitry Andricmulticlass VPatBinaryVL_VV_VX_VI<SDPatternOperator vop, string instruction_name, 781fe6060f1SDimitry Andric Operand ImmType = simm5> 782fe6060f1SDimitry Andric : VPatBinaryVL_VV_VX<vop, instruction_name> { 783fe6060f1SDimitry Andric foreach vti = AllIntegerVectors in { 78406c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 78506c3fb27SDimitry Andric def : VPatBinaryVL_XI<vop, instruction_name, "VI", 78681ad6265SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 787bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass, 788fe6060f1SDimitry Andric !cast<ComplexPattern>(SplatPat#_#ImmType), 789fe6060f1SDimitry Andric ImmType>; 790fe6060f1SDimitry Andric } 791fe6060f1SDimitry Andric} 792fe6060f1SDimitry Andric 79306c3fb27SDimitry Andricmulticlass VPatBinaryWVL_VV_VX<SDPatternOperator vop, string instruction_name> { 794fe6060f1SDimitry Andric foreach VtiToWti = AllWidenableIntVectors in { 795fe6060f1SDimitry Andric defvar vti = VtiToWti.Vti; 796fe6060f1SDimitry Andric defvar wti = VtiToWti.Wti; 79706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 79806c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 79906c3fb27SDimitry Andric def : VPatBinaryVL_V<vop, instruction_name, "VV", 80081ad6265SDimitry Andric wti.Vector, vti.Vector, vti.Vector, vti.Mask, 801bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass, 802bdd1243dSDimitry Andric vti.RegClass>; 80306c3fb27SDimitry Andric def : VPatBinaryVL_XI<vop, instruction_name, "VX", 80481ad6265SDimitry Andric wti.Vector, vti.Vector, vti.Vector, vti.Mask, 805bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass, 806bdd1243dSDimitry Andric SplatPat, GPR>; 80781ad6265SDimitry Andric } 80881ad6265SDimitry Andric } 80906c3fb27SDimitry Andric} 81006c3fb27SDimitry Andric 81106c3fb27SDimitry Andricmulticlass VPatBinaryWVL_VV_VX_WV_WX<SDPatternOperator vop, SDNode vop_w, 81281ad6265SDimitry Andric string instruction_name> 81381ad6265SDimitry Andric : VPatBinaryWVL_VV_VX<vop, instruction_name> { 81481ad6265SDimitry Andric foreach VtiToWti = AllWidenableIntVectors in { 81581ad6265SDimitry Andric defvar vti = VtiToWti.Vti; 81681ad6265SDimitry Andric defvar wti = VtiToWti.Wti; 81706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 81806c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 819bdd1243dSDimitry Andric defm : VPatTiedBinaryNoMaskVL_V<vop_w, instruction_name, "WV", 820bdd1243dSDimitry Andric wti.Vector, vti.Vector, vti.Log2SEW, 821bdd1243dSDimitry Andric vti.LMul, wti.RegClass, vti.RegClass>; 82206c3fb27SDimitry Andric def : VPatBinaryVL_V<vop_w, instruction_name, "WV", 82381ad6265SDimitry Andric wti.Vector, wti.Vector, vti.Vector, vti.Mask, 824bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass, 825bdd1243dSDimitry Andric vti.RegClass>; 82606c3fb27SDimitry Andric def : VPatBinaryVL_XI<vop_w, instruction_name, "WX", 82781ad6265SDimitry Andric wti.Vector, wti.Vector, vti.Vector, vti.Mask, 828bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass, 829bdd1243dSDimitry Andric SplatPat, GPR>; 830bdd1243dSDimitry Andric } 831bdd1243dSDimitry Andric } 83206c3fb27SDimitry Andric} 833bdd1243dSDimitry Andric 83406c3fb27SDimitry Andricmulticlass VPatBinaryNVL_WV_WX_WI<SDPatternOperator vop, string instruction_name> { 835bdd1243dSDimitry Andric foreach VtiToWti = AllWidenableIntVectors in { 836bdd1243dSDimitry Andric defvar vti = VtiToWti.Vti; 837bdd1243dSDimitry Andric defvar wti = VtiToWti.Wti; 83806c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 83906c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 84006c3fb27SDimitry Andric def : VPatBinaryVL_V<vop, instruction_name, "WV", 841bdd1243dSDimitry Andric vti.Vector, wti.Vector, vti.Vector, vti.Mask, 842bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, wti.RegClass, 843bdd1243dSDimitry Andric vti.RegClass>; 84406c3fb27SDimitry Andric def : VPatBinaryVL_XI<vop, instruction_name, "WX", 845bdd1243dSDimitry Andric vti.Vector, wti.Vector, vti.Vector, vti.Mask, 846bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, wti.RegClass, 847bdd1243dSDimitry Andric SplatPat, GPR>; 84806c3fb27SDimitry Andric def : VPatBinaryVL_XI<vop, instruction_name, "WI", 849bdd1243dSDimitry Andric vti.Vector, wti.Vector, vti.Vector, vti.Mask, 850bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, wti.RegClass, 851bdd1243dSDimitry Andric !cast<ComplexPattern>(SplatPat#_#uimm5), 852bdd1243dSDimitry Andric uimm5>; 853fe6060f1SDimitry Andric } 854fe6060f1SDimitry Andric } 85506c3fb27SDimitry Andric} 856fe6060f1SDimitry Andric 85706c3fb27SDimitry Andricclass VPatBinaryVL_VF<SDPatternOperator vop, 858fe6060f1SDimitry Andric string instruction_name, 859fe6060f1SDimitry Andric ValueType result_type, 86006c3fb27SDimitry Andric ValueType vop1_type, 86106c3fb27SDimitry Andric ValueType vop2_type, 862fe6060f1SDimitry Andric ValueType mask_type, 86306c3fb27SDimitry Andric int log2sew, 864fe6060f1SDimitry Andric LMULInfo vlmul, 865bdd1243dSDimitry Andric VReg result_reg_class, 866fe6060f1SDimitry Andric VReg vop_reg_class, 86706c3fb27SDimitry Andric RegisterClass scalar_reg_class, 86806c3fb27SDimitry Andric bit isSEWAware = 0> 86906c3fb27SDimitry Andric : Pat<(result_type (vop (vop1_type vop_reg_class:$rs1), 87006c3fb27SDimitry Andric (vop2_type (SplatFPOp scalar_reg_class:$rs2)), 871bdd1243dSDimitry Andric (result_type result_reg_class:$merge), 87204eeddc0SDimitry Andric (mask_type V0), 87304eeddc0SDimitry Andric VLOpFrag)), 87406c3fb27SDimitry Andric (!cast<Instruction>( 87506c3fb27SDimitry Andric !if(isSEWAware, 87606c3fb27SDimitry Andric instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK", 87706c3fb27SDimitry Andric instruction_name#"_"#vlmul.MX#"_MASK")) 878bdd1243dSDimitry Andric result_reg_class:$merge, 87904eeddc0SDimitry Andric vop_reg_class:$rs1, 88004eeddc0SDimitry Andric scalar_reg_class:$rs2, 88106c3fb27SDimitry Andric (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 882fe6060f1SDimitry Andric 88306c3fb27SDimitry Andricclass VPatBinaryVL_VF_RM<SDPatternOperator vop, 88406c3fb27SDimitry Andric string instruction_name, 88506c3fb27SDimitry Andric ValueType result_type, 88606c3fb27SDimitry Andric ValueType vop1_type, 88706c3fb27SDimitry Andric ValueType vop2_type, 88806c3fb27SDimitry Andric ValueType mask_type, 88906c3fb27SDimitry Andric int log2sew, 89006c3fb27SDimitry Andric LMULInfo vlmul, 89106c3fb27SDimitry Andric VReg result_reg_class, 89206c3fb27SDimitry Andric VReg vop_reg_class, 89306c3fb27SDimitry Andric RegisterClass scalar_reg_class, 89406c3fb27SDimitry Andric bit isSEWAware = 0> 89506c3fb27SDimitry Andric : Pat<(result_type (vop (vop1_type vop_reg_class:$rs1), 89606c3fb27SDimitry Andric (vop2_type (SplatFPOp scalar_reg_class:$rs2)), 89706c3fb27SDimitry Andric (result_type result_reg_class:$merge), 89806c3fb27SDimitry Andric (mask_type V0), 89906c3fb27SDimitry Andric VLOpFrag)), 90006c3fb27SDimitry Andric (!cast<Instruction>( 90106c3fb27SDimitry Andric !if(isSEWAware, 90206c3fb27SDimitry Andric instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK", 90306c3fb27SDimitry Andric instruction_name#"_"#vlmul.MX#"_MASK")) 90406c3fb27SDimitry Andric result_reg_class:$merge, 90506c3fb27SDimitry Andric vop_reg_class:$rs1, 90606c3fb27SDimitry Andric scalar_reg_class:$rs2, 90706c3fb27SDimitry Andric (mask_type V0), 90806c3fb27SDimitry Andric // Value to indicate no rounding mode change in 90906c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 91006c3fb27SDimitry Andric FRM_DYN, 91106c3fb27SDimitry Andric GPR:$vl, log2sew, TAIL_AGNOSTIC)>; 91206c3fb27SDimitry Andric 91306c3fb27SDimitry Andricmulticlass VPatBinaryFPVL_VV_VF<SDPatternOperator vop, string instruction_name, 91406c3fb27SDimitry Andric bit isSEWAware = 0> { 915fe6060f1SDimitry Andric foreach vti = AllFloatVectors in { 91606c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 91706c3fb27SDimitry Andric def : VPatBinaryVL_V<vop, instruction_name, "VV", 91881ad6265SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 919bdd1243dSDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass, 92006c3fb27SDimitry Andric vti.RegClass, isSEWAware>; 92106c3fb27SDimitry Andric def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 92206c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 92306c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass, 92406c3fb27SDimitry Andric vti.ScalarRegClass, isSEWAware>; 92506c3fb27SDimitry Andric } 926fe6060f1SDimitry Andric } 927fe6060f1SDimitry Andric} 928fe6060f1SDimitry Andric 92906c3fb27SDimitry Andricmulticlass VPatBinaryFPVL_VV_VF_RM<SDPatternOperator vop, string instruction_name, 93006c3fb27SDimitry Andric bit isSEWAware = 0> { 93106c3fb27SDimitry Andric foreach vti = AllFloatVectors in { 93206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 93306c3fb27SDimitry Andric def : VPatBinaryVL_V_RM<vop, instruction_name, "VV", 93406c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 93506c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass, 93606c3fb27SDimitry Andric vti.RegClass, isSEWAware>; 93706c3fb27SDimitry Andric def : VPatBinaryVL_VF_RM<vop, instruction_name#"_V"#vti.ScalarSuffix, 93806c3fb27SDimitry Andric vti.Vector, vti.Vector, vti.Vector, vti.Mask, 93906c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass, 94006c3fb27SDimitry Andric vti.ScalarRegClass, isSEWAware>; 94106c3fb27SDimitry Andric } 94206c3fb27SDimitry Andric } 94306c3fb27SDimitry Andric} 94406c3fb27SDimitry Andric 94506c3fb27SDimitry Andricmulticlass VPatBinaryFPVL_R_VF<SDPatternOperator vop, string instruction_name, 94606c3fb27SDimitry Andric bit isSEWAware = 0> { 94704eeddc0SDimitry Andric foreach fvti = AllFloatVectors in { 94806c3fb27SDimitry Andric let Predicates = GetVTypePredicates<fvti>.Predicates in 949fe6060f1SDimitry Andric def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 950fe6060f1SDimitry Andric fvti.RegClass:$rs1, 951bdd1243dSDimitry Andric (fvti.Vector fvti.RegClass:$merge), 95204eeddc0SDimitry Andric (fvti.Mask V0), 95304eeddc0SDimitry Andric VLOpFrag)), 95406c3fb27SDimitry Andric (!cast<Instruction>( 95506c3fb27SDimitry Andric !if(isSEWAware, 95606c3fb27SDimitry Andric instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK", 95706c3fb27SDimitry Andric instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")) 958bdd1243dSDimitry Andric fvti.RegClass:$merge, 95904eeddc0SDimitry Andric fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 96004eeddc0SDimitry Andric (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 96104eeddc0SDimitry Andric } 962fe6060f1SDimitry Andric} 963fe6060f1SDimitry Andric 96406c3fb27SDimitry Andricmulticlass VPatBinaryFPVL_R_VF_RM<SDPatternOperator vop, string instruction_name, 96506c3fb27SDimitry Andric bit isSEWAware = 0> { 96606c3fb27SDimitry Andric foreach fvti = AllFloatVectors in { 96706c3fb27SDimitry Andric let Predicates = GetVTypePredicates<fvti>.Predicates in 96806c3fb27SDimitry Andric def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 96906c3fb27SDimitry Andric fvti.RegClass:$rs1, 97006c3fb27SDimitry Andric (fvti.Vector fvti.RegClass:$merge), 97106c3fb27SDimitry Andric (fvti.Mask V0), 97206c3fb27SDimitry Andric VLOpFrag)), 97306c3fb27SDimitry Andric (!cast<Instruction>( 97406c3fb27SDimitry Andric !if(isSEWAware, 97506c3fb27SDimitry Andric instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK", 97606c3fb27SDimitry Andric instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")) 97706c3fb27SDimitry Andric fvti.RegClass:$merge, 97806c3fb27SDimitry Andric fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 97906c3fb27SDimitry Andric (fvti.Mask V0), 98006c3fb27SDimitry Andric // Value to indicate no rounding mode change in 98106c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 98206c3fb27SDimitry Andric FRM_DYN, 98306c3fb27SDimitry Andric GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 98406c3fb27SDimitry Andric } 98506c3fb27SDimitry Andric} 98606c3fb27SDimitry Andric 987fe6060f1SDimitry Andricmulticlass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 988fe6060f1SDimitry Andric CondCode cc> { 989fe6060f1SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 990fe6060f1SDimitry Andric vti.RegClass:$rs2, cc, 991bdd1243dSDimitry Andric VR:$merge, 99281ad6265SDimitry Andric (vti.Mask V0), 993fe6060f1SDimitry Andric VLOpFrag)), 99481ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 995bdd1243dSDimitry Andric VR:$merge, 99681ad6265SDimitry Andric vti.RegClass:$rs1, 99781ad6265SDimitry Andric vti.RegClass:$rs2, 99881ad6265SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 999fe6060f1SDimitry Andric} 1000fe6060f1SDimitry Andric 1001fe6060f1SDimitry Andric// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 1002fe6060f1SDimitry Andricmulticlass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 100381ad6265SDimitry Andric CondCode cc, CondCode invcc> 100481ad6265SDimitry Andric : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 1005fe6060f1SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 1006fe6060f1SDimitry Andric vti.RegClass:$rs1, invcc, 1007bdd1243dSDimitry Andric VR:$merge, 100881ad6265SDimitry Andric (vti.Mask V0), 1009fe6060f1SDimitry Andric VLOpFrag)), 101081ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 1011bdd1243dSDimitry Andric VR:$merge, vti.RegClass:$rs1, 101281ad6265SDimitry Andric vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1013fe6060f1SDimitry Andric} 1014fe6060f1SDimitry Andric 1015fe6060f1SDimitry Andricmulticlass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 1016fe6060f1SDimitry Andric CondCode cc, CondCode invcc> { 101781ad6265SDimitry Andric defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); 1018fe6060f1SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 1019fe6060f1SDimitry Andric (SplatPat (XLenVT GPR:$rs2)), cc, 1020bdd1243dSDimitry Andric VR:$merge, 102181ad6265SDimitry Andric (vti.Mask V0), 1022fe6060f1SDimitry Andric VLOpFrag)), 1023bdd1243dSDimitry Andric (instruction_masked VR:$merge, vti.RegClass:$rs1, 102481ad6265SDimitry Andric GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1025fe6060f1SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 1026fe6060f1SDimitry Andric (vti.Vector vti.RegClass:$rs1), invcc, 1027bdd1243dSDimitry Andric VR:$merge, 102881ad6265SDimitry Andric (vti.Mask V0), 1029fe6060f1SDimitry Andric VLOpFrag)), 1030bdd1243dSDimitry Andric (instruction_masked VR:$merge, vti.RegClass:$rs1, 103181ad6265SDimitry Andric GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1032fe6060f1SDimitry Andric} 1033fe6060f1SDimitry Andric 1034fe6060f1SDimitry Andricmulticlass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 1035fe6060f1SDimitry Andric CondCode cc, CondCode invcc> { 103681ad6265SDimitry Andric defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 1037fe6060f1SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 1038fe6060f1SDimitry Andric (SplatPat_simm5 simm5:$rs2), cc, 1039bdd1243dSDimitry Andric VR:$merge, 104081ad6265SDimitry Andric (vti.Mask V0), 1041fe6060f1SDimitry Andric VLOpFrag)), 1042bdd1243dSDimitry Andric (instruction_masked VR:$merge, vti.RegClass:$rs1, 104381ad6265SDimitry Andric XLenVT:$rs2, (vti.Mask V0), GPR:$vl, 104481ad6265SDimitry Andric vti.Log2SEW)>; 104581ad6265SDimitry Andric 104681ad6265SDimitry Andric // FIXME: Can do some canonicalization to remove these patterns. 1047fe6060f1SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 1048fe6060f1SDimitry Andric (vti.Vector vti.RegClass:$rs1), invcc, 1049bdd1243dSDimitry Andric VR:$merge, 105081ad6265SDimitry Andric (vti.Mask V0), 1051fe6060f1SDimitry Andric VLOpFrag)), 1052bdd1243dSDimitry Andric (instruction_masked VR:$merge, vti.RegClass:$rs1, 105381ad6265SDimitry Andric simm5:$rs2, (vti.Mask V0), GPR:$vl, 105481ad6265SDimitry Andric vti.Log2SEW)>; 1055fe6060f1SDimitry Andric} 1056fe6060f1SDimitry Andric 105781ad6265SDimitry Andricmulticlass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti, 105881ad6265SDimitry Andric string instruction_name, 105981ad6265SDimitry Andric CondCode cc, CondCode invcc, 106081ad6265SDimitry Andric ComplexPattern splatpat_kind> { 106181ad6265SDimitry Andric defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 1062fe6060f1SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 1063fe6060f1SDimitry Andric (splatpat_kind simm5:$rs2), cc, 1064bdd1243dSDimitry Andric VR:$merge, 106581ad6265SDimitry Andric (vti.Mask V0), 1066fe6060f1SDimitry Andric VLOpFrag)), 1067bdd1243dSDimitry Andric (instruction_masked VR:$merge, vti.RegClass:$rs1, 106881ad6265SDimitry Andric (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 106981ad6265SDimitry Andric vti.Log2SEW)>; 107081ad6265SDimitry Andric 107181ad6265SDimitry Andric // FIXME: Can do some canonicalization to remove these patterns. 107281ad6265SDimitry Andric def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), 107381ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs1), invcc, 1074bdd1243dSDimitry Andric VR:$merge, 107581ad6265SDimitry Andric (vti.Mask V0), 107681ad6265SDimitry Andric VLOpFrag)), 1077bdd1243dSDimitry Andric (instruction_masked VR:$merge, vti.RegClass:$rs1, 107881ad6265SDimitry Andric (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 107981ad6265SDimitry Andric vti.Log2SEW)>; 1080fe6060f1SDimitry Andric} 1081fe6060f1SDimitry Andric 108206c3fb27SDimitry Andricmulticlass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc, 1083fe6060f1SDimitry Andric string inst_name, 1084fe6060f1SDimitry Andric string swapped_op_inst_name> { 1085fe6060f1SDimitry Andric foreach fvti = AllFloatVectors in { 108606c3fb27SDimitry Andric let Predicates = GetVTypePredicates<fvti>.Predicates in { 108706c3fb27SDimitry Andric def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1), 1088fe6060f1SDimitry Andric fvti.RegClass:$rs2, 1089fe6060f1SDimitry Andric cc, 1090bdd1243dSDimitry Andric VR:$merge, 109181ad6265SDimitry Andric (fvti.Mask V0), 1092fe6060f1SDimitry Andric VLOpFrag)), 109381ad6265SDimitry Andric (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX#"_MASK") 1094bdd1243dSDimitry Andric VR:$merge, fvti.RegClass:$rs1, 109581ad6265SDimitry Andric fvti.RegClass:$rs2, (fvti.Mask V0), 109681ad6265SDimitry Andric GPR:$vl, fvti.Log2SEW)>; 109706c3fb27SDimitry Andric def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1), 1098fe6060f1SDimitry Andric (SplatFPOp fvti.ScalarRegClass:$rs2), 1099fe6060f1SDimitry Andric cc, 1100bdd1243dSDimitry Andric VR:$merge, 110181ad6265SDimitry Andric (fvti.Mask V0), 1102fe6060f1SDimitry Andric VLOpFrag)), 110381ad6265SDimitry Andric (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 1104bdd1243dSDimitry Andric VR:$merge, fvti.RegClass:$rs1, 110581ad6265SDimitry Andric fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 1106fe6060f1SDimitry Andric GPR:$vl, fvti.Log2SEW)>; 110706c3fb27SDimitry Andric def : Pat<(fvti.Mask (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 1108fe6060f1SDimitry Andric (fvti.Vector fvti.RegClass:$rs1), 1109fe6060f1SDimitry Andric cc, 1110bdd1243dSDimitry Andric VR:$merge, 111181ad6265SDimitry Andric (fvti.Mask V0), 1112fe6060f1SDimitry Andric VLOpFrag)), 111381ad6265SDimitry Andric (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 1114bdd1243dSDimitry Andric VR:$merge, fvti.RegClass:$rs1, 111581ad6265SDimitry Andric fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 1116fe6060f1SDimitry Andric GPR:$vl, fvti.Log2SEW)>; 1117fe6060f1SDimitry Andric } 1118fe6060f1SDimitry Andric } 111906c3fb27SDimitry Andric} 1120fe6060f1SDimitry Andric 1121bdd1243dSDimitry Andricmulticlass VPatExtendVL_V<SDNode vop, string inst_name, string suffix, 1122fe6060f1SDimitry Andric list <VTypeInfoToFraction> fraction_list> { 1123fe6060f1SDimitry Andric foreach vtiTofti = fraction_list in { 1124fe6060f1SDimitry Andric defvar vti = vtiTofti.Vti; 1125fe6060f1SDimitry Andric defvar fti = vtiTofti.Fti; 112606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 112706c3fb27SDimitry Andric GetVTypePredicates<fti>.Predicates) in 1128fe6060f1SDimitry Andric def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 112981ad6265SDimitry Andric (fti.Mask V0), VLOpFrag)), 113081ad6265SDimitry Andric (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK") 113181ad6265SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 113281ad6265SDimitry Andric fti.RegClass:$rs2, 1133bdd1243dSDimitry Andric (fti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 1134fe6060f1SDimitry Andric } 1135fe6060f1SDimitry Andric} 1136fe6060f1SDimitry Andric 1137bdd1243dSDimitry Andric// Single width converting 1138bdd1243dSDimitry Andric 113906c3fb27SDimitry Andricmulticlass VPatConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> { 1140fe6060f1SDimitry Andric foreach fvti = AllFloatVectors in { 1141fe6060f1SDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 114206c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 114306c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 1144fe6060f1SDimitry Andric def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 114581ad6265SDimitry Andric (fvti.Mask V0), 1146fe6060f1SDimitry Andric VLOpFrag)), 114781ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 114881ad6265SDimitry Andric (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1149bdd1243dSDimitry Andric (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TA_MA)>; 1150fe6060f1SDimitry Andric } 1151fe6060f1SDimitry Andric} 1152fe6060f1SDimitry Andric 115306c3fb27SDimitry Andricmulticlass VPatConvertFP2IVL_V_RM<SDPatternOperator vop, string instruction_name> { 1154bdd1243dSDimitry Andric foreach fvti = AllFloatVectors in { 1155bdd1243dSDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 115606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 115706c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 115806c3fb27SDimitry Andric def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 115906c3fb27SDimitry Andric (fvti.Mask V0), 116006c3fb27SDimitry Andric VLOpFrag)), 116106c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 116206c3fb27SDimitry Andric (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 116306c3fb27SDimitry Andric (fvti.Mask V0), 116406c3fb27SDimitry Andric // Value to indicate no rounding mode change in 116506c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 116606c3fb27SDimitry Andric FRM_DYN, 116706c3fb27SDimitry Andric GPR:$vl, ivti.Log2SEW, TA_MA)>; 116806c3fb27SDimitry Andric } 116906c3fb27SDimitry Andric} 117006c3fb27SDimitry Andric 117106c3fb27SDimitry Andric 117206c3fb27SDimitry Andricmulticlass VPatConvertFP2I_RM_VL_V<SDPatternOperator vop, string instruction_name> { 117306c3fb27SDimitry Andric foreach fvti = AllFloatVectors in { 117406c3fb27SDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 117506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 117606c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 1177bdd1243dSDimitry Andric def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 1178bdd1243dSDimitry Andric (fvti.Mask V0), (XLenVT timm:$frm), 1179bdd1243dSDimitry Andric VLOpFrag)), 1180bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 1181bdd1243dSDimitry Andric (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1182bdd1243dSDimitry Andric (fvti.Mask V0), timm:$frm, GPR:$vl, ivti.Log2SEW, 1183bdd1243dSDimitry Andric TA_MA)>; 1184bdd1243dSDimitry Andric } 1185bdd1243dSDimitry Andric} 1186bdd1243dSDimitry Andric 118706c3fb27SDimitry Andricmulticlass VPatConvertI2FPVL_V_RM<SDPatternOperator vop, string instruction_name> { 1188fe6060f1SDimitry Andric foreach fvti = AllFloatVectors in { 1189fe6060f1SDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 119006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 119106c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 1192fe6060f1SDimitry Andric def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 119381ad6265SDimitry Andric (ivti.Mask V0), 1194fe6060f1SDimitry Andric VLOpFrag)), 119581ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 119681ad6265SDimitry Andric (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 119706c3fb27SDimitry Andric (ivti.Mask V0), 119806c3fb27SDimitry Andric // Value to indicate no rounding mode change in 119906c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 120006c3fb27SDimitry Andric FRM_DYN, 120106c3fb27SDimitry Andric GPR:$vl, fvti.Log2SEW, TA_MA)>; 1202fe6060f1SDimitry Andric } 1203fe6060f1SDimitry Andric} 1204fe6060f1SDimitry Andric 1205bdd1243dSDimitry Andricmulticlass VPatConvertI2FP_RM_VL_V<SDNode vop, string instruction_name> { 1206bdd1243dSDimitry Andric foreach fvti = AllFloatVectors in { 1207bdd1243dSDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 120806c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 120906c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 1210bdd1243dSDimitry Andric def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 1211bdd1243dSDimitry Andric (ivti.Mask V0), (XLenVT timm:$frm), 1212bdd1243dSDimitry Andric VLOpFrag)), 1213bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 1214bdd1243dSDimitry Andric (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 1215bdd1243dSDimitry Andric (ivti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>; 1216bdd1243dSDimitry Andric } 1217bdd1243dSDimitry Andric} 1218bdd1243dSDimitry Andric 1219bdd1243dSDimitry Andric// Widening converting 1220bdd1243dSDimitry Andric 122106c3fb27SDimitry Andricmulticlass VPatWConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> { 1222fe6060f1SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 1223fe6060f1SDimitry Andric defvar fvti = fvtiToFWti.Vti; 1224fe6060f1SDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 122506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 122606c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 1227fe6060f1SDimitry Andric def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 122881ad6265SDimitry Andric (fvti.Mask V0), 1229fe6060f1SDimitry Andric VLOpFrag)), 123081ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 123181ad6265SDimitry Andric (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1232bdd1243dSDimitry Andric (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>; 1233fe6060f1SDimitry Andric } 1234fe6060f1SDimitry Andric} 1235fe6060f1SDimitry Andric 123606c3fb27SDimitry Andricmulticlass VPatWConvertFP2IVL_V_RM<SDPatternOperator vop, string instruction_name> { 123706c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 123806c3fb27SDimitry Andric defvar fvti = fvtiToFWti.Vti; 123906c3fb27SDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 124006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 124106c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 124206c3fb27SDimitry Andric def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 124306c3fb27SDimitry Andric (fvti.Mask V0), 124406c3fb27SDimitry Andric VLOpFrag)), 124506c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 124606c3fb27SDimitry Andric (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 124706c3fb27SDimitry Andric (fvti.Mask V0), 124806c3fb27SDimitry Andric // Value to indicate no rounding mode change in 124906c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 125006c3fb27SDimitry Andric FRM_DYN, 125106c3fb27SDimitry Andric GPR:$vl, fvti.Log2SEW, TA_MA)>; 125206c3fb27SDimitry Andric } 125306c3fb27SDimitry Andric} 125406c3fb27SDimitry Andric 125506c3fb27SDimitry Andric 1256bdd1243dSDimitry Andricmulticlass VPatWConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> { 1257bdd1243dSDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 1258bdd1243dSDimitry Andric defvar fvti = fvtiToFWti.Vti; 1259bdd1243dSDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 126006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 126106c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 1262bdd1243dSDimitry Andric def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 1263bdd1243dSDimitry Andric (fvti.Mask V0), (XLenVT timm:$frm), 1264bdd1243dSDimitry Andric VLOpFrag)), 1265bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 1266bdd1243dSDimitry Andric (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1267bdd1243dSDimitry Andric (fvti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>; 1268bdd1243dSDimitry Andric } 1269bdd1243dSDimitry Andric} 1270bdd1243dSDimitry Andric 127106c3fb27SDimitry Andricmulticlass VPatWConvertI2FPVL_V<SDPatternOperator vop, 127206c3fb27SDimitry Andric string instruction_name> { 1273fe6060f1SDimitry Andric foreach vtiToWti = AllWidenableIntToFloatVectors in { 1274fe6060f1SDimitry Andric defvar ivti = vtiToWti.Vti; 1275fe6060f1SDimitry Andric defvar fwti = vtiToWti.Wti; 127606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates, 127706c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 1278fe6060f1SDimitry Andric def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 127981ad6265SDimitry Andric (ivti.Mask V0), 1280fe6060f1SDimitry Andric VLOpFrag)), 128181ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 128281ad6265SDimitry Andric (fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 128306c3fb27SDimitry Andric (ivti.Mask V0), 128406c3fb27SDimitry Andric GPR:$vl, ivti.Log2SEW, TA_MA)>; 1285bdd1243dSDimitry Andric } 1286bdd1243dSDimitry Andric} 1287bdd1243dSDimitry Andric 1288bdd1243dSDimitry Andric// Narrowing converting 1289bdd1243dSDimitry Andric 129006c3fb27SDimitry Andricmulticlass VPatNConvertFP2IVL_W<SDPatternOperator vop, 129106c3fb27SDimitry Andric string instruction_name> { 1292bdd1243dSDimitry Andric // Reuse the same list of types used in the widening nodes, but just swap the 1293bdd1243dSDimitry Andric // direction of types around so we're converting from Wti -> Vti 1294fe6060f1SDimitry Andric foreach vtiToWti = AllWidenableIntToFloatVectors in { 1295fe6060f1SDimitry Andric defvar vti = vtiToWti.Vti; 1296fe6060f1SDimitry Andric defvar fwti = vtiToWti.Wti; 129706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 129806c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 1299fe6060f1SDimitry Andric def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 130081ad6265SDimitry Andric (fwti.Mask V0), 1301fe6060f1SDimitry Andric VLOpFrag)), 130281ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK") 130381ad6265SDimitry Andric (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1304bdd1243dSDimitry Andric (fwti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 1305fe6060f1SDimitry Andric } 1306fe6060f1SDimitry Andric} 1307fe6060f1SDimitry Andric 130806c3fb27SDimitry Andricmulticlass VPatNConvertFP2IVL_W_RM<SDPatternOperator vop, 130906c3fb27SDimitry Andric string instruction_name> { 131006c3fb27SDimitry Andric // Reuse the same list of types used in the widening nodes, but just swap the 131106c3fb27SDimitry Andric // direction of types around so we're converting from Wti -> Vti 1312bdd1243dSDimitry Andric foreach vtiToWti = AllWidenableIntToFloatVectors in { 1313bdd1243dSDimitry Andric defvar vti = vtiToWti.Vti; 1314bdd1243dSDimitry Andric defvar fwti = vtiToWti.Wti; 131506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 131606c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 131706c3fb27SDimitry Andric def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 131806c3fb27SDimitry Andric (fwti.Mask V0), 131906c3fb27SDimitry Andric VLOpFrag)), 132006c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK") 132106c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 132206c3fb27SDimitry Andric (fwti.Mask V0), 132306c3fb27SDimitry Andric // Value to indicate no rounding mode change in 132406c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 132506c3fb27SDimitry Andric FRM_DYN, 132606c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TA_MA)>; 132706c3fb27SDimitry Andric } 132806c3fb27SDimitry Andric} 132906c3fb27SDimitry Andric 133006c3fb27SDimitry Andricmulticlass VPatNConvertFP2I_RM_VL_W<SDNode vop, string instruction_name> { 133106c3fb27SDimitry Andric foreach vtiToWti = AllWidenableIntToFloatVectors in { 133206c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 133306c3fb27SDimitry Andric defvar fwti = vtiToWti.Wti; 133406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 133506c3fb27SDimitry Andric GetVTypePredicates<fwti>.Predicates) in 1336bdd1243dSDimitry Andric def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 1337bdd1243dSDimitry Andric (fwti.Mask V0), (XLenVT timm:$frm), 1338bdd1243dSDimitry Andric VLOpFrag)), 1339bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK") 1340bdd1243dSDimitry Andric (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1341bdd1243dSDimitry Andric (fwti.Mask V0), timm:$frm, GPR:$vl, vti.Log2SEW, TA_MA)>; 1342bdd1243dSDimitry Andric } 1343bdd1243dSDimitry Andric} 1344bdd1243dSDimitry Andric 134506c3fb27SDimitry Andricmulticlass VPatNConvertI2FPVL_W_RM<SDPatternOperator vop, 134606c3fb27SDimitry Andric string instruction_name> { 1347fe6060f1SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 1348fe6060f1SDimitry Andric defvar fvti = fvtiToFWti.Vti; 1349fe6060f1SDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 135006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 135106c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 1352fe6060f1SDimitry Andric def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 135381ad6265SDimitry Andric (iwti.Mask V0), 1354fe6060f1SDimitry Andric VLOpFrag)), 135581ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 135681ad6265SDimitry Andric (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1, 135706c3fb27SDimitry Andric (iwti.Mask V0), 135806c3fb27SDimitry Andric // Value to indicate no rounding mode change in 135906c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 136006c3fb27SDimitry Andric FRM_DYN, 136106c3fb27SDimitry Andric GPR:$vl, fvti.Log2SEW, TA_MA)>; 1362bdd1243dSDimitry Andric } 1363bdd1243dSDimitry Andric} 1364bdd1243dSDimitry Andric 136506c3fb27SDimitry Andricmulticlass VPatNConvertI2FP_RM_VL_W<SDNode vop, string instruction_name> { 1366bdd1243dSDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 1367bdd1243dSDimitry Andric defvar fvti = fvtiToFWti.Vti; 1368bdd1243dSDimitry Andric defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 136906c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 137006c3fb27SDimitry Andric GetVTypePredicates<iwti>.Predicates) in 1371bdd1243dSDimitry Andric def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 1372bdd1243dSDimitry Andric (iwti.Mask V0), (XLenVT timm:$frm), 1373bdd1243dSDimitry Andric VLOpFrag)), 1374bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 1375bdd1243dSDimitry Andric (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1, 1376bdd1243dSDimitry Andric (iwti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>; 1377fe6060f1SDimitry Andric } 1378fe6060f1SDimitry Andric} 1379fe6060f1SDimitry Andric 1380fe6060f1SDimitry Andricmulticlass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 1381fe6060f1SDimitry Andric foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 1382fe6060f1SDimitry Andric defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 138306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 138406c3fb27SDimitry Andric def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), 138506c3fb27SDimitry Andric (vti.Vector vti.RegClass:$rs1), VR:$rs2, 138606c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag, 138706c3fb27SDimitry Andric (XLenVT timm:$policy))), 138806c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") 1389349cc55cSDimitry Andric (vti_m1.Vector VR:$merge), 1390349cc55cSDimitry Andric (vti.Vector vti.RegClass:$rs1), 1391349cc55cSDimitry Andric (vti_m1.Vector VR:$rs2), 139206c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>; 139306c3fb27SDimitry Andric } 1394fe6060f1SDimitry Andric } 1395fe6060f1SDimitry Andric} 1396fe6060f1SDimitry Andric 139706c3fb27SDimitry Andricmulticlass VPatReductionVL_RM<SDNode vop, string instruction_name, bit is_float> { 139806c3fb27SDimitry Andric foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 139906c3fb27SDimitry Andric defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 140006c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 140106c3fb27SDimitry Andric def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), 140206c3fb27SDimitry Andric (vti.Vector vti.RegClass:$rs1), VR:$rs2, 140306c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag, 140406c3fb27SDimitry Andric (XLenVT timm:$policy))), 140506c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") 140606c3fb27SDimitry Andric (vti_m1.Vector VR:$merge), 140706c3fb27SDimitry Andric (vti.Vector vti.RegClass:$rs1), 140806c3fb27SDimitry Andric (vti_m1.Vector VR:$rs2), 140906c3fb27SDimitry Andric (vti.Mask V0), 141006c3fb27SDimitry Andric // Value to indicate no rounding mode change in 141106c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 141206c3fb27SDimitry Andric FRM_DYN, 141306c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>; 141406c3fb27SDimitry Andric } 141504eeddc0SDimitry Andric } 141604eeddc0SDimitry Andric} 141704eeddc0SDimitry Andric 1418bdd1243dSDimitry Andricmulticlass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> { 141981ad6265SDimitry Andric foreach vtiToWti = AllWidenableIntVectors in { 142081ad6265SDimitry Andric defvar vti = vtiToWti.Vti; 142181ad6265SDimitry Andric defvar wti = vtiToWti.Wti; 142206c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 142306c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 142406c3fb27SDimitry Andric def : Pat< 142506c3fb27SDimitry Andric (vti.Vector 142606c3fb27SDimitry Andric (riscv_trunc_vector_vl 142706c3fb27SDimitry Andric (op (wti.Vector wti.RegClass:$rs2), 142806c3fb27SDimitry Andric (wti.Vector (ext_oneuse (vti.Vector vti.RegClass:$rs1)))), 142906c3fb27SDimitry Andric (vti.Mask true_mask), 143006c3fb27SDimitry Andric VLOpFrag)), 143106c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX) 143206c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 14335f757f3fSDimitry Andric wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>; 143406c3fb27SDimitry Andric 143506c3fb27SDimitry Andric def : Pat< 143606c3fb27SDimitry Andric (vti.Vector 143706c3fb27SDimitry Andric (riscv_trunc_vector_vl 143806c3fb27SDimitry Andric (op (wti.Vector wti.RegClass:$rs2), 14395f757f3fSDimitry Andric (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1)))), 144006c3fb27SDimitry Andric (vti.Mask true_mask), 144106c3fb27SDimitry Andric VLOpFrag)), 144206c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 144306c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 14445f757f3fSDimitry Andric wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>; 144506c3fb27SDimitry Andric 144681ad6265SDimitry Andric def : Pat< 144781ad6265SDimitry Andric (vti.Vector 144881ad6265SDimitry Andric (riscv_trunc_vector_vl 144981ad6265SDimitry Andric (op (wti.Vector wti.RegClass:$rs2), 145081ad6265SDimitry Andric (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask), 145181ad6265SDimitry Andric VLOpFrag)), 145281ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 145306c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 14545f757f3fSDimitry Andric wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>; 145506c3fb27SDimitry Andric } 145681ad6265SDimitry Andric } 145704eeddc0SDimitry Andric} 145804eeddc0SDimitry Andric 145981ad6265SDimitry Andricmulticlass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 146081ad6265SDimitry Andric foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 146181ad6265SDimitry Andric defvar vti = vtiToWti.Vti; 146281ad6265SDimitry Andric defvar wti = vtiToWti.Wti; 146381ad6265SDimitry Andric defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 146406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 146506c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 146681ad6265SDimitry Andric def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 146781ad6265SDimitry Andric (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 146806c3fb27SDimitry Andric VR:$rs2, (vti.Mask V0), VLOpFrag, 146906c3fb27SDimitry Andric (XLenVT timm:$policy))), 147006c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") 147181ad6265SDimitry Andric (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 147206c3fb27SDimitry Andric (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW, 147306c3fb27SDimitry Andric (XLenVT timm:$policy))>; 147406c3fb27SDimitry Andric } 147506c3fb27SDimitry Andric } 147606c3fb27SDimitry Andric} 147706c3fb27SDimitry Andric 147806c3fb27SDimitry Andricmulticlass VPatWidenReductionVL_RM<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 147906c3fb27SDimitry Andric foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 148006c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 148106c3fb27SDimitry Andric defvar wti = vtiToWti.Wti; 148206c3fb27SDimitry Andric defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 148306c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 148406c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 148506c3fb27SDimitry Andric def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 148606c3fb27SDimitry Andric (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 148706c3fb27SDimitry Andric VR:$rs2, (vti.Mask V0), VLOpFrag, 148806c3fb27SDimitry Andric (XLenVT timm:$policy))), 148906c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") 149006c3fb27SDimitry Andric (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 149106c3fb27SDimitry Andric (wti_m1.Vector VR:$rs2), (vti.Mask V0), 149206c3fb27SDimitry Andric // Value to indicate no rounding mode change in 149306c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 149406c3fb27SDimitry Andric FRM_DYN, 149506c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, 149606c3fb27SDimitry Andric (XLenVT timm:$policy))>; 149706c3fb27SDimitry Andric } 149881ad6265SDimitry Andric } 149981ad6265SDimitry Andric} 150081ad6265SDimitry Andric 150181ad6265SDimitry Andricmulticlass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 150281ad6265SDimitry Andric foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 150381ad6265SDimitry Andric defvar vti = vtiToWti.Vti; 150481ad6265SDimitry Andric defvar wti = vtiToWti.Wti; 150581ad6265SDimitry Andric defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 150606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 150706c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 150881ad6265SDimitry Andric def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 150981ad6265SDimitry Andric (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 151006c3fb27SDimitry Andric VR:$rs2, (vti.Mask V0), VLOpFrag, 151106c3fb27SDimitry Andric (XLenVT timm:$policy))), 151206c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") 151381ad6265SDimitry Andric (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 151406c3fb27SDimitry Andric (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW, 151506c3fb27SDimitry Andric (XLenVT timm:$policy))>; 151606c3fb27SDimitry Andric } 151781ad6265SDimitry Andric } 151881ad6265SDimitry Andric} 151981ad6265SDimitry Andric 152006c3fb27SDimitry Andricmulticlass VPatWidenReductionVL_Ext_VL_RM<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 152106c3fb27SDimitry Andric foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 152206c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 152306c3fb27SDimitry Andric defvar wti = vtiToWti.Wti; 152406c3fb27SDimitry Andric defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 152506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 152606c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 152706c3fb27SDimitry Andric def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 152806c3fb27SDimitry Andric (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 152906c3fb27SDimitry Andric VR:$rs2, (vti.Mask V0), VLOpFrag, 153006c3fb27SDimitry Andric (XLenVT timm:$policy))), 153106c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") 153206c3fb27SDimitry Andric (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 153306c3fb27SDimitry Andric (wti_m1.Vector VR:$rs2), (vti.Mask V0), 153406c3fb27SDimitry Andric // Value to indicate no rounding mode change in 153506c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 153606c3fb27SDimitry Andric FRM_DYN, 153706c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, 153806c3fb27SDimitry Andric (XLenVT timm:$policy))>; 153906c3fb27SDimitry Andric } 154006c3fb27SDimitry Andric } 154106c3fb27SDimitry Andric} 154206c3fb27SDimitry Andric 154306c3fb27SDimitry Andricmulticlass VPatBinaryFPWVL_VV_VF<SDNode vop, string instruction_name> { 154481ad6265SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 154506c3fb27SDimitry Andric defvar vti = fvtiToFWti.Vti; 154606c3fb27SDimitry Andric defvar wti = fvtiToFWti.Wti; 154706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 154806c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 154906c3fb27SDimitry Andric def : VPatBinaryVL_V<vop, instruction_name, "VV", 155006c3fb27SDimitry Andric wti.Vector, vti.Vector, vti.Vector, vti.Mask, 155106c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass, 155206c3fb27SDimitry Andric vti.RegClass>; 155306c3fb27SDimitry Andric def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 155406c3fb27SDimitry Andric wti.Vector, vti.Vector, vti.Vector, vti.Mask, 155506c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass, 155606c3fb27SDimitry Andric vti.ScalarRegClass>; 155706c3fb27SDimitry Andric } 155881ad6265SDimitry Andric } 155981ad6265SDimitry Andric} 156081ad6265SDimitry Andric 156106c3fb27SDimitry Andricmulticlass VPatBinaryFPWVL_VV_VF_RM<SDNode vop, string instruction_name> { 156281ad6265SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 156306c3fb27SDimitry Andric defvar vti = fvtiToFWti.Vti; 156406c3fb27SDimitry Andric defvar wti = fvtiToFWti.Wti; 156506c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 156606c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 156706c3fb27SDimitry Andric def : VPatBinaryVL_V_RM<vop, instruction_name, "VV", 156806c3fb27SDimitry Andric wti.Vector, vti.Vector, vti.Vector, vti.Mask, 156906c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass, 157006c3fb27SDimitry Andric vti.RegClass>; 157106c3fb27SDimitry Andric def : VPatBinaryVL_VF_RM<vop, instruction_name#"_V"#vti.ScalarSuffix, 157206c3fb27SDimitry Andric wti.Vector, vti.Vector, vti.Vector, vti.Mask, 157306c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass, 157406c3fb27SDimitry Andric vti.ScalarRegClass>; 157506c3fb27SDimitry Andric } 157681ad6265SDimitry Andric } 157781ad6265SDimitry Andric} 157881ad6265SDimitry Andric 157906c3fb27SDimitry Andricmulticlass VPatBinaryFPWVL_VV_VF_WV_WF<SDNode vop, SDNode vop_w, string instruction_name> 158006c3fb27SDimitry Andric : VPatBinaryFPWVL_VV_VF<vop, instruction_name> { 158106c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 158206c3fb27SDimitry Andric defvar vti = fvtiToFWti.Vti; 158306c3fb27SDimitry Andric defvar wti = fvtiToFWti.Wti; 158406c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 158506c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 158606c3fb27SDimitry Andric defm : VPatTiedBinaryNoMaskVL_V<vop_w, instruction_name, "WV", 158706c3fb27SDimitry Andric wti.Vector, vti.Vector, vti.Log2SEW, 158806c3fb27SDimitry Andric vti.LMul, wti.RegClass, vti.RegClass>; 158906c3fb27SDimitry Andric def : VPatBinaryVL_V<vop_w, instruction_name, "WV", 159006c3fb27SDimitry Andric wti.Vector, wti.Vector, vti.Vector, vti.Mask, 159106c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass, 159206c3fb27SDimitry Andric vti.RegClass>; 159306c3fb27SDimitry Andric def : VPatBinaryVL_VF<vop_w, instruction_name#"_W"#vti.ScalarSuffix, 159406c3fb27SDimitry Andric wti.Vector, wti.Vector, vti.Vector, vti.Mask, 159506c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass, 159606c3fb27SDimitry Andric vti.ScalarRegClass>; 159706c3fb27SDimitry Andric } 159806c3fb27SDimitry Andric } 159906c3fb27SDimitry Andric} 160006c3fb27SDimitry Andric 160106c3fb27SDimitry Andricmulticlass VPatBinaryFPWVL_VV_VF_WV_WF_RM<SDNode vop, SDNode vop_w, string instruction_name> 160206c3fb27SDimitry Andric : VPatBinaryFPWVL_VV_VF_RM<vop, instruction_name> { 160306c3fb27SDimitry Andric foreach fvtiToFWti = AllWidenableFloatVectors in { 160406c3fb27SDimitry Andric defvar vti = fvtiToFWti.Vti; 160506c3fb27SDimitry Andric defvar wti = fvtiToFWti.Wti; 160606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 160706c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 160806c3fb27SDimitry Andric defm : VPatTiedBinaryNoMaskVL_V_RM<vop_w, instruction_name, "WV", 160906c3fb27SDimitry Andric wti.Vector, vti.Vector, vti.Log2SEW, 161006c3fb27SDimitry Andric vti.LMul, wti.RegClass, vti.RegClass>; 161106c3fb27SDimitry Andric def : VPatBinaryVL_V_RM<vop_w, instruction_name, "WV", 161206c3fb27SDimitry Andric wti.Vector, wti.Vector, vti.Vector, vti.Mask, 161306c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass, 161406c3fb27SDimitry Andric vti.RegClass>; 161506c3fb27SDimitry Andric def : VPatBinaryVL_VF_RM<vop_w, instruction_name#"_W"#vti.ScalarSuffix, 161606c3fb27SDimitry Andric wti.Vector, wti.Vector, vti.Vector, vti.Mask, 161706c3fb27SDimitry Andric vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass, 161806c3fb27SDimitry Andric vti.ScalarRegClass>; 161906c3fb27SDimitry Andric } 162006c3fb27SDimitry Andric } 162181ad6265SDimitry Andric} 162281ad6265SDimitry Andric 162381ad6265SDimitry Andricmulticlass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> { 162481ad6265SDimitry Andric foreach vtiToWti = AllWidenableIntVectors in { 162581ad6265SDimitry Andric defvar vti = vtiToWti.Vti; 162681ad6265SDimitry Andric defvar wti = vtiToWti.Wti; 162706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 162806c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 162981ad6265SDimitry Andric def : Pat< 163081ad6265SDimitry Andric (vti.Vector 163181ad6265SDimitry Andric (riscv_trunc_vector_vl 163281ad6265SDimitry Andric (op (wti.Vector wti.RegClass:$rs2), 163306c3fb27SDimitry Andric (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1))), 163481ad6265SDimitry Andric (vti.Mask true_mask), VLOpFrag)), 1635bdd1243dSDimitry Andric srcvalue, (wti.Mask true_mask), VLOpFrag), 163681ad6265SDimitry Andric (vti.Mask true_mask), VLOpFrag)), 163781ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 163806c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 16395f757f3fSDimitry Andric wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>; 164081ad6265SDimitry Andric } 164181ad6265SDimitry Andric} 164281ad6265SDimitry Andric 164306c3fb27SDimitry Andricmulticlass VPatNarrowShiftExtVL_WV<SDNode op, PatFrags extop, string instruction_name> { 164406c3fb27SDimitry Andric foreach vtiToWti = AllWidenableIntVectors in { 164506c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 164606c3fb27SDimitry Andric defvar wti = vtiToWti.Wti; 164706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 164806c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 164906c3fb27SDimitry Andric def : Pat< 165006c3fb27SDimitry Andric (vti.Vector 165106c3fb27SDimitry Andric (riscv_trunc_vector_vl 165206c3fb27SDimitry Andric (op (wti.Vector wti.RegClass:$rs2), 165306c3fb27SDimitry Andric (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), 165406c3fb27SDimitry Andric (vti.Mask true_mask), VLOpFrag)), 165506c3fb27SDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 165606c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag)), 165706c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_MASK") 165806c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2, vti.RegClass:$rs1, 16595f757f3fSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 166006c3fb27SDimitry Andric } 166106c3fb27SDimitry Andric} 166206c3fb27SDimitry Andric 166306c3fb27SDimitry Andricmulticlass VPatNarrowShiftVL_WV<SDNode op, string instruction_name> { 166406c3fb27SDimitry Andric defm : VPatNarrowShiftExtVL_WV<op, riscv_sext_vl_oneuse, instruction_name>; 166506c3fb27SDimitry Andric defm : VPatNarrowShiftExtVL_WV<op, riscv_zext_vl_oneuse, instruction_name>; 166606c3fb27SDimitry Andric} 166706c3fb27SDimitry Andric 166881ad6265SDimitry Andricmulticlass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> { 166981ad6265SDimitry Andric foreach vti = AllIntegerVectors in { 167081ad6265SDimitry Andric defvar suffix = vti.LMul.MX; 167106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 167281ad6265SDimitry Andric // NOTE: We choose VMADD because it has the most commuting freedom. So it 167381ad6265SDimitry Andric // works best with how TwoAddressInstructionPass tries commuting. 167481ad6265SDimitry Andric def : Pat<(vti.Vector 167581ad6265SDimitry Andric (op vti.RegClass:$rs2, 167681ad6265SDimitry Andric (riscv_mul_vl_oneuse vti.RegClass:$rs1, 167781ad6265SDimitry Andric vti.RegClass:$rd, 1678bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 1679bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag)), 168081ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix) 168181ad6265SDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 168281ad6265SDimitry Andric GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 168381ad6265SDimitry Andric // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 168481ad6265SDimitry Andric // commutable. 168581ad6265SDimitry Andric def : Pat<(vti.Vector 168681ad6265SDimitry Andric (op vti.RegClass:$rs2, 168781ad6265SDimitry Andric (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 168881ad6265SDimitry Andric vti.RegClass:$rd, 1689bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 1690bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag)), 169181ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_VX_" # suffix) 169281ad6265SDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 169381ad6265SDimitry Andric GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 169481ad6265SDimitry Andric } 169581ad6265SDimitry Andric } 169606c3fb27SDimitry Andric} 169781ad6265SDimitry Andric 1698bdd1243dSDimitry Andricmulticlass VPatMultiplyAccVL_VV_VX<PatFrag op, string instruction_name> { 1699bdd1243dSDimitry Andric foreach vti = AllIntegerVectors in { 1700bdd1243dSDimitry Andric defvar suffix = vti.LMul.MX; 170106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 1702cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1703bdd1243dSDimitry Andric (vti.Vector (op vti.RegClass:$rd, 1704bdd1243dSDimitry Andric (riscv_mul_vl_oneuse vti.RegClass:$rs1, vti.RegClass:$rs2, 1705bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 1706bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag)), 1707cb14a3feSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag), 1708bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 1709bdd1243dSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 171006c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>; 1711cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1712bdd1243dSDimitry Andric (vti.Vector (op vti.RegClass:$rd, 1713bdd1243dSDimitry Andric (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rs2, 1714bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 1715bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag)), 1716cb14a3feSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag), 1717bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_VX_"# suffix #"_MASK") 1718bdd1243dSDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 171906c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>; 17201db9f3b2SDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1721bdd1243dSDimitry Andric (vti.Vector (op vti.RegClass:$rd, 1722bdd1243dSDimitry Andric (riscv_mul_vl_oneuse vti.RegClass:$rs1, vti.RegClass:$rs2, 1723bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 1724bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag)), 17251db9f3b2SDimitry Andric vti.RegClass:$rd, undef, VLOpFrag), 1726bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 1727bdd1243dSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1728bdd1243dSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 17291db9f3b2SDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1730bdd1243dSDimitry Andric (vti.Vector (op vti.RegClass:$rd, 1731bdd1243dSDimitry Andric (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rs2, 1732bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 1733bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag)), 17341db9f3b2SDimitry Andric vti.RegClass:$rd, undef, VLOpFrag), 1735bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_VX_"# suffix #"_MASK") 1736bdd1243dSDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1737bdd1243dSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1738bdd1243dSDimitry Andric } 1739bdd1243dSDimitry Andric } 174006c3fb27SDimitry Andric} 1741bdd1243dSDimitry Andric 174206c3fb27SDimitry Andricmulticlass VPatWidenMultiplyAddVL_VV_VX<SDNode vwmacc_op, string instr_name> { 174381ad6265SDimitry Andric foreach vtiTowti = AllWidenableIntVectors in { 174481ad6265SDimitry Andric defvar vti = vtiTowti.Vti; 174581ad6265SDimitry Andric defvar wti = vtiTowti.Wti; 174606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 174706c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 174806c3fb27SDimitry Andric def : Pat<(vwmacc_op (vti.Vector vti.RegClass:$rs1), 174981ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs2), 175006c3fb27SDimitry Andric (wti.Vector wti.RegClass:$rd), 175106c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag), 175206c3fb27SDimitry Andric (!cast<Instruction>(instr_name#"_VV_"#vti.LMul.MX#"_MASK") 175381ad6265SDimitry Andric wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 175406c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 175506c3fb27SDimitry Andric def : Pat<(vwmacc_op (SplatPat XLenVT:$rs1), 175681ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs2), 175706c3fb27SDimitry Andric (wti.Vector wti.RegClass:$rd), 175806c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag), 175906c3fb27SDimitry Andric (!cast<Instruction>(instr_name#"_VX_"#vti.LMul.MX#"_MASK") 176006c3fb27SDimitry Andric wti.RegClass:$rd, vti.ScalarRegClass:$rs1, 176106c3fb27SDimitry Andric vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 176206c3fb27SDimitry Andric TAIL_AGNOSTIC)>; 176306c3fb27SDimitry Andric } 176481ad6265SDimitry Andric } 176581ad6265SDimitry Andric} 176681ad6265SDimitry Andric 176781ad6265SDimitry Andricmulticlass VPatNarrowShiftSplat_WX_WI<SDNode op, string instruction_name> { 176881ad6265SDimitry Andric foreach vtiTowti = AllWidenableIntVectors in { 176981ad6265SDimitry Andric defvar vti = vtiTowti.Vti; 177081ad6265SDimitry Andric defvar wti = vtiTowti.Wti; 177106c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 177206c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 177381ad6265SDimitry Andric def : Pat<(vti.Vector (riscv_trunc_vector_vl 177481ad6265SDimitry Andric (wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 1775bdd1243dSDimitry Andric srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)), 177681ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 177706c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 17785f757f3fSDimitry Andric wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>; 177981ad6265SDimitry Andric def : Pat<(vti.Vector (riscv_trunc_vector_vl 178081ad6265SDimitry Andric (wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 1781bdd1243dSDimitry Andric srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)), 178281ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 178306c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 17845f757f3fSDimitry Andric wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>; 178506c3fb27SDimitry Andric } 178681ad6265SDimitry Andric } 178781ad6265SDimitry Andric} 178881ad6265SDimitry Andric 178906c3fb27SDimitry Andricmulticlass VPatFPMulAddVL_VV_VF<SDPatternOperator vop, string instruction_name> { 179081ad6265SDimitry Andric foreach vti = AllFloatVectors in { 179181ad6265SDimitry Andric defvar suffix = vti.LMul.MX; 179206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 179381ad6265SDimitry Andric def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd, 179481ad6265SDimitry Andric vti.RegClass:$rs2, (vti.Mask V0), 179581ad6265SDimitry Andric VLOpFrag)), 179681ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 179781ad6265SDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 179806c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 179981ad6265SDimitry Andric 180081ad6265SDimitry Andric def : Pat<(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), 180181ad6265SDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs2, 180281ad6265SDimitry Andric (vti.Mask V0), 180381ad6265SDimitry Andric VLOpFrag)), 180481ad6265SDimitry Andric (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 180581ad6265SDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 180606c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 180706c3fb27SDimitry Andric } 180806c3fb27SDimitry Andric } 180906c3fb27SDimitry Andric} 181006c3fb27SDimitry Andric 181106c3fb27SDimitry Andricmulticlass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_name> { 181206c3fb27SDimitry Andric foreach vti = AllFloatVectors in { 181306c3fb27SDimitry Andric defvar suffix = vti.LMul.MX; 181406c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 181506c3fb27SDimitry Andric def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd, 181606c3fb27SDimitry Andric vti.RegClass:$rs2, (vti.Mask V0), 181706c3fb27SDimitry Andric VLOpFrag)), 181806c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 181906c3fb27SDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 182006c3fb27SDimitry Andric (vti.Mask V0), 182106c3fb27SDimitry Andric // Value to indicate no rounding mode change in 182206c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 182306c3fb27SDimitry Andric FRM_DYN, 182406c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TA_MA)>; 182506c3fb27SDimitry Andric 182606c3fb27SDimitry Andric def : Pat<(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), 182706c3fb27SDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs2, 182806c3fb27SDimitry Andric (vti.Mask V0), 182906c3fb27SDimitry Andric VLOpFrag)), 183006c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 183106c3fb27SDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 183206c3fb27SDimitry Andric (vti.Mask V0), 183306c3fb27SDimitry Andric // Value to indicate no rounding mode change in 183406c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 183506c3fb27SDimitry Andric FRM_DYN, 183606c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TA_MA)>; 183706c3fb27SDimitry Andric } 183881ad6265SDimitry Andric } 183981ad6265SDimitry Andric} 184081ad6265SDimitry Andric 1841bdd1243dSDimitry Andricmulticlass VPatFPMulAccVL_VV_VF<PatFrag vop, string instruction_name> { 1842bdd1243dSDimitry Andric foreach vti = AllFloatVectors in { 1843bdd1243dSDimitry Andric defvar suffix = vti.LMul.MX; 184406c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 1845cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1846bdd1243dSDimitry Andric (vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2, 1847bdd1243dSDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 1848cb14a3feSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag), 1849bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 1850bdd1243dSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 185106c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>; 1852cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1853bdd1243dSDimitry Andric (vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2, 1854bdd1243dSDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 1855cb14a3feSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag), 1856bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1857bdd1243dSDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 185806c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>; 18591db9f3b2SDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1860bdd1243dSDimitry Andric (vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2, 1861bdd1243dSDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 18621db9f3b2SDimitry Andric vti.RegClass:$rd, undef, VLOpFrag), 1863bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 1864bdd1243dSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1865bdd1243dSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 18661db9f3b2SDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 1867bdd1243dSDimitry Andric (vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2, 1868bdd1243dSDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 18691db9f3b2SDimitry Andric vti.RegClass:$rd, undef, VLOpFrag), 1870bdd1243dSDimitry Andric (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1871bdd1243dSDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1872bdd1243dSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1873bdd1243dSDimitry Andric } 1874bdd1243dSDimitry Andric } 187506c3fb27SDimitry Andric} 187606c3fb27SDimitry Andric 187706c3fb27SDimitry Andricmulticlass VPatFPMulAccVL_VV_VF_RM<PatFrag vop, string instruction_name> { 187806c3fb27SDimitry Andric foreach vti = AllFloatVectors in { 187906c3fb27SDimitry Andric defvar suffix = vti.LMul.MX; 188006c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 1881cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 188206c3fb27SDimitry Andric (vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2, 188306c3fb27SDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 1884cb14a3feSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag), 188506c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 188606c3fb27SDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 188706c3fb27SDimitry Andric (vti.Mask V0), 188806c3fb27SDimitry Andric // Value to indicate no rounding mode change in 188906c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 189006c3fb27SDimitry Andric FRM_DYN, 189106c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TU_MU)>; 1892cb14a3feSDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 189306c3fb27SDimitry Andric (vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2, 189406c3fb27SDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 1895cb14a3feSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag), 189606c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 189706c3fb27SDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 189806c3fb27SDimitry Andric (vti.Mask V0), 189906c3fb27SDimitry Andric // Value to indicate no rounding mode change in 190006c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 190106c3fb27SDimitry Andric FRM_DYN, 190206c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TU_MU)>; 19031db9f3b2SDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 190406c3fb27SDimitry Andric (vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2, 190506c3fb27SDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 19061db9f3b2SDimitry Andric vti.RegClass:$rd, undef, VLOpFrag), 190706c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") 190806c3fb27SDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 190906c3fb27SDimitry Andric (vti.Mask V0), 191006c3fb27SDimitry Andric // Value to indicate no rounding mode change in 191106c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 191206c3fb27SDimitry Andric FRM_DYN, 191306c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 19141db9f3b2SDimitry Andric def : Pat<(riscv_vmerge_vl (vti.Mask V0), 191506c3fb27SDimitry Andric (vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2, 191606c3fb27SDimitry Andric vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), 19171db9f3b2SDimitry Andric vti.RegClass:$rd, undef, VLOpFrag), 191806c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 191906c3fb27SDimitry Andric vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 192006c3fb27SDimitry Andric (vti.Mask V0), 192106c3fb27SDimitry Andric // Value to indicate no rounding mode change in 192206c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 192306c3fb27SDimitry Andric FRM_DYN, 192406c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 192506c3fb27SDimitry Andric } 192606c3fb27SDimitry Andric } 192706c3fb27SDimitry Andric} 1928bdd1243dSDimitry Andric 192981ad6265SDimitry Andricmulticlass VPatWidenFPMulAccVL_VV_VF<SDNode vop, string instruction_name> { 193081ad6265SDimitry Andric foreach vtiToWti = AllWidenableFloatVectors in { 193181ad6265SDimitry Andric defvar vti = vtiToWti.Vti; 193281ad6265SDimitry Andric defvar wti = vtiToWti.Wti; 193306c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 193406c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 193506c3fb27SDimitry Andric def : Pat<(vop (vti.Vector vti.RegClass:$rs1), 193681ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs2), 193706c3fb27SDimitry Andric (wti.Vector wti.RegClass:$rd), (vti.Mask V0), 193881ad6265SDimitry Andric VLOpFrag), 193906c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX #"_MASK") 194081ad6265SDimitry Andric wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 194106c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 194206c3fb27SDimitry Andric def : Pat<(vop (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 194381ad6265SDimitry Andric (vti.Vector vti.RegClass:$rs2), 194406c3fb27SDimitry Andric (wti.Vector wti.RegClass:$rd), (vti.Mask V0), 194581ad6265SDimitry Andric VLOpFrag), 194606c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX #"_MASK") 194781ad6265SDimitry Andric wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 194806c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 194906c3fb27SDimitry Andric } 195006c3fb27SDimitry Andric } 195106c3fb27SDimitry Andric} 195206c3fb27SDimitry Andric 195306c3fb27SDimitry Andricmulticlass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name> { 195406c3fb27SDimitry Andric foreach vtiToWti = AllWidenableFloatVectors in { 195506c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 195606c3fb27SDimitry Andric defvar wti = vtiToWti.Wti; 195706c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 195806c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 195906c3fb27SDimitry Andric def : Pat<(vop (vti.Vector vti.RegClass:$rs1), 196006c3fb27SDimitry Andric (vti.Vector vti.RegClass:$rs2), 196106c3fb27SDimitry Andric (wti.Vector wti.RegClass:$rd), (vti.Mask V0), 196206c3fb27SDimitry Andric VLOpFrag), 196306c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX #"_MASK") 196406c3fb27SDimitry Andric wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 196506c3fb27SDimitry Andric (vti.Mask V0), 196606c3fb27SDimitry Andric // Value to indicate no rounding mode change in 196706c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 196806c3fb27SDimitry Andric FRM_DYN, 196906c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TA_MA)>; 197006c3fb27SDimitry Andric def : Pat<(vop (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 197106c3fb27SDimitry Andric (vti.Vector vti.RegClass:$rs2), 197206c3fb27SDimitry Andric (wti.Vector wti.RegClass:$rd), (vti.Mask V0), 197306c3fb27SDimitry Andric VLOpFrag), 197406c3fb27SDimitry Andric (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX #"_MASK") 197506c3fb27SDimitry Andric wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 197606c3fb27SDimitry Andric (vti.Mask V0), 197706c3fb27SDimitry Andric // Value to indicate no rounding mode change in 197806c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 197906c3fb27SDimitry Andric FRM_DYN, 198006c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TA_MA)>; 198106c3fb27SDimitry Andric } 198281ad6265SDimitry Andric } 198304eeddc0SDimitry Andric} 198404eeddc0SDimitry Andric 19855f757f3fSDimitry Andricmulticlass VPatSlideVL_VX_VI<SDNode vop, string instruction_name> { 19865f757f3fSDimitry Andric foreach vti = AllVectors in { 19875f757f3fSDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 19885f757f3fSDimitry Andric def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rd), 19895f757f3fSDimitry Andric (vti.Vector vti.RegClass:$rs1), 19905f757f3fSDimitry Andric uimm5:$rs2, (vti.Mask V0), 19915f757f3fSDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 19925f757f3fSDimitry Andric (!cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK") 19935f757f3fSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, uimm5:$rs2, 19945f757f3fSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, 19955f757f3fSDimitry Andric (XLenVT timm:$policy))>; 19965f757f3fSDimitry Andric 19975f757f3fSDimitry Andric def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rd), 19985f757f3fSDimitry Andric (vti.Vector vti.RegClass:$rs1), 19995f757f3fSDimitry Andric GPR:$rs2, (vti.Mask V0), 20005f757f3fSDimitry Andric VLOpFrag, (XLenVT timm:$policy))), 20015f757f3fSDimitry Andric (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK") 20025f757f3fSDimitry Andric vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, 20035f757f3fSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, 20045f757f3fSDimitry Andric (XLenVT timm:$policy))>; 20055f757f3fSDimitry Andric } 20065f757f3fSDimitry Andric } 20075f757f3fSDimitry Andric} 20085f757f3fSDimitry Andric 20095f757f3fSDimitry Andricmulticlass VPatSlide1VL_VX<SDNode vop, string instruction_name> { 20105f757f3fSDimitry Andric foreach vti = AllIntegerVectors in { 20115f757f3fSDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 20125f757f3fSDimitry Andric def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rs3), 20135f757f3fSDimitry Andric (vti.Vector vti.RegClass:$rs1), 20145f757f3fSDimitry Andric GPR:$rs2, (vti.Mask V0), VLOpFrag)), 20155f757f3fSDimitry Andric (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK") 20165f757f3fSDimitry Andric vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 20175f757f3fSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>; 20185f757f3fSDimitry Andric } 20195f757f3fSDimitry Andric } 20205f757f3fSDimitry Andric} 20215f757f3fSDimitry Andric 20225f757f3fSDimitry Andricmulticlass VPatSlide1VL_VF<SDNode vop, string instruction_name> { 20235f757f3fSDimitry Andric foreach vti = AllFloatVectors in { 20245f757f3fSDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 20255f757f3fSDimitry Andric def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rs3), 20265f757f3fSDimitry Andric (vti.Vector vti.RegClass:$rs1), 20275f757f3fSDimitry Andric vti.Scalar:$rs2, (vti.Mask V0), VLOpFrag)), 20285f757f3fSDimitry Andric (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_MASK") 20295f757f3fSDimitry Andric vti.RegClass:$rs3, vti.RegClass:$rs1, vti.Scalar:$rs2, 20305f757f3fSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>; 20315f757f3fSDimitry Andric } 20325f757f3fSDimitry Andric } 20335f757f3fSDimitry Andric} 20345f757f3fSDimitry Andric 2035297eecfbSDimitry Andricmulticlass VPatAVGADDVL_VV_VX_RM<SDNode vop, int vxrm> { 2036297eecfbSDimitry Andric foreach vti = AllIntegerVectors in { 2037297eecfbSDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 2038297eecfbSDimitry Andric def : Pat<(vop (vti.Vector vti.RegClass:$rs1), 2039297eecfbSDimitry Andric (vti.Vector vti.RegClass:$rs2), 2040297eecfbSDimitry Andric vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), 2041297eecfbSDimitry Andric (!cast<Instruction>("PseudoVAADDU_VV_"#vti.LMul.MX#"_MASK") 2042297eecfbSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs2, 2043297eecfbSDimitry Andric (vti.Mask V0), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2044297eecfbSDimitry Andric def : Pat<(vop (vti.Vector vti.RegClass:$rs1), 2045297eecfbSDimitry Andric (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 2046297eecfbSDimitry Andric vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), 2047297eecfbSDimitry Andric (!cast<Instruction>("PseudoVAADDU_VX_"#vti.LMul.MX#"_MASK") 2048297eecfbSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs1, GPR:$rs2, 2049297eecfbSDimitry Andric (vti.Mask V0), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2050297eecfbSDimitry Andric } 2051297eecfbSDimitry Andric } 2052297eecfbSDimitry Andric} 2053297eecfbSDimitry Andric 2054fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 2055fe6060f1SDimitry Andric// Patterns. 2056fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 2057fe6060f1SDimitry Andric 2058bdd1243dSDimitry Andric// 11. Vector Integer Arithmetic Instructions 2059bdd1243dSDimitry Andric 2060bdd1243dSDimitry Andric// 11.1. Vector Single-Width Integer Add and Subtract 2061fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 2062fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 2063fe6060f1SDimitry Andric// Handle VRSUB specially since it's the only integer binary op with reversed 2064fe6060f1SDimitry Andric// pattern operands 2065fe6060f1SDimitry Andricforeach vti = AllIntegerVectors in { 206606c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 2067fe6060f1SDimitry Andric def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 2068bdd1243dSDimitry Andric (vti.Vector vti.RegClass:$rs1), 2069bdd1243dSDimitry Andric vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), 2070fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 2071bdd1243dSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs1, GPR:$rs2, 2072349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2073fe6060f1SDimitry Andric def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 2074bdd1243dSDimitry Andric (vti.Vector vti.RegClass:$rs1), 2075bdd1243dSDimitry Andric vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), 2076fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 2077bdd1243dSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs1, simm5:$rs2, 2078349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2079fe6060f1SDimitry Andric } 208006c3fb27SDimitry Andric} 2081fe6060f1SDimitry Andric 2082bdd1243dSDimitry Andric// 11.2. Vector Widening Integer Add/Subtract 208381ad6265SDimitry Andricdefm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwadd_vl, riscv_vwadd_w_vl, "PseudoVWADD">; 208481ad6265SDimitry Andricdefm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWADDU">; 208581ad6265SDimitry Andricdefm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">; 208681ad6265SDimitry Andricdefm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">; 208704eeddc0SDimitry Andric 208806c3fb27SDimitry Andric// shl_vl (ext_vl v, splat 1) is a special case of widening add. 208906c3fb27SDimitry Andricforeach vtiToWti = AllWidenableIntVectors in { 209006c3fb27SDimitry Andric defvar vti = vtiToWti.Vti; 209106c3fb27SDimitry Andric defvar wti = vtiToWti.Wti; 209206c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 209306c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in { 209406c3fb27SDimitry Andric def : Pat<(riscv_shl_vl (wti.Vector (riscv_sext_vl_oneuse 209506c3fb27SDimitry Andric (vti.Vector vti.RegClass:$rs1), 209606c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag)), 209706c3fb27SDimitry Andric (wti.Vector (riscv_vmv_v_x_vl 209806c3fb27SDimitry Andric (wti.Vector undef), 1, VLOpFrag)), 209906c3fb27SDimitry Andric wti.RegClass:$merge, (vti.Mask V0), VLOpFrag), 210006c3fb27SDimitry Andric (!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX#"_MASK") 210106c3fb27SDimitry Andric wti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs1, 210206c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 210306c3fb27SDimitry Andric def : Pat<(riscv_shl_vl (wti.Vector (riscv_zext_vl_oneuse 210406c3fb27SDimitry Andric (vti.Vector vti.RegClass:$rs1), 210506c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag)), 210606c3fb27SDimitry Andric (wti.Vector (riscv_vmv_v_x_vl 210706c3fb27SDimitry Andric (wti.Vector undef), 1, VLOpFrag)), 210806c3fb27SDimitry Andric wti.RegClass:$merge, (vti.Mask V0), VLOpFrag), 210906c3fb27SDimitry Andric (!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX#"_MASK") 211006c3fb27SDimitry Andric wti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs1, 211106c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 211206c3fb27SDimitry Andric } 211306c3fb27SDimitry Andric} 211406c3fb27SDimitry Andric 2115bdd1243dSDimitry Andric// 11.3. Vector Integer Extension 2116bdd1243dSDimitry Andricdefm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF2", 2117fe6060f1SDimitry Andric AllFractionableVF2IntVectors>; 2118bdd1243dSDimitry Andricdefm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF2", 2119fe6060f1SDimitry Andric AllFractionableVF2IntVectors>; 2120bdd1243dSDimitry Andricdefm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF4", 2121fe6060f1SDimitry Andric AllFractionableVF4IntVectors>; 2122bdd1243dSDimitry Andricdefm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF4", 2123fe6060f1SDimitry Andric AllFractionableVF4IntVectors>; 2124bdd1243dSDimitry Andricdefm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF8", 2125fe6060f1SDimitry Andric AllFractionableVF8IntVectors>; 2126bdd1243dSDimitry Andricdefm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF8", 2127fe6060f1SDimitry Andric AllFractionableVF8IntVectors>; 2128fe6060f1SDimitry Andric 2129bdd1243dSDimitry Andric// 11.5. Vector Bitwise Logical Instructions 2130fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 2131fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 2132fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 2133fe6060f1SDimitry Andric 2134bdd1243dSDimitry Andric// 11.6. Vector Single-Width Bit Shift Instructions 2135fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 2136fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 2137fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 2138fe6060f1SDimitry Andric 2139fe6060f1SDimitry Andricforeach vti = AllIntegerVectors in { 2140fe6060f1SDimitry Andric // Emit shift by 1 as an add since it might be faster. 214106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 2142fe6060f1SDimitry Andric def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 214381ad6265SDimitry Andric (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)), 2144bdd1243dSDimitry Andric srcvalue, (vti.Mask true_mask), VLOpFrag), 2145fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 214606c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 21475f757f3fSDimitry Andric vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>; 2148fe6060f1SDimitry Andric} 2149fe6060f1SDimitry Andric 2150bdd1243dSDimitry Andric// 11.7. Vector Narrowing Integer Right Shift Instructions 2151bdd1243dSDimitry Andricdefm : VPatBinaryVL_WV_WX_WI<srl, "PseudoVNSRL">; 2152bdd1243dSDimitry Andricdefm : VPatBinaryVL_WV_WX_WI<sra, "PseudoVNSRA">; 215381ad6265SDimitry Andric 215481ad6265SDimitry Andricdefm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">; 215581ad6265SDimitry Andricdefm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">; 215681ad6265SDimitry Andricdefm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">; 215781ad6265SDimitry Andricdefm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">; 215881ad6265SDimitry Andricdefm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">; 215981ad6265SDimitry Andricdefm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">; 216004eeddc0SDimitry Andric 216106c3fb27SDimitry Andricdefm : VPatNarrowShiftVL_WV<riscv_srl_vl, "PseudoVNSRL">; 216206c3fb27SDimitry Andricdefm : VPatNarrowShiftVL_WV<riscv_sra_vl, "PseudoVNSRA">; 216306c3fb27SDimitry Andric 2164bdd1243dSDimitry Andricdefm : VPatBinaryNVL_WV_WX_WI<riscv_vnsrl_vl, "PseudoVNSRL">; 2165bdd1243dSDimitry Andric 2166fe6060f1SDimitry Andricforeach vtiTowti = AllWidenableIntVectors in { 2167fe6060f1SDimitry Andric defvar vti = vtiTowti.Vti; 2168fe6060f1SDimitry Andric defvar wti = vtiTowti.Wti; 216906c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 217006c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 2171fe6060f1SDimitry Andric def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 217281ad6265SDimitry Andric (vti.Mask V0), 2173fe6060f1SDimitry Andric VLOpFrag)), 2174bdd1243dSDimitry Andric (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX#"_MASK") 2175bdd1243dSDimitry Andric (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0, 2176bdd1243dSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 2177fe6060f1SDimitry Andric} 2178fe6060f1SDimitry Andric 2179bdd1243dSDimitry Andric// 11.8. Vector Integer Comparison Instructions 2180fe6060f1SDimitry Andricforeach vti = AllIntegerVectors in { 218106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 2182fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 2183fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 2184fe6060f1SDimitry Andric 2185fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 2186fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 2187fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 2188fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 2189fe6060f1SDimitry Andric 2190fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 2191fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 2192fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 2193fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 2194fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 2195fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 2196fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 2197fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 2198fe6060f1SDimitry Andric // There is no VMSGE(U)_VX instruction 2199fe6060f1SDimitry Andric 2200fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 2201fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 2202fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 2203fe6060f1SDimitry Andric defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 220404eeddc0SDimitry Andric defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 220504eeddc0SDimitry Andric defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 2206fe6060f1SDimitry Andric 220781ad6265SDimitry Andric defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT, 220806c3fb27SDimitry Andric SplatPat_simm5_plus1>; 220981ad6265SDimitry Andric defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT, 2210fe6060f1SDimitry Andric SplatPat_simm5_plus1_nonzero>; 221181ad6265SDimitry Andric defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE, 2212fe6060f1SDimitry Andric SplatPat_simm5_plus1>; 221381ad6265SDimitry Andric defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE, 2214fe6060f1SDimitry Andric SplatPat_simm5_plus1_nonzero>; 221506c3fb27SDimitry Andric } 2216fe6060f1SDimitry Andric} // foreach vti = AllIntegerVectors 2217fe6060f1SDimitry Andric 2218bdd1243dSDimitry Andric// 11.9. Vector Integer Min/Max Instructions 2219fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 2220fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 2221fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 2222fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 2223fe6060f1SDimitry Andric 2224bdd1243dSDimitry Andric// 11.10. Vector Single-Width Integer Multiply Instructions 2225fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 222606c3fb27SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH", IntegerVectorsExceptI64>; 222706c3fb27SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU", IntegerVectorsExceptI64>; 222806c3fb27SDimitry Andric// vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*. 222906c3fb27SDimitry Andriclet Predicates = [HasVInstructionsFullMultiply] in { 223006c3fb27SDimitry Andric defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH", I64IntegerVectors>; 223106c3fb27SDimitry Andric defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU", I64IntegerVectors>; 223206c3fb27SDimitry Andric} 2233fe6060f1SDimitry Andric 2234bdd1243dSDimitry Andric// 11.11. Vector Integer Divide Instructions 223506c3fb27SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU", isSEWAware=1>; 223606c3fb27SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV", isSEWAware=1>; 223706c3fb27SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU", isSEWAware=1>; 223806c3fb27SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM", isSEWAware=1>; 2239fe6060f1SDimitry Andric 2240bdd1243dSDimitry Andric// 11.12. Vector Widening Integer Multiply Instructions 2241fe6060f1SDimitry Andricdefm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 2242fe6060f1SDimitry Andricdefm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 22431fd87a68SDimitry Andricdefm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; 2244fe6060f1SDimitry Andric 2245bdd1243dSDimitry Andric// 11.13 Vector Single-Width Integer Multiply-Add Instructions 224681ad6265SDimitry Andricdefm : VPatMultiplyAddVL_VV_VX<riscv_add_vl, "PseudoVMADD">; 224781ad6265SDimitry Andricdefm : VPatMultiplyAddVL_VV_VX<riscv_sub_vl, "PseudoVNMSUB">; 2248bdd1243dSDimitry Andricdefm : VPatMultiplyAccVL_VV_VX<riscv_add_vl_oneuse, "PseudoVMACC">; 2249bdd1243dSDimitry Andricdefm : VPatMultiplyAccVL_VV_VX<riscv_sub_vl_oneuse, "PseudoVNMSAC">; 2250fe6060f1SDimitry Andric 2251bdd1243dSDimitry Andric// 11.14. Vector Widening Integer Multiply-Add Instructions 225206c3fb27SDimitry Andricdefm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmacc_vl, "PseudoVWMACC">; 225306c3fb27SDimitry Andricdefm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmaccu_vl, "PseudoVWMACCU">; 225406c3fb27SDimitry Andricdefm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmaccsu_vl, "PseudoVWMACCSU">; 2255fe6060f1SDimitry Andricforeach vtiTowti = AllWidenableIntVectors in { 2256fe6060f1SDimitry Andric defvar vti = vtiTowti.Vti; 2257fe6060f1SDimitry Andric defvar wti = vtiTowti.Wti; 225806c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 225906c3fb27SDimitry Andric GetVTypePredicates<wti>.Predicates) in 226006c3fb27SDimitry Andric def : Pat<(riscv_vwmaccsu_vl (vti.Vector vti.RegClass:$rs1), 226181ad6265SDimitry Andric (SplatPat XLenVT:$rs2), 226206c3fb27SDimitry Andric (wti.Vector wti.RegClass:$rd), 226306c3fb27SDimitry Andric (vti.Mask V0), VLOpFrag), 226406c3fb27SDimitry Andric (!cast<Instruction>("PseudoVWMACCUS_VX_"#vti.LMul.MX#"_MASK") 226581ad6265SDimitry Andric wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1, 226606c3fb27SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2267fe6060f1SDimitry Andric} 2268fe6060f1SDimitry Andric 2269bdd1243dSDimitry Andric// 11.15. Vector Integer Merge Instructions 2270fe6060f1SDimitry Andricforeach vti = AllIntegerVectors in { 227106c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 2272cb14a3feSDimitry Andric def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask V0), 227304eeddc0SDimitry Andric vti.RegClass:$rs1, 227404eeddc0SDimitry Andric vti.RegClass:$rs2, 2275cb14a3feSDimitry Andric vti.RegClass:$merge, 227604eeddc0SDimitry Andric VLOpFrag)), 227706c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 2278cb14a3feSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 227904eeddc0SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 228004eeddc0SDimitry Andric 2281cb14a3feSDimitry Andric def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask V0), 228204eeddc0SDimitry Andric (SplatPat XLenVT:$rs1), 228304eeddc0SDimitry Andric vti.RegClass:$rs2, 2284cb14a3feSDimitry Andric vti.RegClass:$merge, 228504eeddc0SDimitry Andric VLOpFrag)), 228606c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 2287cb14a3feSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1, 228804eeddc0SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 228904eeddc0SDimitry Andric 2290cb14a3feSDimitry Andric def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask V0), 229104eeddc0SDimitry Andric (SplatPat_simm5 simm5:$rs1), 229204eeddc0SDimitry Andric vti.RegClass:$rs2, 2293cb14a3feSDimitry Andric vti.RegClass:$merge, 229404eeddc0SDimitry Andric VLOpFrag)), 229506c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 2296cb14a3feSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, simm5:$rs1, 229704eeddc0SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 2298fe6060f1SDimitry Andric } 229906c3fb27SDimitry Andric} 2300fe6060f1SDimitry Andric 2301bdd1243dSDimitry Andric// 11.16. Vector Integer Move Instructions 230206c3fb27SDimitry Andricforeach vti = AllVectors in { 230306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 230406c3fb27SDimitry Andric def : Pat<(vti.Vector (riscv_vmv_v_v_vl vti.RegClass:$passthru, 230506c3fb27SDimitry Andric vti.RegClass:$rs2, VLOpFrag)), 230606c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX) 230706c3fb27SDimitry Andric vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>; 230806c3fb27SDimitry Andric} 230906c3fb27SDimitry Andric 2310fe6060f1SDimitry Andricforeach vti = AllIntegerVectors in { 231106c3fb27SDimitry Andric def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, GPR:$rs2, VLOpFrag)), 2312fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 231306c3fb27SDimitry Andric vti.RegClass:$passthru, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>; 2314fe6060f1SDimitry Andric defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 231506c3fb27SDimitry Andric def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, (ImmPat simm5:$imm5), 2316fe6060f1SDimitry Andric VLOpFrag)), 2317fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 231806c3fb27SDimitry Andric vti.RegClass:$passthru, simm5:$imm5, GPR:$vl, vti.Log2SEW, TU_MU)>; 231906c3fb27SDimitry Andric } 2320fe6060f1SDimitry Andric} 2321fe6060f1SDimitry Andric 2322bdd1243dSDimitry Andric// 12. Vector Fixed-Point Arithmetic Instructions 2323bdd1243dSDimitry Andric 2324fe6060f1SDimitry Andric// 12.1. Vector Single-Width Saturating Add and Subtract 2325fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 2326fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 2327fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 2328fe6060f1SDimitry Andricdefm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 2329fe6060f1SDimitry Andric 23301db9f3b2SDimitry Andric// 12.2. Vector Single-Width Averaging Add and Subtract 2331297eecfbSDimitry Andricdefm : VPatAVGADDVL_VV_VX_RM<riscv_avgflooru_vl, 0b10>; 2332297eecfbSDimitry Andricdefm : VPatAVGADDVL_VV_VX_RM<riscv_avgceilu_vl, 0b00>; 23331db9f3b2SDimitry Andric 2334647cbc5dSDimitry Andric// 12.5. Vector Narrowing Fixed-Point Clip Instructions 2335647cbc5dSDimitry Andricclass VPatTruncSatClipMaxMinBase<string inst, 2336647cbc5dSDimitry Andric VTypeInfo vti, 2337647cbc5dSDimitry Andric VTypeInfo wti, 2338647cbc5dSDimitry Andric SDPatternOperator op1, 2339647cbc5dSDimitry Andric int op1_value, 2340647cbc5dSDimitry Andric SDPatternOperator op2, 2341647cbc5dSDimitry Andric int op2_value> : 2342647cbc5dSDimitry Andric Pat<(vti.Vector (riscv_trunc_vector_vl 2343647cbc5dSDimitry Andric (wti.Vector (op1 2344647cbc5dSDimitry Andric (wti.Vector (op2 2345647cbc5dSDimitry Andric (wti.Vector wti.RegClass:$rs1), 2346647cbc5dSDimitry Andric (wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), op2_value, (XLenVT srcvalue))), 2347647cbc5dSDimitry Andric (wti.Vector undef),(wti.Mask V0), VLOpFrag)), 2348647cbc5dSDimitry Andric (wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), op1_value, (XLenVT srcvalue))), 2349647cbc5dSDimitry Andric (wti.Vector undef), (wti.Mask V0), VLOpFrag)), 2350647cbc5dSDimitry Andric (vti.Mask V0), VLOpFrag)), 2351647cbc5dSDimitry Andric (!cast<Instruction>(inst#"_WI_"#vti.LMul.MX#"_MASK") 2352647cbc5dSDimitry Andric (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0, 2353647cbc5dSDimitry Andric (vti.Mask V0), 0, GPR:$vl, vti.Log2SEW, TA_MA)>; 2354647cbc5dSDimitry Andric 2355647cbc5dSDimitry Andricclass VPatTruncSatClipUMin<VTypeInfo vti, 2356647cbc5dSDimitry Andric VTypeInfo wti, 2357647cbc5dSDimitry Andric int uminval> : 2358647cbc5dSDimitry Andric Pat<(vti.Vector (riscv_trunc_vector_vl 2359647cbc5dSDimitry Andric (wti.Vector (riscv_umin_vl 2360647cbc5dSDimitry Andric (wti.Vector wti.RegClass:$rs1), 2361647cbc5dSDimitry Andric (wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), uminval, (XLenVT srcvalue))), 2362647cbc5dSDimitry Andric (wti.Vector undef), (wti.Mask V0), VLOpFrag)), 2363647cbc5dSDimitry Andric (vti.Mask V0), VLOpFrag)), 2364647cbc5dSDimitry Andric (!cast<Instruction>("PseudoVNCLIPU_WI_"#vti.LMul.MX#"_MASK") 2365647cbc5dSDimitry Andric (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0, 2366647cbc5dSDimitry Andric (vti.Mask V0), 0, GPR:$vl, vti.Log2SEW, TA_MA)>; 2367647cbc5dSDimitry Andric 2368647cbc5dSDimitry Andricmulticlass VPatTruncSatClipMaxMin<string inst, VTypeInfo vti, VTypeInfo wti, 2369647cbc5dSDimitry Andric SDPatternOperator max, int maxval, SDPatternOperator min, int minval> { 2370647cbc5dSDimitry Andric def : VPatTruncSatClipMaxMinBase<inst, vti, wti, max, maxval, min, minval>; 2371647cbc5dSDimitry Andric def : VPatTruncSatClipMaxMinBase<inst, vti, wti, min, minval, max, maxval>; 2372647cbc5dSDimitry Andric} 2373647cbc5dSDimitry Andric 2374647cbc5dSDimitry Andricmulticlass VPatTruncSatClip<VTypeInfo vti, VTypeInfo wti> { 2375647cbc5dSDimitry Andric defvar sew = vti.SEW; 2376647cbc5dSDimitry Andric defvar uminval = !sub(!shl(1, sew), 1); 2377647cbc5dSDimitry Andric defvar sminval = !sub(!shl(1, !sub(sew, 1)), 1); 2378647cbc5dSDimitry Andric defvar smaxval = !sub(0, !shl(1, !sub(sew, 1))); 2379647cbc5dSDimitry Andric 2380647cbc5dSDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 2381647cbc5dSDimitry Andric GetVTypePredicates<wti>.Predicates) in { 2382647cbc5dSDimitry Andric defm : VPatTruncSatClipMaxMin<"PseudoVNCLIP", vti, wti, riscv_smin_vl, 2383647cbc5dSDimitry Andric sminval, riscv_smax_vl, smaxval>; 2384647cbc5dSDimitry Andric def : VPatTruncSatClipUMin<vti, wti, uminval>; 2385647cbc5dSDimitry Andric } 2386647cbc5dSDimitry Andric 2387647cbc5dSDimitry Andric} 2388647cbc5dSDimitry Andric 2389647cbc5dSDimitry Andricforeach vtiToWti = AllWidenableIntVectors in 2390647cbc5dSDimitry Andric defm : VPatTruncSatClip<vtiToWti.Vti, vtiToWti.Wti>; 2391647cbc5dSDimitry Andric 2392bdd1243dSDimitry Andric// 13. Vector Floating-Point Instructions 2393fe6060f1SDimitry Andric 2394bdd1243dSDimitry Andric// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 239506c3fb27SDimitry Andricdefm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fadd_vl, "PseudoVFADD">; 239606c3fb27SDimitry Andricdefm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fsub_vl, "PseudoVFSUB">; 239706c3fb27SDimitry Andricdefm : VPatBinaryFPVL_R_VF_RM<any_riscv_fsub_vl, "PseudoVFRSUB">; 2398fe6060f1SDimitry Andric 2399bdd1243dSDimitry Andric// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 240006c3fb27SDimitry Andricdefm : VPatBinaryFPWVL_VV_VF_WV_WF_RM<riscv_vfwadd_vl, riscv_vfwadd_w_vl, "PseudoVFWADD">; 240106c3fb27SDimitry Andricdefm : VPatBinaryFPWVL_VV_VF_WV_WF_RM<riscv_vfwsub_vl, riscv_vfwsub_w_vl, "PseudoVFWSUB">; 240281ad6265SDimitry Andric 2403bdd1243dSDimitry Andric// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 240406c3fb27SDimitry Andricdefm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL">; 240506c3fb27SDimitry Andricdefm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", isSEWAware=1>; 240606c3fb27SDimitry Andricdefm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", isSEWAware=1>; 2407fe6060f1SDimitry Andric 2408bdd1243dSDimitry Andric// 13.5. Vector Widening Floating-Point Multiply Instructions 240906c3fb27SDimitry Andricdefm : VPatBinaryFPWVL_VV_VF_RM<riscv_vfwmul_vl, "PseudoVFWMUL">; 241081ad6265SDimitry Andric 2411bdd1243dSDimitry Andric// 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 241206c3fb27SDimitry Andricdefm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmadd_vl, "PseudoVFMADD">; 241306c3fb27SDimitry Andricdefm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmsub_vl, "PseudoVFMSUB">; 241406c3fb27SDimitry Andricdefm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmadd_vl, "PseudoVFNMADD">; 241506c3fb27SDimitry Andricdefm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmsub_vl, "PseudoVFNMSUB">; 241606c3fb27SDimitry Andricdefm : VPatFPMulAccVL_VV_VF_RM<riscv_vfmadd_vl_oneuse, "PseudoVFMACC">; 241706c3fb27SDimitry Andricdefm : VPatFPMulAccVL_VV_VF_RM<riscv_vfmsub_vl_oneuse, "PseudoVFMSAC">; 241806c3fb27SDimitry Andricdefm : VPatFPMulAccVL_VV_VF_RM<riscv_vfnmadd_vl_oneuse, "PseudoVFNMACC">; 241906c3fb27SDimitry Andricdefm : VPatFPMulAccVL_VV_VF_RM<riscv_vfnmsub_vl_oneuse, "PseudoVFNMSAC">; 2420fe6060f1SDimitry Andric 2421bdd1243dSDimitry Andric// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 242206c3fb27SDimitry Andricdefm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmadd_vl, "PseudoVFWMACC">; 242306c3fb27SDimitry Andricdefm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwnmadd_vl, "PseudoVFWNMACC">; 242406c3fb27SDimitry Andricdefm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmsub_vl, "PseudoVFWMSAC">; 242506c3fb27SDimitry Andricdefm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwnmsub_vl, "PseudoVFWNMSAC">; 2426fe6060f1SDimitry Andric 2427bdd1243dSDimitry Andric// 13.11. Vector Floating-Point MIN/MAX Instructions 24285f757f3fSDimitry Andricdefm : VPatBinaryFPVL_VV_VF<riscv_vfmin_vl, "PseudoVFMIN">; 24295f757f3fSDimitry Andricdefm : VPatBinaryFPVL_VV_VF<riscv_vfmax_vl, "PseudoVFMAX">; 2430fe6060f1SDimitry Andric 2431bdd1243dSDimitry Andric// 13.13. Vector Floating-Point Compare Instructions 243206c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETEQ, 243306c3fb27SDimitry Andric "PseudoVMFEQ", "PseudoVMFEQ">; 243406c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETOEQ, 243506c3fb27SDimitry Andric "PseudoVMFEQ", "PseudoVMFEQ">; 243606c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETNE, 243706c3fb27SDimitry Andric "PseudoVMFNE", "PseudoVMFNE">; 243806c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETUNE, 243906c3fb27SDimitry Andric "PseudoVMFNE", "PseudoVMFNE">; 244006c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETLT, 244106c3fb27SDimitry Andric "PseudoVMFLT", "PseudoVMFGT">; 244206c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETOLT, 244306c3fb27SDimitry Andric "PseudoVMFLT", "PseudoVMFGT">; 244406c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETLE, 244506c3fb27SDimitry Andric "PseudoVMFLE", "PseudoVMFGE">; 244606c3fb27SDimitry Andricdefm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETOLE, 244706c3fb27SDimitry Andric "PseudoVMFLE", "PseudoVMFGE">; 2448fe6060f1SDimitry Andric 2449fe6060f1SDimitry Andricforeach vti = AllFloatVectors in { 245006c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 2451bdd1243dSDimitry Andric // 13.8. Vector Floating-Point Square-Root Instruction 245206c3fb27SDimitry Andric def : Pat<(any_riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask V0), 2453fe6060f1SDimitry Andric VLOpFrag), 245406c3fb27SDimitry Andric (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX # "_E" # vti.SEW # "_MASK") 2455bdd1243dSDimitry Andric (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, 245606c3fb27SDimitry Andric (vti.Mask V0), 245706c3fb27SDimitry Andric // Value to indicate no rounding mode change in 245806c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 245906c3fb27SDimitry Andric FRM_DYN, 246006c3fb27SDimitry Andric GPR:$vl, vti.Log2SEW, TA_MA)>; 2461fe6060f1SDimitry Andric 2462bdd1243dSDimitry Andric // 13.12. Vector Floating-Point Sign-Injection Instructions 2463bdd1243dSDimitry Andric def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), 2464fe6060f1SDimitry Andric VLOpFrag), 2465bdd1243dSDimitry Andric (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX #"_MASK") 2466bdd1243dSDimitry Andric (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs, 2467bdd1243dSDimitry Andric vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 2468bdd1243dSDimitry Andric TA_MA)>; 2469fe6060f1SDimitry Andric // Handle fneg with VFSGNJN using the same input for both operands. 247081ad6265SDimitry Andric def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), 2471fe6060f1SDimitry Andric VLOpFrag), 247281ad6265SDimitry Andric (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX #"_MASK") 247381ad6265SDimitry Andric (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs, 247481ad6265SDimitry Andric vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 2475bdd1243dSDimitry Andric TA_MA)>; 247681ad6265SDimitry Andric 2477fe6060f1SDimitry Andric def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 2478fe6060f1SDimitry Andric (vti.Vector vti.RegClass:$rs2), 2479bdd1243dSDimitry Andric vti.RegClass:$merge, 2480bdd1243dSDimitry Andric (vti.Mask V0), 2481fe6060f1SDimitry Andric VLOpFrag), 2482bdd1243dSDimitry Andric (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX#"_MASK") 2483bdd1243dSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs1, 2484bdd1243dSDimitry Andric vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 2485bdd1243dSDimitry Andric TAIL_AGNOSTIC)>; 2486bdd1243dSDimitry Andric 2487fe6060f1SDimitry Andric def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 2488fe6060f1SDimitry Andric (riscv_fneg_vl vti.RegClass:$rs2, 2489fe6060f1SDimitry Andric (vti.Mask true_mask), 2490fe6060f1SDimitry Andric VLOpFrag), 2491bdd1243dSDimitry Andric srcvalue, 2492fe6060f1SDimitry Andric (vti.Mask true_mask), 2493fe6060f1SDimitry Andric VLOpFrag), 2494fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 249506c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), 24965f757f3fSDimitry Andric vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>; 2497fe6060f1SDimitry Andric 2498fe6060f1SDimitry Andric def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 2499fe6060f1SDimitry Andric (SplatFPOp vti.ScalarRegClass:$rs2), 2500bdd1243dSDimitry Andric vti.RegClass:$merge, 2501bdd1243dSDimitry Andric (vti.Mask V0), 2502fe6060f1SDimitry Andric VLOpFrag), 2503bdd1243dSDimitry Andric (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX#"_MASK") 2504bdd1243dSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs1, 2505bdd1243dSDimitry Andric vti.ScalarRegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 2506bdd1243dSDimitry Andric TAIL_AGNOSTIC)>; 2507bdd1243dSDimitry Andric 2508bdd1243dSDimitry Andric // Rounding without exception to implement nearbyint. 250906c3fb27SDimitry Andric def : Pat<(any_riscv_vfround_noexcept_vl (vti.Vector vti.RegClass:$rs1), 2510bdd1243dSDimitry Andric (vti.Mask V0), VLOpFrag), 2511bdd1243dSDimitry Andric (!cast<Instruction>("PseudoVFROUND_NOEXCEPT_V_" # vti.LMul.MX #"_MASK") 2512bdd1243dSDimitry Andric (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, 2513bdd1243dSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 251406c3fb27SDimitry Andric 251506c3fb27SDimitry Andric // 14.14. Vector Floating-Point Classify Instruction 251606c3fb27SDimitry Andric def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2), 25175f757f3fSDimitry Andric (vti.Mask V0), VLOpFrag), 25185f757f3fSDimitry Andric (!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX #"_MASK") 25195f757f3fSDimitry Andric (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, 25205f757f3fSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; 252106c3fb27SDimitry Andric } 2522fe6060f1SDimitry Andric} 2523fe6060f1SDimitry Andric 2524fe6060f1SDimitry Andricforeach fvti = AllFloatVectors in { 2525fe6060f1SDimitry Andric // Floating-point vselects: 2526bdd1243dSDimitry Andric // 11.15. Vector Integer Merge Instructions 2527bdd1243dSDimitry Andric // 13.15. Vector Floating-Point Merge Instruction 25285f757f3fSDimitry Andric defvar ivti = GetIntVTypeInfo<fvti>.Vti; 25295f757f3fSDimitry Andric let Predicates = GetVTypePredicates<ivti>.Predicates in { 2530cb14a3feSDimitry Andric def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0), 253104eeddc0SDimitry Andric fvti.RegClass:$rs1, 253204eeddc0SDimitry Andric fvti.RegClass:$rs2, 2533cb14a3feSDimitry Andric fvti.RegClass:$merge, 253404eeddc0SDimitry Andric VLOpFrag)), 253506c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 2536cb14a3feSDimitry Andric fvti.RegClass:$merge, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 253704eeddc0SDimitry Andric GPR:$vl, fvti.Log2SEW)>; 253804eeddc0SDimitry Andric 2539cb14a3feSDimitry Andric def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0), 25401db9f3b2SDimitry Andric (SplatFPOp (SelectFPImm (XLenVT GPR:$imm))), 25411db9f3b2SDimitry Andric fvti.RegClass:$rs2, 25421db9f3b2SDimitry Andric fvti.RegClass:$merge, 25431db9f3b2SDimitry Andric VLOpFrag)), 25441db9f3b2SDimitry Andric (!cast<Instruction>("PseudoVMERGE_VXM_"#fvti.LMul.MX) 25451db9f3b2SDimitry Andric fvti.RegClass:$merge, fvti.RegClass:$rs2, GPR:$imm, (fvti.Mask V0), 25461db9f3b2SDimitry Andric GPR:$vl, fvti.Log2SEW)>; 25471db9f3b2SDimitry Andric 25481db9f3b2SDimitry Andric 25491db9f3b2SDimitry Andric def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0), 25505f757f3fSDimitry Andric (SplatFPOp (fvti.Scalar fpimm0)), 25515f757f3fSDimitry Andric fvti.RegClass:$rs2, 2552cb14a3feSDimitry Andric fvti.RegClass:$merge, 25535f757f3fSDimitry Andric VLOpFrag)), 25545f757f3fSDimitry Andric (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 2555cb14a3feSDimitry Andric fvti.RegClass:$merge, fvti.RegClass:$rs2, 0, (fvti.Mask V0), 25565f757f3fSDimitry Andric GPR:$vl, fvti.Log2SEW)>; 25575f757f3fSDimitry Andric } 25585f757f3fSDimitry Andric 25595f757f3fSDimitry Andric let Predicates = GetVTypePredicates<fvti>.Predicates in { 2560cb14a3feSDimitry Andric def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0), 256104eeddc0SDimitry Andric (SplatFPOp fvti.ScalarRegClass:$rs1), 256204eeddc0SDimitry Andric fvti.RegClass:$rs2, 2563cb14a3feSDimitry Andric fvti.RegClass:$merge, 256404eeddc0SDimitry Andric VLOpFrag)), 256506c3fb27SDimitry Andric (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 2566cb14a3feSDimitry Andric fvti.RegClass:$merge, fvti.RegClass:$rs2, 256704eeddc0SDimitry Andric (fvti.Scalar fvti.ScalarRegClass:$rs1), 256804eeddc0SDimitry Andric (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 256904eeddc0SDimitry Andric 2570bdd1243dSDimitry Andric // 13.16. Vector Floating-Point Move Instruction 2571fe6060f1SDimitry Andric // If we're splatting fpimm0, use vmv.v.x vd, x0. 2572fe6060f1SDimitry Andric def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 257381ad6265SDimitry Andric fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)), 257406c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 257506c3fb27SDimitry Andric $passthru, 0, GPR:$vl, fvti.Log2SEW, TU_MU)>; 2576fe6060f1SDimitry Andric def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 257706c3fb27SDimitry Andric fvti.Vector:$passthru, (fvti.Scalar (SelectFPImm (XLenVT GPR:$imm))), VLOpFrag)), 257806c3fb27SDimitry Andric (!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX) 257906c3fb27SDimitry Andric $passthru, GPR:$imm, GPR:$vl, fvti.Log2SEW, TU_MU)>; 258006c3fb27SDimitry Andric 258181ad6265SDimitry Andric def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 258281ad6265SDimitry Andric fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 258381ad6265SDimitry Andric (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 258406c3fb27SDimitry Andric fvti.LMul.MX) 258581ad6265SDimitry Andric $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), 258606c3fb27SDimitry Andric GPR:$vl, fvti.Log2SEW, TU_MU)>; 258706c3fb27SDimitry Andric } 258806c3fb27SDimitry Andric} 2589fe6060f1SDimitry Andric 2590bdd1243dSDimitry Andric// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 259106c3fb27SDimitry Andricdefm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">; 259206c3fb27SDimitry Andricdefm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">; 2593bdd1243dSDimitry Andricdefm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_RM_XU_F_V">; 259406c3fb27SDimitry Andricdefm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_RM_X_F_V">; 2595fe6060f1SDimitry Andric 259606c3fb27SDimitry Andricdefm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFCVT_RTZ_XU_F_V">; 259706c3fb27SDimitry Andricdefm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFCVT_RTZ_X_F_V">; 2598bdd1243dSDimitry Andric 259906c3fb27SDimitry Andricdefm : VPatConvertI2FPVL_V_RM<any_riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 260006c3fb27SDimitry Andricdefm : VPatConvertI2FPVL_V_RM<any_riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 2601bdd1243dSDimitry Andric 2602bdd1243dSDimitry Andricdefm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_RM_F_XU_V">; 2603bdd1243dSDimitry Andricdefm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_RM_F_X_V">; 2604bdd1243dSDimitry Andric 2605bdd1243dSDimitry Andric// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 260606c3fb27SDimitry Andricdefm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFWCVT_XU_F_V">; 260706c3fb27SDimitry Andricdefm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFWCVT_X_F_V">; 2608bdd1243dSDimitry Andricdefm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_RM_XU_F_V">; 2609bdd1243dSDimitry Andricdefm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_RM_X_F_V">; 2610bdd1243dSDimitry Andric 261106c3fb27SDimitry Andricdefm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 261206c3fb27SDimitry Andricdefm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">; 2613bdd1243dSDimitry Andric 261406c3fb27SDimitry Andricdefm : VPatWConvertI2FPVL_V<any_riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 261506c3fb27SDimitry Andricdefm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 2616bdd1243dSDimitry Andric 2617fe6060f1SDimitry Andricforeach fvtiToFWti = AllWidenableFloatVectors in { 2618fe6060f1SDimitry Andric defvar fvti = fvtiToFWti.Vti; 2619fe6060f1SDimitry Andric defvar fwti = fvtiToFWti.Wti; 26205f757f3fSDimitry Andric let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal], 26215f757f3fSDimitry Andric !listconcat(GetVTypePredicates<fvti>.Predicates, 26225f757f3fSDimitry Andric GetVTypePredicates<fwti>.Predicates)) in 262306c3fb27SDimitry Andric def : Pat<(fwti.Vector (any_riscv_fpextend_vl 262406c3fb27SDimitry Andric (fvti.Vector fvti.RegClass:$rs1), 262581ad6265SDimitry Andric (fvti.Mask V0), 2626fe6060f1SDimitry Andric VLOpFrag)), 262781ad6265SDimitry Andric (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK") 262881ad6265SDimitry Andric (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 262906c3fb27SDimitry Andric (fvti.Mask V0), 263006c3fb27SDimitry Andric GPR:$vl, fvti.Log2SEW, TA_MA)>; 2631fe6060f1SDimitry Andric} 2632fe6060f1SDimitry Andric 2633bdd1243dSDimitry Andric// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions 263406c3fb27SDimitry Andricdefm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_xu_f_vl, "PseudoVFNCVT_XU_F_W">; 263506c3fb27SDimitry Andricdefm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_x_f_vl, "PseudoVFNCVT_X_F_W">; 263606c3fb27SDimitry Andricdefm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_RM_XU_F_W">; 263706c3fb27SDimitry Andricdefm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_RM_X_F_W">; 2638bdd1243dSDimitry Andric 263906c3fb27SDimitry Andricdefm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 264006c3fb27SDimitry Andricdefm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F_W">; 2641bdd1243dSDimitry Andric 264206c3fb27SDimitry Andricdefm : VPatNConvertI2FPVL_W_RM<any_riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 264306c3fb27SDimitry Andricdefm : VPatNConvertI2FPVL_W_RM<any_riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 2644bdd1243dSDimitry Andric 264506c3fb27SDimitry Andricdefm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_RM_F_XU_W">; 264606c3fb27SDimitry Andricdefm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_RM_F_X_W">; 2647bdd1243dSDimitry Andric 2648fe6060f1SDimitry Andricforeach fvtiToFWti = AllWidenableFloatVectors in { 2649fe6060f1SDimitry Andric defvar fvti = fvtiToFWti.Vti; 2650fe6060f1SDimitry Andric defvar fwti = fvtiToFWti.Wti; 26515f757f3fSDimitry Andric // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable. 26525f757f3fSDimitry Andric let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal], 26535f757f3fSDimitry Andric !listconcat(GetVTypePredicates<fvti>.Predicates, 26545f757f3fSDimitry Andric GetVTypePredicates<fwti>.Predicates)) in { 265506c3fb27SDimitry Andric def : Pat<(fvti.Vector (any_riscv_fpround_vl 265606c3fb27SDimitry Andric (fwti.Vector fwti.RegClass:$rs1), 265706c3fb27SDimitry Andric (fwti.Mask V0), VLOpFrag)), 265881ad6265SDimitry Andric (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK") 265981ad6265SDimitry Andric (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 266081ad6265SDimitry Andric (fwti.Mask V0), 266106c3fb27SDimitry Andric // Value to indicate no rounding mode change in 266206c3fb27SDimitry Andric // RISCVInsertReadWriteCSR 266306c3fb27SDimitry Andric FRM_DYN, 266406c3fb27SDimitry Andric GPR:$vl, fvti.Log2SEW, TA_MA)>; 266506c3fb27SDimitry Andric 26665f757f3fSDimitry Andric let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, 26675f757f3fSDimitry Andric GetVTypePredicates<fwti>.Predicates) in 266806c3fb27SDimitry Andric def : Pat<(fvti.Vector (any_riscv_fncvt_rod_vl 266906c3fb27SDimitry Andric (fwti.Vector fwti.RegClass:$rs1), 267006c3fb27SDimitry Andric (fwti.Mask V0), VLOpFrag)), 267181ad6265SDimitry Andric (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_MASK") 267281ad6265SDimitry Andric (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 2673bdd1243dSDimitry Andric (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>; 2674fe6060f1SDimitry Andric } 2675fe6060f1SDimitry Andric} 2676fe6060f1SDimitry Andric 2677bdd1243dSDimitry Andric// 14. Vector Reduction Operations 2678bdd1243dSDimitry Andric 2679bdd1243dSDimitry Andric// 14.1. Vector Single-Width Integer Reduction Instructions 268006c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", is_float=0>; 268106c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", is_float=0>; 268206c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", is_float=0>; 268306c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", is_float=0>; 268406c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", is_float=0>; 268506c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", is_float=0>; 268606c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", is_float=0>; 268706c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", is_float=0>; 2688bdd1243dSDimitry Andric 2689bdd1243dSDimitry Andric// 14.2. Vector Widening Integer Reduction Instructions 269006c3fb27SDimitry Andricdefm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", is_float=0>; 269106c3fb27SDimitry Andricdefm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", is_float=0>; 269206c3fb27SDimitry Andricdefm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", is_float=0>; 269306c3fb27SDimitry Andricdefm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", is_float=0>; 269406c3fb27SDimitry Andricdefm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", is_float=0>; 2695bdd1243dSDimitry Andric 2696bdd1243dSDimitry Andric// 14.3. Vector Single-Width Floating-Point Reduction Instructions 269706c3fb27SDimitry Andricdefm : VPatReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", is_float=1>; 269806c3fb27SDimitry Andricdefm : VPatReductionVL_RM<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", is_float=1>; 269906c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", is_float=1>; 270006c3fb27SDimitry Andricdefm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", is_float=1>; 2701bdd1243dSDimitry Andric 2702bdd1243dSDimitry Andric// 14.4. Vector Widening Floating-Point Reduction Instructions 270306c3fb27SDimitry Andricdefm : VPatWidenReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, 270406c3fb27SDimitry Andric "PseudoVFWREDOSUM", is_float=1>; 270506c3fb27SDimitry Andricdefm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_SEQ_FADD_vl, 270606c3fb27SDimitry Andric riscv_fpextend_vl_oneuse, 270706c3fb27SDimitry Andric "PseudoVFWREDOSUM", is_float=1>; 270806c3fb27SDimitry Andricdefm : VPatWidenReductionVL_RM<rvv_vecreduce_FADD_vl, fpext_oneuse, 270906c3fb27SDimitry Andric "PseudoVFWREDUSUM", is_float=1>; 271006c3fb27SDimitry Andricdefm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_FADD_vl, 271106c3fb27SDimitry Andric riscv_fpextend_vl_oneuse, 271206c3fb27SDimitry Andric "PseudoVFWREDUSUM", is_float=1>; 2713bdd1243dSDimitry Andric 2714bdd1243dSDimitry Andric// 15. Vector Mask Instructions 2715bdd1243dSDimitry Andric 2716fe6060f1SDimitry Andricforeach mti = AllMasks in { 271706c3fb27SDimitry Andric let Predicates = [HasVInstructions] in { 2718bdd1243dSDimitry Andric // 15.1 Vector Mask-Register Logical Instructions 2719fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 2720fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 2721fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 2722fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 2723fe6060f1SDimitry Andric 2724fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 2725fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 2726fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2727fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 2728fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 2729fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2730fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 2731fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 2732fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2733fe6060f1SDimitry Andric 2734fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 2735fe6060f1SDimitry Andric (riscv_vmnot_vl VR:$rs2, VLOpFrag), 2736fe6060f1SDimitry Andric VLOpFrag)), 2737349cc55cSDimitry Andric (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 2738fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2739fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 2740fe6060f1SDimitry Andric (riscv_vmnot_vl VR:$rs2, VLOpFrag), 2741fe6060f1SDimitry Andric VLOpFrag)), 2742349cc55cSDimitry Andric (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 2743fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2744fe6060f1SDimitry Andric // XOR is associative so we need 2 patterns for VMXNOR. 2745fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 2746fe6060f1SDimitry Andric VLOpFrag), 2747fe6060f1SDimitry Andric VR:$rs2, VLOpFrag)), 2748fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 2749fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2750fe6060f1SDimitry Andric 2751fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 2752fe6060f1SDimitry Andric VLOpFrag), 2753fe6060f1SDimitry Andric VLOpFrag)), 2754fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 2755fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2756fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 2757fe6060f1SDimitry Andric VLOpFrag), 2758fe6060f1SDimitry Andric VLOpFrag)), 2759fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 2760fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2761fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 2762fe6060f1SDimitry Andric VLOpFrag), 2763fe6060f1SDimitry Andric VLOpFrag)), 2764fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 2765fe6060f1SDimitry Andric VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2766fe6060f1SDimitry Andric 2767fe6060f1SDimitry Andric // Match the not idiom to the vmnot.m pseudo. 2768fe6060f1SDimitry Andric def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 2769fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 2770fe6060f1SDimitry Andric VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 2771fe6060f1SDimitry Andric 2772bdd1243dSDimitry Andric // 15.2 Vector count population in mask vcpop.m 2773349cc55cSDimitry Andric def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 2774fe6060f1SDimitry Andric VLOpFrag)), 2775349cc55cSDimitry Andric (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 2776fe6060f1SDimitry Andric VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2777349cc55cSDimitry Andric def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 2778349cc55cSDimitry Andric VLOpFrag)), 2779349cc55cSDimitry Andric (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 2780349cc55cSDimitry Andric VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 2781bdd1243dSDimitry Andric 2782bdd1243dSDimitry Andric // 15.3 vfirst find-first-set mask bit 2783bdd1243dSDimitry Andric def : Pat<(XLenVT (riscv_vfirst_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 2784bdd1243dSDimitry Andric VLOpFrag)), 2785bdd1243dSDimitry Andric (!cast<Instruction>("PseudoVFIRST_M_" # mti.BX) 2786bdd1243dSDimitry Andric VR:$rs2, GPR:$vl, mti.Log2SEW)>; 2787bdd1243dSDimitry Andric def : Pat<(XLenVT (riscv_vfirst_vl (mti.Mask VR:$rs2), (mti.Mask V0), 2788bdd1243dSDimitry Andric VLOpFrag)), 2789bdd1243dSDimitry Andric (!cast<Instruction>("PseudoVFIRST_M_" # mti.BX # "_MASK") 2790bdd1243dSDimitry Andric VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 2791fe6060f1SDimitry Andric } 279206c3fb27SDimitry Andric} 2793fe6060f1SDimitry Andric 2794bdd1243dSDimitry Andric// 16. Vector Permutation Instructions 2795bdd1243dSDimitry Andric 2796bdd1243dSDimitry Andric// 16.1. Integer Scalar Move Instructions 2797*7a6dacacSDimitry Andricforeach vti = NoGroupIntegerVectors in { 279806c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 2799fe6060f1SDimitry Andric def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 2800fe6060f1SDimitry Andric vti.ScalarRegClass:$rs1, 2801fe6060f1SDimitry Andric VLOpFrag)), 2802*7a6dacacSDimitry Andric (PseudoVMV_S_X $merge, vti.ScalarRegClass:$rs1, GPR:$vl, 2803*7a6dacacSDimitry Andric vti.Log2SEW)>; 2804*7a6dacacSDimitry Andric } 2805*7a6dacacSDimitry Andric} 2806fe6060f1SDimitry Andric 2807*7a6dacacSDimitry Andric// 16.4. Vector Register Gather Instruction 2808*7a6dacacSDimitry Andricforeach vti = AllIntegerVectors in { 2809*7a6dacacSDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 281081ad6265SDimitry Andric def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 2811fe6060f1SDimitry Andric vti.RegClass:$rs1, 2812fe6060f1SDimitry Andric vti.RegClass:$merge, 2813bdd1243dSDimitry Andric (vti.Mask V0), 2814fe6060f1SDimitry Andric VLOpFrag)), 281506c3fb27SDimitry Andric (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK") 2816fe6060f1SDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 2817349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 281881ad6265SDimitry Andric def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 281981ad6265SDimitry Andric vti.RegClass:$merge, 2820bdd1243dSDimitry Andric (vti.Mask V0), 282181ad6265SDimitry Andric VLOpFrag)), 282281ad6265SDimitry Andric (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX#"_MASK") 282381ad6265SDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1, 282481ad6265SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 282581ad6265SDimitry Andric def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, 2826349cc55cSDimitry Andric uimm5:$imm, 2827349cc55cSDimitry Andric vti.RegClass:$merge, 2828bdd1243dSDimitry Andric (vti.Mask V0), 2829349cc55cSDimitry Andric VLOpFrag)), 2830349cc55cSDimitry Andric (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 2831349cc55cSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 2832349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 283306c3fb27SDimitry Andric } 2834fe6060f1SDimitry Andric 2835fe6060f1SDimitry Andric // emul = lmul * 16 / sew 2836fe6060f1SDimitry Andric defvar vlmul = vti.LMul; 2837fe6060f1SDimitry Andric defvar octuple_lmul = vlmul.octuple; 2838fe6060f1SDimitry Andric defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 2839fe6060f1SDimitry Andric if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 2840fe6060f1SDimitry Andric defvar emul_str = octuple_to_str<octuple_emul>.ret; 2841fe6060f1SDimitry Andric defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 284206c3fb27SDimitry Andric defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; 284306c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in 284481ad6265SDimitry Andric def : Pat<(vti.Vector 284581ad6265SDimitry Andric (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 2846fe6060f1SDimitry Andric (ivti.Vector ivti.RegClass:$rs1), 2847fe6060f1SDimitry Andric vti.RegClass:$merge, 2848bdd1243dSDimitry Andric (vti.Mask V0), 2849fe6060f1SDimitry Andric VLOpFrag)), 2850fe6060f1SDimitry Andric (!cast<Instruction>(inst#"_MASK") 2851fe6060f1SDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 2852349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2853fe6060f1SDimitry Andric } 2854fe6060f1SDimitry Andric} 2855fe6060f1SDimitry Andric 2856bdd1243dSDimitry Andric// 16.2. Floating-Point Scalar Move Instructions 2857*7a6dacacSDimitry Andricforeach vti = NoGroupFloatVectors in { 285806c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 2859fe6060f1SDimitry Andric def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 286004eeddc0SDimitry Andric (vti.Scalar (fpimm0)), 286104eeddc0SDimitry Andric VLOpFrag)), 2862*7a6dacacSDimitry Andric (PseudoVMV_S_X $merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>; 286306c3fb27SDimitry Andric def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 286406c3fb27SDimitry Andric (vti.Scalar (SelectFPImm (XLenVT GPR:$imm))), 286506c3fb27SDimitry Andric VLOpFrag)), 2866*7a6dacacSDimitry Andric (PseudoVMV_S_X $merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>; 2867*7a6dacacSDimitry Andric } 2868*7a6dacacSDimitry Andric} 2869*7a6dacacSDimitry Andric 2870*7a6dacacSDimitry Andricforeach vti = AllFloatVectors in { 2871*7a6dacacSDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 287204eeddc0SDimitry Andric def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 2873fe6060f1SDimitry Andric vti.ScalarRegClass:$rs1, 2874fe6060f1SDimitry Andric VLOpFrag)), 2875fe6060f1SDimitry Andric (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 2876fe6060f1SDimitry Andric vti.RegClass:$merge, 2877fe6060f1SDimitry Andric (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 287806c3fb27SDimitry Andric } 2879fe6060f1SDimitry Andric defvar ivti = GetIntVTypeInfo<vti>.Vti; 288006c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 288106c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in { 288281ad6265SDimitry Andric def : Pat<(vti.Vector 288381ad6265SDimitry Andric (riscv_vrgather_vv_vl vti.RegClass:$rs2, 2884fe6060f1SDimitry Andric (ivti.Vector vti.RegClass:$rs1), 2885fe6060f1SDimitry Andric vti.RegClass:$merge, 2886bdd1243dSDimitry Andric (vti.Mask V0), 2887fe6060f1SDimitry Andric VLOpFrag)), 288806c3fb27SDimitry Andric (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK") 2889fe6060f1SDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 2890349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 289181ad6265SDimitry Andric def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 289281ad6265SDimitry Andric vti.RegClass:$merge, 2893bdd1243dSDimitry Andric (vti.Mask V0), 289481ad6265SDimitry Andric VLOpFrag)), 289581ad6265SDimitry Andric (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX#"_MASK") 289681ad6265SDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1, 289781ad6265SDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 289881ad6265SDimitry Andric def : Pat<(vti.Vector 289981ad6265SDimitry Andric (riscv_vrgather_vx_vl vti.RegClass:$rs2, 2900349cc55cSDimitry Andric uimm5:$imm, 2901349cc55cSDimitry Andric vti.RegClass:$merge, 2902bdd1243dSDimitry Andric (vti.Mask V0), 2903349cc55cSDimitry Andric VLOpFrag)), 2904349cc55cSDimitry Andric (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 2905349cc55cSDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 2906349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 290706c3fb27SDimitry Andric } 2908fe6060f1SDimitry Andric 2909fe6060f1SDimitry Andric defvar vlmul = vti.LMul; 2910fe6060f1SDimitry Andric defvar octuple_lmul = vlmul.octuple; 2911fe6060f1SDimitry Andric defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 2912fe6060f1SDimitry Andric if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 2913fe6060f1SDimitry Andric defvar emul_str = octuple_to_str<octuple_emul>.ret; 2914fe6060f1SDimitry Andric defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 291506c3fb27SDimitry Andric defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; 291606c3fb27SDimitry Andric let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, 291706c3fb27SDimitry Andric GetVTypePredicates<ivti>.Predicates) in 291881ad6265SDimitry Andric def : Pat<(vti.Vector 291981ad6265SDimitry Andric (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 2920fe6060f1SDimitry Andric (ivti.Vector ivti.RegClass:$rs1), 2921fe6060f1SDimitry Andric vti.RegClass:$merge, 2922bdd1243dSDimitry Andric (vti.Mask V0), 2923fe6060f1SDimitry Andric VLOpFrag)), 2924fe6060f1SDimitry Andric (!cast<Instruction>(inst#"_MASK") 2925fe6060f1SDimitry Andric vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 2926349cc55cSDimitry Andric (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2927fe6060f1SDimitry Andric } 2928fe6060f1SDimitry Andric} 2929fe6060f1SDimitry Andric 2930fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 2931fe6060f1SDimitry Andric// Miscellaneous RISCVISD SDNodes 2932fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 2933fe6060f1SDimitry Andric 2934fe6060f1SDimitry Andricdef riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 2935fe6060f1SDimitry Andric [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 2936fe6060f1SDimitry Andric SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 2937fe6060f1SDimitry Andric 2938bdd1243dSDimitry Andricdef SDTRVVSlide : SDTypeProfile<1, 6, [ 2939fe6060f1SDimitry Andric SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 2940bdd1243dSDimitry Andric SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT>, 2941bdd1243dSDimitry Andric SDTCisVT<6, XLenVT> 2942fe6060f1SDimitry Andric]>; 294381ad6265SDimitry Andricdef SDTRVVSlide1 : SDTypeProfile<1, 5, [ 294481ad6265SDimitry Andric SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>, 294581ad6265SDimitry Andric SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, 294681ad6265SDimitry Andric SDTCisVT<5, XLenVT> 2947fe6060f1SDimitry Andric]>; 294806c3fb27SDimitry Andricdef SDTRVVFSlide1 : SDTypeProfile<1, 5, [ 294906c3fb27SDimitry Andric SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisFP<0>, 295006c3fb27SDimitry Andric SDTCisEltOfVec<3, 0>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, 295106c3fb27SDimitry Andric SDTCisVT<5, XLenVT> 295206c3fb27SDimitry Andric]>; 2953fe6060f1SDimitry Andric 2954fe6060f1SDimitry Andricdef riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 2955fe6060f1SDimitry Andricdef riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 2956fe6060f1SDimitry Andricdef riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 2957fe6060f1SDimitry Andricdef riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 295806c3fb27SDimitry Andricdef riscv_fslide1up_vl : SDNode<"RISCVISD::VFSLIDE1UP_VL", SDTRVVFSlide1, []>; 295906c3fb27SDimitry Andricdef riscv_fslide1down_vl : SDNode<"RISCVISD::VFSLIDE1DOWN_VL", SDTRVVFSlide1, []>; 2960fe6060f1SDimitry Andric 2961fe6060f1SDimitry Andricforeach vti = AllIntegerVectors in { 296206c3fb27SDimitry Andric let Predicates = GetVTypePredicates<vti>.Predicates in { 296306c3fb27SDimitry Andric def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask V0), 2964fe6060f1SDimitry Andric VLOpFrag)), 296506c3fb27SDimitry Andric (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX#"_MASK") 296606c3fb27SDimitry Andric (vti.Vector (IMPLICIT_DEF)), (vti.Mask V0), GPR:$vl, vti.Log2SEW, 296706c3fb27SDimitry Andric TAIL_AGNOSTIC)>; 296806c3fb27SDimitry Andric } 2969fe6060f1SDimitry Andric} 2970fe6060f1SDimitry Andric 29715f757f3fSDimitry Andricdefm : VPatSlideVL_VX_VI<riscv_slideup_vl, "PseudoVSLIDEUP">; 29725f757f3fSDimitry Andricdefm : VPatSlideVL_VX_VI<riscv_slidedown_vl, "PseudoVSLIDEDOWN">; 29735f757f3fSDimitry Andricdefm : VPatSlide1VL_VX<riscv_slide1up_vl, "PseudoVSLIDE1UP">; 29745f757f3fSDimitry Andricdefm : VPatSlide1VL_VF<riscv_fslide1up_vl, "PseudoVFSLIDE1UP">; 29755f757f3fSDimitry Andricdefm : VPatSlide1VL_VX<riscv_slide1down_vl, "PseudoVSLIDE1DOWN">; 29765f757f3fSDimitry Andricdefm : VPatSlide1VL_VF<riscv_fslide1down_vl, "PseudoVFSLIDE1DOWN">; 2977