1//===-- RISCVInstrInfoXCV.td - CORE-V instructions ---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the vendor extensions defined by Core-V extensions.
10//
11//===----------------------------------------------------------------------===//
12
13let DecoderNamespace = "XCVbitmanip" in {
14  class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
15                      string opcodestr, string argstr>
16      : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
17    bits<5> is3;
18    bits<5> is2;
19    let imm12 = {funct2, is3, is2};
20  }
21
22  class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
23                      Operand i3type = uimm5>
24      : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
25                          (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
26                          opcodestr, "$rd, $rs1, $is3, $is2">;
27
28  class CVBitManipRR<bits<7> funct7, string opcodestr>
29      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
30                (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
31
32  class CVBitManipR<bits<7> funct7, string opcodestr>
33      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
34                (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1"> {
35    let rs2 = 0b00000;
36  }
37}
38
39let Predicates = [HasVendorXCVbitmanip, IsRV32],
40    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
41  def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
42  def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
43
44  def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
45  def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
46  def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;
47
48  def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;
49  def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;
50
51  let Constraints = "$rd = $rd_wb" in {
52    def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
53                             (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
54                             "cv.insert", "$rd, $rs1, $is3, $is2">;
55    def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
56                             (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
57                             "cv.insertr", "$rd, $rs1, $rs2">;
58  }
59
60  def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
61  def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;
62
63  def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;
64  def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;
65  def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;
66  def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;
67  def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">;
68}
69
70class CVInstMac<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
71                string opcodestr, string argstr, list<dag> pattern>
72    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
73  bits<5> rs2;
74  bits<5> rs1;
75  bits<5> rd;
76
77  let Inst{31-25} = funct7;
78  let Inst{24-20} = rs2;
79  let Inst{19-15} = rs1;
80  let Inst{14-12} = funct3;
81  let Inst{11-7} = rd;
82  let Inst{6-0} = OPC_CUSTOM_1.Value;
83  let DecoderNamespace = "XCVmac";
84}
85
86class CVInstMac16I<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
87                   string opcodestr, string argstr, list<dag> pattern>
88    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
89  bits<5> imm5;
90  bits<5> rs2;
91  bits<5> rs1;
92  bits<5> rd;
93
94  let Inst{31-30} = funct2;
95  let Inst{29-25} = imm5;
96  let Inst{24-20} = rs2;
97  let Inst{19-15} = rs1;
98  let Inst{14-12} = funct3;
99  let Inst{11-7} = rd;
100  let Inst{6-0} = OPC_CUSTOM_2.Value;
101  let DecoderNamespace = "XCVmac";
102}
103
104let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0,
105    mayStore = 0, Constraints = "$rd = $rd_wb" in {
106  // 32x32 bit macs
107  def CV_MAC      : CVInstMac<0b1001000, 0b011, (outs GPR:$rd_wb),
108                              (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
109                              "cv.mac", "$rd, $rs1, $rs2", []>,
110                    Sched<[]>;
111  def CV_MSU      : CVInstMac<0b1001001, 0b011, (outs GPR:$rd_wb),
112                              (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
113                              "cv.msu", "$rd, $rs1, $rs2", []>,
114                    Sched<[]>;
115
116  // Signed 16x16 bit macs with imm
117  def CV_MACSN    : CVInstMac16I<0b00, 0b110, (outs GPR:$rd_wb),
118                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
119                                 "cv.macsn", "$rd, $rs1, $rs2, $imm5", []>,
120                    Sched<[]>;
121  def CV_MACHHSN  : CVInstMac16I<0b01, 0b110, (outs GPR:$rd_wb),
122                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
123                                 "cv.machhsn", "$rd, $rs1, $rs2, $imm5", []>,
124                    Sched<[]>;
125  def CV_MACSRN   : CVInstMac16I<0b10, 0b110, (outs GPR:$rd_wb),
126                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
127                                 "cv.macsrn", "$rd, $rs1, $rs2, $imm5", []>,
128                    Sched<[]>;
129  def CV_MACHHSRN : CVInstMac16I<0b11, 0b110, (outs GPR:$rd_wb),
130                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
131                                 "cv.machhsrn", "$rd, $rs1, $rs2, $imm5", []>,
132                    Sched<[]>;
133
134  // Unsigned 16x16 bit macs with imm
135  def CV_MACUN    : CVInstMac16I<0b00, 0b111, (outs GPR:$rd_wb),
136                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
137                                 "cv.macun", "$rd, $rs1, $rs2, $imm5", []>,
138                    Sched<[]>;
139  def CV_MACHHUN  : CVInstMac16I<0b01, 0b111, (outs GPR:$rd_wb),
140                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
141                                 "cv.machhun", "$rd, $rs1, $rs2, $imm5", []>,
142                    Sched<[]>;
143  def CV_MACURN   : CVInstMac16I<0b10, 0b111, (outs GPR:$rd_wb),
144                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
145                                 "cv.macurn", "$rd, $rs1, $rs2, $imm5", []>,
146                    Sched<[]>;
147  def CV_MACHHURN : CVInstMac16I<0b11, 0b111, (outs GPR:$rd_wb),
148                                 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
149                                 "cv.machhurn", "$rd, $rs1, $rs2, $imm5", []>,
150                    Sched<[]>;
151} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
152
153let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
154  // Signed 16x16 bit muls with imm
155  def CV_MULSN    : CVInstMac16I<0b00, 0b100, (outs GPR:$rd),
156                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
157                                 "cv.mulsn", "$rd, $rs1, $rs2, $imm5", []>,
158                    Sched<[]>;
159  def CV_MULHHSN  : CVInstMac16I<0b01, 0b100, (outs GPR:$rd),
160                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
161                                 "cv.mulhhsn", "$rd, $rs1, $rs2, $imm5", []>,
162                    Sched<[]>;
163  def CV_MULSRN   : CVInstMac16I<0b10, 0b100, (outs GPR:$rd),
164                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
165                                 "cv.mulsrn", "$rd, $rs1, $rs2, $imm5", []>,
166                    Sched<[]>;
167  def CV_MULHHSRN : CVInstMac16I<0b11, 0b100, (outs GPR:$rd),
168                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
169                                 "cv.mulhhsrn", "$rd, $rs1, $rs2, $imm5", []>,
170                    Sched<[]>;
171
172
173  // Unsigned 16x16 bit muls with imm
174  def CV_MULUN    : CVInstMac16I<0b00, 0b101, (outs GPR:$rd),
175                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
176                                 "cv.mulun", "$rd, $rs1, $rs2, $imm5", []>,
177                    Sched<[]>;
178  def CV_MULHHUN  : CVInstMac16I<0b01, 0b101, (outs GPR:$rd),
179                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
180                                 "cv.mulhhun", "$rd, $rs1, $rs2, $imm5", []>,
181                    Sched<[]>;
182  def CV_MULURN   : CVInstMac16I<0b10, 0b101, (outs GPR:$rd),
183                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
184                                 "cv.mulurn", "$rd, $rs1, $rs2, $imm5", []>,
185                    Sched<[]>;
186  def CV_MULHHURN : CVInstMac16I<0b11, 0b101, (outs GPR:$rd),
187                                 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
188                                 "cv.mulhhurn", "$rd, $rs1, $rs2, $imm5", []>,
189                    Sched<[]>;
190} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
191
192let Predicates = [HasVendorXCVmac, IsRV32] in {
193  // Xcvmac Pseudo Instructions
194  // Signed 16x16 bit muls
195  def : InstAlias<"cv.muls $rd1, $rs1, $rs2",
196                  (CV_MULSN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
197  def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2",
198                  (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
199
200  // Unsigned 16x16 bit muls
201  def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",
202                  (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
203  def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
204                  (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
205} // Predicates = [HasVendorXCVmac, IsRV32]
206