1//===-- RISCVInstrInfoZicbo.td - RISC-V CMO instructions ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the RISC-V instructions from the standard Base Cache
10// Management Operation ISA Extensions document (Zicbom, Zicboz, and Zicbop).
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Operand definitions.
16//===----------------------------------------------------------------------===//
17
18// A 12-bit signed immediate where the least significant five bits are zero.
19def simm12_lsb00000 : Operand<XLenVT>,
20                      ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
21  let ParserMatchClass = SImmAsmOperand<12, "Lsb00000">;
22  let EncoderMethod = "getImmOpValue";
23  let DecoderMethod = "decodeSImmOperand<12>";
24  let MCOperandPredicate = [{
25    int64_t Imm;
26    if (MCOp.evaluateAsConstantImm(Imm))
27      return isShiftedInt<7, 5>(Imm);
28    return MCOp.isBareSymbolRef();
29  }];
30  let OperandType = "OPERAND_SIMM12_LSB00000";
31  let OperandNamespace = "RISCVOp";
32}
33
34//===----------------------------------------------------------------------===//
35// Instruction Class Templates
36//===----------------------------------------------------------------------===//
37let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
38class CBO_r<bits<12> optype, string opcodestr>
39    : RVInstI<0b010, OPC_MISC_MEM, (outs), (ins GPRMemZeroOffset:$rs1),
40              opcodestr, "$rs1"> {
41  let imm12 = optype;
42  let rd = 0b00000;
43}
44
45let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
46class Prefetch_ri<bits<5> optype, string opcodestr>
47    : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPR:$rs1, simm12_lsb00000:$imm12),
48              opcodestr, "${imm12}(${rs1})"> {
49  let Inst{11-7} = 0b00000;
50  let rs2 = optype;
51}
52
53//===----------------------------------------------------------------------===//
54// Instructions
55//===----------------------------------------------------------------------===//
56
57let Predicates = [HasStdExtZicbom] in {
58def CBO_CLEAN : CBO_r<0b000000000001, "cbo.clean">, Sched<[]>;
59def CBO_FLUSH : CBO_r<0b000000000010, "cbo.flush">, Sched<[]>;
60def CBO_INVAL : CBO_r<0b000000000000, "cbo.inval">, Sched<[]>;
61} // Predicates = [HasStdExtZicbom]
62
63let Predicates = [HasStdExtZicboz] in {
64def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;
65} // Predicates = [HasStdExtZicboz]
66
67let Predicates = [HasStdExtZicbop] in {
68def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;
69def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;
70def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
71} // Predicates = [HasStdExtZicbop]
72
73//===----------------------------------------------------------------------===//
74// Patterns
75//===----------------------------------------------------------------------===//
76
77let Predicates = [HasStdExtZicbop] in {
78  // FIXME: Match address with offset
79  def : Pat<(prefetch GPR:$rs1, imm, imm, (XLenVT 0)),
80            (PREFETCH_I GPR:$rs1, 0)>;
81  def : Pat<(prefetch GPR:$rs1, (XLenVT 0), imm, (XLenVT 1)),
82            (PREFETCH_R GPR:$rs1, 0)>;
83  def : Pat<(prefetch GPR:$rs1, (XLenVT 1), imm, (XLenVT 1)),
84            (PREFETCH_W GPR:$rs1, 0)>;
85}
86