1*647cbc5dSDimitry Andric//===------ RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen -*------===// 2*647cbc5dSDimitry Andric// 3*647cbc5dSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*647cbc5dSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*647cbc5dSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*647cbc5dSDimitry Andric// 7*647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 8*647cbc5dSDimitry Andric 9*647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 10*647cbc5dSDimitry Andric// Instruction class templates 11*647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 12*647cbc5dSDimitry Andric 13*647cbc5dSDimitry Andricclass RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> : 14*647cbc5dSDimitry Andric RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> { 15*647cbc5dSDimitry Andric let Inst{15-13} = 0b011; 16*647cbc5dSDimitry Andric let Inst{12} = 0; 17*647cbc5dSDimitry Andric let Inst{11-7} = rs1val; 18*647cbc5dSDimitry Andric let Inst{6-2} = 0b00000; 19*647cbc5dSDimitry Andric let Inst{1-0} = 0b01; 20*647cbc5dSDimitry Andric let DecoderMethod = "decodeCSSPushPopchk"; 21*647cbc5dSDimitry Andric} 22*647cbc5dSDimitry Andric 23*647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 24*647cbc5dSDimitry Andric// Instructions 25*647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 26*647cbc5dSDimitry Andric 27*647cbc5dSDimitry Andriclet Predicates = [HasStdExtZicfiss] in { 28*647cbc5dSDimitry Andriclet Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 29*647cbc5dSDimitry Andricdef SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk", 30*647cbc5dSDimitry Andric "$rs1"> { 31*647cbc5dSDimitry Andric let rd = 0; 32*647cbc5dSDimitry Andric let imm12 = 0b110011011100; 33*647cbc5dSDimitry Andric} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 34*647cbc5dSDimitry Andric 35*647cbc5dSDimitry Andriclet Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 36*647cbc5dSDimitry Andricdef SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"> { 37*647cbc5dSDimitry Andric let imm12 = 0b110011011100; 38*647cbc5dSDimitry Andric let rs1 = 0b00000; 39*647cbc5dSDimitry Andric} 40*647cbc5dSDimitry Andric} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 41*647cbc5dSDimitry Andric 42*647cbc5dSDimitry Andriclet Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 43*647cbc5dSDimitry Andricdef SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2), 44*647cbc5dSDimitry Andric "sspush", "$rs2"> { 45*647cbc5dSDimitry Andric let rd = 0b00000; 46*647cbc5dSDimitry Andric let rs1 = 0b00000; 47*647cbc5dSDimitry Andric} 48*647cbc5dSDimitry Andric} // Predicates = [HasStdExtZicfiss] 49*647cbc5dSDimitry Andric 50*647cbc5dSDimitry Andriclet Predicates = [HasStdExtZicfiss, HasStdExtZcmop], 51*647cbc5dSDimitry Andric DecoderNamespace = "Zicfiss" in { 52*647cbc5dSDimitry Andriclet Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 53*647cbc5dSDimitry Andricdef C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">; 54*647cbc5dSDimitry Andric 55*647cbc5dSDimitry Andriclet Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 56*647cbc5dSDimitry Andricdef C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">; 57*647cbc5dSDimitry Andric} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop] 58*647cbc5dSDimitry Andric 59*647cbc5dSDimitry Andriclet Predicates = [HasStdExtZicfiss] in 60*647cbc5dSDimitry Andricdefm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">; 61*647cbc5dSDimitry Andric 62*647cbc5dSDimitry Andriclet Predicates = [HasStdExtZicfiss, IsRV64] in 63*647cbc5dSDimitry Andricdefm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">; 64*647cbc5dSDimitry Andric 65*647cbc5dSDimitry Andric//===----------------------------------------------------------------------===/ 66*647cbc5dSDimitry Andric// Compress Instruction tablegen backend. 67*647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 68*647cbc5dSDimitry Andric 69*647cbc5dSDimitry Andriclet Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in { 70*647cbc5dSDimitry Andricdef : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>; 71*647cbc5dSDimitry Andricdef : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>; 72*647cbc5dSDimitry Andric} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop] 73