1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVRegisterInfo.h" 14 #include "RISCV.h" 15 #include "RISCVMachineFunctionInfo.h" 16 #include "RISCVSubtarget.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/RegisterScavenging.h" 21 #include "llvm/CodeGen/TargetFrameLowering.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/Support/ErrorHandling.h" 24 25 #define GET_REGINFO_TARGET_DESC 26 #include "RISCVGenRegisterInfo.inc" 27 28 using namespace llvm; 29 30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive"); 31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive"); 32 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive"); 33 static_assert(RISCV::F31_H == RISCV::F0_H + 31, 34 "Register list not consecutive"); 35 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive"); 36 static_assert(RISCV::F31_F == RISCV::F0_F + 31, 37 "Register list not consecutive"); 38 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive"); 39 static_assert(RISCV::F31_D == RISCV::F0_D + 31, 40 "Register list not consecutive"); 41 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive"); 42 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive"); 43 44 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) 45 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, 46 /*PC*/0, HwMode) {} 47 48 const MCPhysReg * 49 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 50 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>(); 51 if (MF->getFunction().getCallingConv() == CallingConv::GHC) 52 return CSR_NoRegs_SaveList; 53 if (MF->getFunction().hasFnAttribute("interrupt")) { 54 if (Subtarget.hasStdExtD()) 55 return CSR_XLEN_F64_Interrupt_SaveList; 56 if (Subtarget.hasStdExtF()) 57 return CSR_XLEN_F32_Interrupt_SaveList; 58 return CSR_Interrupt_SaveList; 59 } 60 61 switch (Subtarget.getTargetABI()) { 62 default: 63 llvm_unreachable("Unrecognized ABI"); 64 case RISCVABI::ABI_ILP32: 65 case RISCVABI::ABI_LP64: 66 return CSR_ILP32_LP64_SaveList; 67 case RISCVABI::ABI_ILP32F: 68 case RISCVABI::ABI_LP64F: 69 return CSR_ILP32F_LP64F_SaveList; 70 case RISCVABI::ABI_ILP32D: 71 case RISCVABI::ABI_LP64D: 72 return CSR_ILP32D_LP64D_SaveList; 73 } 74 } 75 76 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 77 const RISCVFrameLowering *TFI = getFrameLowering(MF); 78 BitVector Reserved(getNumRegs()); 79 80 // Mark any registers requested to be reserved as such 81 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) { 82 if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg)) 83 markSuperRegs(Reserved, Reg); 84 } 85 86 // Use markSuperRegs to ensure any register aliases are also reserved 87 markSuperRegs(Reserved, RISCV::X0); // zero 88 markSuperRegs(Reserved, RISCV::X2); // sp 89 markSuperRegs(Reserved, RISCV::X3); // gp 90 markSuperRegs(Reserved, RISCV::X4); // tp 91 if (TFI->hasFP(MF)) 92 markSuperRegs(Reserved, RISCV::X8); // fp 93 // Reserve the base register if we need to realign the stack and allocate 94 // variable-sized objects at runtime. 95 if (TFI->hasBP(MF)) 96 markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp 97 98 // V registers for code generation. We handle them manually. 99 markSuperRegs(Reserved, RISCV::VL); 100 markSuperRegs(Reserved, RISCV::VTYPE); 101 markSuperRegs(Reserved, RISCV::VXSAT); 102 markSuperRegs(Reserved, RISCV::VXRM); 103 104 assert(checkAllSuperRegsMarked(Reserved)); 105 return Reserved; 106 } 107 108 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF, 109 MCRegister PhysReg) const { 110 return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg); 111 } 112 113 bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { 114 return PhysReg == RISCV::X0; 115 } 116 117 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { 118 return CSR_NoRegs_RegMask; 119 } 120 121 // Frame indexes representing locations of CSRs which are given a fixed location 122 // by save/restore libcalls. 123 static const std::map<unsigned, int> FixedCSRFIMap = { 124 {/*ra*/ RISCV::X1, -1}, 125 {/*s0*/ RISCV::X8, -2}, 126 {/*s1*/ RISCV::X9, -3}, 127 {/*s2*/ RISCV::X18, -4}, 128 {/*s3*/ RISCV::X19, -5}, 129 {/*s4*/ RISCV::X20, -6}, 130 {/*s5*/ RISCV::X21, -7}, 131 {/*s6*/ RISCV::X22, -8}, 132 {/*s7*/ RISCV::X23, -9}, 133 {/*s8*/ RISCV::X24, -10}, 134 {/*s9*/ RISCV::X25, -11}, 135 {/*s10*/ RISCV::X26, -12}, 136 {/*s11*/ RISCV::X27, -13} 137 }; 138 139 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 140 Register Reg, 141 int &FrameIdx) const { 142 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 143 if (!RVFI->useSaveRestoreLibCalls(MF)) 144 return false; 145 146 auto FII = FixedCSRFIMap.find(Reg); 147 if (FII == FixedCSRFIMap.end()) 148 return false; 149 150 FrameIdx = FII->second; 151 return true; 152 } 153 154 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 155 int SPAdj, unsigned FIOperandNum, 156 RegScavenger *RS) const { 157 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value"); 158 159 MachineInstr &MI = *II; 160 MachineFunction &MF = *MI.getParent()->getParent(); 161 MachineRegisterInfo &MRI = MF.getRegInfo(); 162 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); 163 DebugLoc DL = MI.getDebugLoc(); 164 165 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 166 Register FrameReg; 167 int Offset = getFrameLowering(MF) 168 ->getFrameIndexReference(MF, FrameIndex, FrameReg) 169 .getFixed() + 170 MI.getOperand(FIOperandNum + 1).getImm(); 171 172 if (!isInt<32>(Offset)) { 173 report_fatal_error( 174 "Frame offsets outside of the signed 32-bit range not supported"); 175 } 176 177 MachineBasicBlock &MBB = *MI.getParent(); 178 bool FrameRegIsKill = false; 179 180 if (!isInt<12>(Offset)) { 181 assert(isInt<32>(Offset) && "Int32 expected"); 182 // The offset won't fit in an immediate, so use a scratch register instead 183 // Modify Offset and FrameReg appropriately 184 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 185 TII->movImm(MBB, II, DL, ScratchReg, Offset); 186 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg) 187 .addReg(FrameReg) 188 .addReg(ScratchReg, RegState::Kill); 189 Offset = 0; 190 FrameReg = ScratchReg; 191 FrameRegIsKill = true; 192 } 193 194 MI.getOperand(FIOperandNum) 195 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill); 196 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 197 } 198 199 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 200 const TargetFrameLowering *TFI = getFrameLowering(MF); 201 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; 202 } 203 204 const uint32_t * 205 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF, 206 CallingConv::ID CC) const { 207 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); 208 209 if (CC == CallingConv::GHC) 210 return CSR_NoRegs_RegMask; 211 switch (Subtarget.getTargetABI()) { 212 default: 213 llvm_unreachable("Unrecognized ABI"); 214 case RISCVABI::ABI_ILP32: 215 case RISCVABI::ABI_LP64: 216 return CSR_ILP32_LP64_RegMask; 217 case RISCVABI::ABI_ILP32F: 218 case RISCVABI::ABI_LP64F: 219 return CSR_ILP32F_LP64F_RegMask; 220 case RISCVABI::ABI_ILP32D: 221 case RISCVABI::ABI_LP64D: 222 return CSR_ILP32D_LP64D_RegMask; 223 } 224 } 225