1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/RegisterScavenging.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 
24 #define GET_REGINFO_TARGET_DESC
25 #include "RISCVGenRegisterInfo.inc"
26 
27 using namespace llvm;
28 
29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
31 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
32 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
33               "Register list not consecutive");
34 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
35 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
36               "Register list not consecutive");
37 
38 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
39     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
40                            /*PC*/0, HwMode) {}
41 
42 const MCPhysReg *
43 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
44   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
45   if (MF->getFunction().hasFnAttribute("interrupt")) {
46     if (Subtarget.hasStdExtD())
47       return CSR_XLEN_F64_Interrupt_SaveList;
48     if (Subtarget.hasStdExtF())
49       return CSR_XLEN_F32_Interrupt_SaveList;
50     return CSR_Interrupt_SaveList;
51   }
52 
53   switch (Subtarget.getTargetABI()) {
54   default:
55     llvm_unreachable("Unrecognized ABI");
56   case RISCVABI::ABI_ILP32:
57   case RISCVABI::ABI_LP64:
58     return CSR_ILP32_LP64_SaveList;
59   case RISCVABI::ABI_ILP32F:
60   case RISCVABI::ABI_LP64F:
61     return CSR_ILP32F_LP64F_SaveList;
62   case RISCVABI::ABI_ILP32D:
63   case RISCVABI::ABI_LP64D:
64     return CSR_ILP32D_LP64D_SaveList;
65   }
66 }
67 
68 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
69   const RISCVFrameLowering *TFI = getFrameLowering(MF);
70   BitVector Reserved(getNumRegs());
71 
72   // Mark any registers requested to be reserved as such
73   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
74     if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
75       markSuperRegs(Reserved, Reg);
76   }
77 
78   // Use markSuperRegs to ensure any register aliases are also reserved
79   markSuperRegs(Reserved, RISCV::X0); // zero
80   markSuperRegs(Reserved, RISCV::X2); // sp
81   markSuperRegs(Reserved, RISCV::X3); // gp
82   markSuperRegs(Reserved, RISCV::X4); // tp
83   if (TFI->hasFP(MF))
84     markSuperRegs(Reserved, RISCV::X8); // fp
85   // Reserve the base register if we need to realign the stack and allocate
86   // variable-sized objects at runtime.
87   if (TFI->hasBP(MF))
88     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
89   assert(checkAllSuperRegsMarked(Reserved));
90   return Reserved;
91 }
92 
93 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
94                                          unsigned PhysReg) const {
95   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
96 }
97 
98 bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
99   return PhysReg == RISCV::X0;
100 }
101 
102 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
103   return CSR_NoRegs_RegMask;
104 }
105 
106 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
107                                             int SPAdj, unsigned FIOperandNum,
108                                             RegScavenger *RS) const {
109   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
110 
111   MachineInstr &MI = *II;
112   MachineFunction &MF = *MI.getParent()->getParent();
113   MachineRegisterInfo &MRI = MF.getRegInfo();
114   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
115   DebugLoc DL = MI.getDebugLoc();
116 
117   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
118   unsigned FrameReg;
119   int Offset =
120       getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
121       MI.getOperand(FIOperandNum + 1).getImm();
122 
123   if (!isInt<32>(Offset)) {
124     report_fatal_error(
125         "Frame offsets outside of the signed 32-bit range not supported");
126   }
127 
128   MachineBasicBlock &MBB = *MI.getParent();
129   bool FrameRegIsKill = false;
130 
131   if (!isInt<12>(Offset)) {
132     assert(isInt<32>(Offset) && "Int32 expected");
133     // The offset won't fit in an immediate, so use a scratch register instead
134     // Modify Offset and FrameReg appropriately
135     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
136     TII->movImm(MBB, II, DL, ScratchReg, Offset);
137     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
138         .addReg(FrameReg)
139         .addReg(ScratchReg, RegState::Kill);
140     Offset = 0;
141     FrameReg = ScratchReg;
142     FrameRegIsKill = true;
143   }
144 
145   MI.getOperand(FIOperandNum)
146       .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
147   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
148 }
149 
150 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
151   const TargetFrameLowering *TFI = getFrameLowering(MF);
152   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
153 }
154 
155 const uint32_t *
156 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
157                                         CallingConv::ID /*CC*/) const {
158   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
159 
160   switch (Subtarget.getTargetABI()) {
161   default:
162     llvm_unreachable("Unrecognized ABI");
163   case RISCVABI::ABI_ILP32:
164   case RISCVABI::ABI_LP64:
165     return CSR_ILP32_LP64_RegMask;
166   case RISCVABI::ABI_ILP32F:
167   case RISCVABI::ABI_LP64F:
168     return CSR_ILP32F_LP64F_RegMask;
169   case RISCVABI::ABI_ILP32D:
170   case RISCVABI::ABI_LP64D:
171     return CSR_ILP32D_LP64D_RegMask;
172   }
173 }
174