1 //===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 15 16 #include "llvm/CodeGen/TargetRegisterInfo.h" 17 18 #define GET_REGINFO_HEADER 19 #include "RISCVGenRegisterInfo.inc" 20 21 namespace llvm { 22 23 struct RISCVRegisterInfo : public RISCVGenRegisterInfo { 24 25 RISCVRegisterInfo(unsigned HwMode); 26 27 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 28 CallingConv::ID) const override; 29 30 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 31 32 BitVector getReservedRegs(const MachineFunction &MF) const override; 33 bool isAsmClobberable(const MachineFunction &MF, 34 MCRegister PhysReg) const override; 35 36 const uint32_t *getNoPreservedMask() const override; 37 38 bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, 39 int &FrameIdx) const override; 40 41 // Update DestReg to have the value SrcReg plus an offset. This is 42 // used during frame layout, and we may need to ensure that if we 43 // split the offset internally that the DestReg is always aligned, 44 // assuming that source reg was. 45 void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, 46 const DebugLoc &DL, Register DestReg, Register SrcReg, 47 StackOffset Offset, MachineInstr::MIFlag Flag, 48 MaybeAlign RequiredAlign) const; 49 50 bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 51 unsigned FIOperandNum, 52 RegScavenger *RS = nullptr) const override; 53 54 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; 55 56 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 57 58 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, 59 int64_t Offset) const override; 60 61 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, 62 int64_t Offset) const override; 63 64 void resolveFrameIndex(MachineInstr &MI, Register BaseReg, 65 int64_t Offset) const override; 66 67 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 68 int Idx) const override; 69 70 void lowerVSPILL(MachineBasicBlock::iterator II) const; 71 void lowerVRELOAD(MachineBasicBlock::iterator II) const; 72 73 Register getFrameRegister(const MachineFunction &MF) const override; 74 75 bool requiresRegisterScavenging(const MachineFunction &MF) const override { 76 return true; 77 } 78 79 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 80 return true; 81 } 82 83 const TargetRegisterClass * 84 getPointerRegClass(const MachineFunction &MF, 85 unsigned Kind = 0) const override { 86 return &RISCV::GPRRegClass; 87 } 88 89 const TargetRegisterClass * 90 getLargestLegalSuperClass(const TargetRegisterClass *RC, 91 const MachineFunction &) const override; 92 93 void getOffsetOpcodes(const StackOffset &Offset, 94 SmallVectorImpl<uint64_t> &Ops) const override; 95 96 unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override; 97 98 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order, 99 SmallVectorImpl<MCPhysReg> &Hints, 100 const MachineFunction &MF, const VirtRegMap *VRM, 101 const LiveRegMatrix *Matrix) const override; 102 }; 103 } 104 105 #endif 106