1//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the RISC-V register files 11//===----------------------------------------------------------------------===// 12 13let Namespace = "RISCV" in { 14class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 15 let HWEncoding{4-0} = Enc; 16 let AltNames = alt; 17} 18 19class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs, 20 list<string> alt = []> 21 : RegisterWithSubRegs<n, subregs> { 22 let HWEncoding{4-0} = Enc; 23 let AltNames = alt; 24} 25 26class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 27 let HWEncoding{4-0} = Enc; 28 let AltNames = alt; 29} 30 31def sub_16 : SubRegIndex<16>; 32class RISCVReg32<RISCVReg16 subreg> 33 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg], 34 subreg.AltNames> { 35 let SubRegIndices = [sub_16]; 36} 37 38// Because RISCVReg64 register have AsmName and AltNames that alias with their 39// 16/32-bit sub-register, RISCVAsmParser will need to coerce a register number 40// from a RISCVReg16/RISCVReg32 to the equivalent RISCVReg64 when appropriate. 41def sub_32 : SubRegIndex<32>; 42class RISCVReg64<RISCVReg32 subreg> 43 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg], 44 subreg.AltNames> { 45 let SubRegIndices = [sub_32]; 46} 47 48let FallbackRegAltNameIndex = NoRegAltName in 49def ABIRegAltName : RegAltNameIndex; 50 51def sub_vrm4_0 : SubRegIndex<256>; 52def sub_vrm4_1 : SubRegIndex<256, 256>; 53def sub_vrm2_0 : SubRegIndex<128>; 54def sub_vrm2_1 : SubRegIndex<128, 128>; 55def sub_vrm2_2 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_0>; 56def sub_vrm2_3 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_1>; 57def sub_vrm1_0 : SubRegIndex<64>; 58def sub_vrm1_1 : SubRegIndex<64, 64>; 59def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>; 60def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>; 61def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>; 62def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>; 63def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>; 64def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>; 65 66def sub_32_hi : SubRegIndex<32, 32>; 67} // Namespace = "RISCV" 68 69// Integer registers 70// CostPerUse is set higher for registers that may not be compressible as they 71// are not part of GPRC, the most restrictive register class used by the 72// compressed instruction set. This will influence the greedy register 73// allocator to reduce the use of registers that can't be encoded in 16 bit 74// instructions. 75 76let RegAltNameIndices = [ABIRegAltName] in { 77 let isConstant = true in 78 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; 79 let CostPerUse = [0, 1] in { 80 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; 81 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; 82 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; 83 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; 84 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; 85 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; 86 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; 87 } 88 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; 89 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; 90 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; 91 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; 92 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; 93 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; 94 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; 95 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; 96 let CostPerUse = [0, 1] in { 97 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; 98 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; 99 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; 100 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; 101 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; 102 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; 103 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; 104 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; 105 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>; 106 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>; 107 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>; 108 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>; 109 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>; 110 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; 111 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; 112 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; 113 } 114} 115 116def XLenVT : ValueTypeByHwMode<[RV32, RV64], 117 [i32, i64]>; 118// Allow f64 in GPR for ZDINX on RV64. 119def XLenFVT : ValueTypeByHwMode<[RV64], 120 [f64]>; 121def XLenRI : RegInfoByHwMode< 122 [RV32, RV64], 123 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 124 125class GPRRegisterClass<dag regList> 126 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, regList> { 127 let RegInfos = XLenRI; 128} 129 130// The order of registers represents the preferred allocation sequence. 131// Registers are listed in the order caller-save, callee-save, specials. 132def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17), 133 (sequence "X%u", 5, 7), 134 (sequence "X%u", 28, 31), 135 (sequence "X%u", 8, 9), 136 (sequence "X%u", 18, 27), 137 (sequence "X%u", 0, 4))>; 138 139def GPRX0 : GPRRegisterClass<(add X0)>; 140 141def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>; 142 143def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)>; 144 145// Don't use X1 or X5 for JALR since that is a hint to pop the return address 146// stack on some microarchitectures. Also remove the reserved registers X0, X2, 147// X3, and X4 as it reduces the number of register classes that get synthesized 148// by tablegen. 149def GPRJALR : GPRRegisterClass<(sub GPR, (sequence "X%u", 0, 5))>; 150 151def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15), 152 (sequence "X%u", 8, 9))>; 153 154// For indirect tail calls, we can't use callee-saved registers, as they are 155// restored to the saved value before the tail call, which would clobber a call 156// address. We shouldn't use x5 since that is a hint for to pop the return 157// address stack on some microarchitectures. 158def GPRTC : GPRRegisterClass<(add (sequence "X%u", 6, 7), 159 (sequence "X%u", 10, 17), 160 (sequence "X%u", 28, 31))>; 161 162def SP : GPRRegisterClass<(add X2)>; 163 164// Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension 165def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9), 166 (sequence "X%u", 18, 23))>; 167 168// Registers saveable by PUSH/POP instruction in Zcmp extension 169def PGPR : RegisterClass<"RISCV", [XLenVT], 32, (add 170 (sequence "X%u", 8, 9), 171 (sequence "X%u", 18, 27), 172 X1 173 )> { 174 let RegInfos = XLenRI; 175} 176 177// Floating point registers 178let RegAltNameIndices = [ABIRegAltName] in { 179 def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; 180 def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; 181 def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; 182 def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; 183 def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; 184 def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; 185 def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; 186 def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; 187 def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; 188 def F9_H : RISCVReg16<9, "f9", ["fs1"]>, DwarfRegNum<[41]>; 189 def F10_H : RISCVReg16<10,"f10", ["fa0"]>, DwarfRegNum<[42]>; 190 def F11_H : RISCVReg16<11,"f11", ["fa1"]>, DwarfRegNum<[43]>; 191 def F12_H : RISCVReg16<12,"f12", ["fa2"]>, DwarfRegNum<[44]>; 192 def F13_H : RISCVReg16<13,"f13", ["fa3"]>, DwarfRegNum<[45]>; 193 def F14_H : RISCVReg16<14,"f14", ["fa4"]>, DwarfRegNum<[46]>; 194 def F15_H : RISCVReg16<15,"f15", ["fa5"]>, DwarfRegNum<[47]>; 195 def F16_H : RISCVReg16<16,"f16", ["fa6"]>, DwarfRegNum<[48]>; 196 def F17_H : RISCVReg16<17,"f17", ["fa7"]>, DwarfRegNum<[49]>; 197 def F18_H : RISCVReg16<18,"f18", ["fs2"]>, DwarfRegNum<[50]>; 198 def F19_H : RISCVReg16<19,"f19", ["fs3"]>, DwarfRegNum<[51]>; 199 def F20_H : RISCVReg16<20,"f20", ["fs4"]>, DwarfRegNum<[52]>; 200 def F21_H : RISCVReg16<21,"f21", ["fs5"]>, DwarfRegNum<[53]>; 201 def F22_H : RISCVReg16<22,"f22", ["fs6"]>, DwarfRegNum<[54]>; 202 def F23_H : RISCVReg16<23,"f23", ["fs7"]>, DwarfRegNum<[55]>; 203 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>; 204 def F25_H : RISCVReg16<25,"f25", ["fs9"]>, DwarfRegNum<[57]>; 205 def F26_H : RISCVReg16<26,"f26", ["fs10"]>, DwarfRegNum<[58]>; 206 def F27_H : RISCVReg16<27,"f27", ["fs11"]>, DwarfRegNum<[59]>; 207 def F28_H : RISCVReg16<28,"f28", ["ft8"]>, DwarfRegNum<[60]>; 208 def F29_H : RISCVReg16<29,"f29", ["ft9"]>, DwarfRegNum<[61]>; 209 def F30_H : RISCVReg16<30,"f30", ["ft10"]>, DwarfRegNum<[62]>; 210 def F31_H : RISCVReg16<31,"f31", ["ft11"]>, DwarfRegNum<[63]>; 211 212 foreach Index = 0-31 in { 213 def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>, 214 DwarfRegNum<[!add(Index, 32)]>; 215 } 216 217 foreach Index = 0-31 in { 218 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>, 219 DwarfRegNum<[!add(Index, 32)]>; 220 } 221} 222 223// The order of registers represents the preferred allocation sequence, 224// meaning caller-save regs are listed before callee-save. 225// We start by allocating argument registers in reverse order since they are 226// compressible. 227def FPR16 : RegisterClass<"RISCV", [f16, bf16], 16, (add 228 (sequence "F%u_H", 15, 10), // fa5-fa0 229 (sequence "F%u_H", 0, 7), // ft0-f7 230 (sequence "F%u_H", 16, 17), // fa6-fa7 231 (sequence "F%u_H", 28, 31), // ft8-ft11 232 (sequence "F%u_H", 8, 9), // fs0-fs1 233 (sequence "F%u_H", 18, 27) // fs2-fs11 234)>; 235 236def FPR32 : RegisterClass<"RISCV", [f32], 32, (add 237 (sequence "F%u_F", 15, 10), 238 (sequence "F%u_F", 0, 7), 239 (sequence "F%u_F", 16, 17), 240 (sequence "F%u_F", 28, 31), 241 (sequence "F%u_F", 8, 9), 242 (sequence "F%u_F", 18, 27) 243)>; 244 245def FPR32C : RegisterClass<"RISCV", [f32], 32, (add 246 (sequence "F%u_F", 15, 10), 247 (sequence "F%u_F", 8, 9) 248)>; 249 250// The order of registers represents the preferred allocation sequence, 251// meaning caller-save regs are listed before callee-save. 252def FPR64 : RegisterClass<"RISCV", [f64], 64, (add 253 (sequence "F%u_D", 15, 10), 254 (sequence "F%u_D", 0, 7), 255 (sequence "F%u_D", 16, 17), 256 (sequence "F%u_D", 28, 31), 257 (sequence "F%u_D", 8, 9), 258 (sequence "F%u_D", 18, 27) 259)>; 260 261def FPR64C : RegisterClass<"RISCV", [f64], 64, (add 262 (sequence "F%u_D", 15, 10), 263 (sequence "F%u_D", 8, 9) 264)>; 265 266// Vector type mapping to LLVM types. 267// 268// The V vector extension requires that VLEN >= 128 and <= 65536. 269// Additionally, the only supported ELEN values are 32 and 64, 270// thus `vscale` can be defined as VLEN/64, 271// allowing the same types with either ELEN value. 272// 273// MF8 MF4 MF2 M1 M2 M4 M8 274// i64* N/A N/A N/A nxv1i64 nxv2i64 nxv4i64 nxv8i64 275// i32 N/A N/A nxv1i32 nxv2i32 nxv4i32 nxv8i32 nxv16i32 276// i16 N/A nxv1i16 nxv2i16 nxv4i16 nxv8i16 nxv16i16 nxv32i16 277// i8 nxv1i8 nxv2i8 nxv4i8 nxv8i8 nxv16i8 nxv32i8 nxv64i8 278// double* N/A N/A N/A nxv1f64 nxv2f64 nxv4f64 nxv8f64 279// float N/A N/A nxv1f32 nxv2f32 nxv4f32 nxv8f32 nxv16f32 280// half N/A nxv1f16 nxv2f16 nxv4f16 nxv8f16 nxv16f16 nxv32f16 281// * ELEN=64 282 283defvar vint8mf8_t = nxv1i8; 284defvar vint8mf4_t = nxv2i8; 285defvar vint8mf2_t = nxv4i8; 286defvar vint8m1_t = nxv8i8; 287defvar vint8m2_t = nxv16i8; 288defvar vint8m4_t = nxv32i8; 289defvar vint8m8_t = nxv64i8; 290 291defvar vint16mf4_t = nxv1i16; 292defvar vint16mf2_t = nxv2i16; 293defvar vint16m1_t = nxv4i16; 294defvar vint16m2_t = nxv8i16; 295defvar vint16m4_t = nxv16i16; 296defvar vint16m8_t = nxv32i16; 297 298defvar vint32mf2_t = nxv1i32; 299defvar vint32m1_t = nxv2i32; 300defvar vint32m2_t = nxv4i32; 301defvar vint32m4_t = nxv8i32; 302defvar vint32m8_t = nxv16i32; 303 304defvar vint64m1_t = nxv1i64; 305defvar vint64m2_t = nxv2i64; 306defvar vint64m4_t = nxv4i64; 307defvar vint64m8_t = nxv8i64; 308 309defvar vfloat16mf4_t = nxv1f16; 310defvar vfloat16mf2_t = nxv2f16; 311defvar vfloat16m1_t = nxv4f16; 312defvar vfloat16m2_t = nxv8f16; 313defvar vfloat16m4_t = nxv16f16; 314defvar vfloat16m8_t = nxv32f16; 315 316defvar vfloat32mf2_t = nxv1f32; 317defvar vfloat32m1_t = nxv2f32; 318defvar vfloat32m2_t = nxv4f32; 319defvar vfloat32m4_t = nxv8f32; 320defvar vfloat32m8_t = nxv16f32; 321 322defvar vfloat64m1_t = nxv1f64; 323defvar vfloat64m2_t = nxv2f64; 324defvar vfloat64m4_t = nxv4f64; 325defvar vfloat64m8_t = nxv8f64; 326 327defvar vbool1_t = nxv64i1; 328defvar vbool2_t = nxv32i1; 329defvar vbool4_t = nxv16i1; 330defvar vbool8_t = nxv8i1; 331defvar vbool16_t = nxv4i1; 332defvar vbool32_t = nxv2i1; 333defvar vbool64_t = nxv1i1; 334 335// There is no need to define register classes for fractional LMUL. 336defvar LMULList = [1, 2, 4, 8]; 337 338//===----------------------------------------------------------------------===// 339// Utility classes for segment load/store. 340//===----------------------------------------------------------------------===// 341// The set of legal NF for LMUL = lmul. 342// LMUL == 1, NF = 2, 3, 4, 5, 6, 7, 8 343// LMUL == 2, NF = 2, 3, 4 344// LMUL == 4, NF = 2 345class NFList<int lmul> { 346 list<int> L = !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8], 347 !eq(lmul, 2): [2, 3, 4], 348 !eq(lmul, 4): [2], 349 !eq(lmul, 8): []); 350} 351 352// Generate [start, end) SubRegIndex list. 353class SubRegSet<int nf, int lmul> { 354 list<SubRegIndex> L = !foldl([]<SubRegIndex>, 355 [0, 1, 2, 3, 4, 5, 6, 7], 356 AccList, i, 357 !listconcat(AccList, 358 !if(!lt(i, nf), 359 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)], 360 []))); 361} 362 363// Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX. 364// When NF = 2, the valid TUPLE_INDEX is 0 and 1. 365// For example, when LMUL = 4, the potential valid indexes is 366// [8, 12, 16, 20, 24, 28, 4]. However, not all these indexes are valid under 367// NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0. 368// The filter is 369// (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul) 370// 371// Use START = 0, LMUL = 4 and NF = 2 as the example, 372// i x 4 <= 24 373// The class will return [8, 12, 16, 20, 24, 4]. 374// Use START = 1, LMUL = 4 and NF = 2 as the example, 375// (1 + i) x 4 <= 28 376// The class will return [12, 16, 20, 24, 28, 8]. 377// 378class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> { 379 list<int> R = 380 !foldl([]<int>, 381 !if(isV0, [0], 382 !cond( 383 !eq(lmul, 1): 384 [8, 9, 10, 11, 12, 13, 14, 15, 385 16, 17, 18, 19, 20, 21, 22, 23, 386 24, 25, 26, 27, 28, 29, 30, 31, 387 1, 2, 3, 4, 5, 6, 7], 388 !eq(lmul, 2): 389 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 1, 2, 3], 390 !eq(lmul, 4): 391 [2, 3, 4, 5, 6, 7, 1])), 392 L, i, 393 !listconcat(L, 394 !if(!le(!mul(!add(i, tuple_index), lmul), 395 !sub(!add(32, !mul(tuple_index, lmul)), !mul(nf, lmul))), 396 [!mul(!add(i, tuple_index), lmul)], []))); 397} 398 399// This class returns a list of vector register collections. 400// For example, for NF = 2 and LMUL = 4, 401// it will return 402// ([ V8M4, V12M4, V16M4, V20M4, V24M4, V4M4], 403// [V12M4, V16M4, V20M4, V24M4, V28M4, V8M4]) 404// 405class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> { 406 list<dag> L = 407 !if(!ge(start, nf), 408 LIn, 409 !listconcat( 410 [!dag(add, 411 !foreach(i, IndexSet<start, nf, lmul, isV0>.R, 412 !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2", 413 !eq(lmul, 4): "M4", 414 true: ""))), 415 !listsplat("", 416 !size(IndexSet<start, nf, lmul, isV0>.R)))], 417 VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L)); 418} 419 420// Vector registers 421foreach Index = 0-31 in { 422 def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>; 423} 424 425foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 426 24, 26, 28, 30] in { 427 def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index, 428 [!cast<Register>("V"#Index), 429 !cast<Register>("V"#!add(Index, 1))]>, 430 DwarfRegAlias<!cast<Register>("V"#Index)> { 431 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1]; 432 } 433} 434 435foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in { 436 def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index, 437 [!cast<Register>("V"#Index#"M2"), 438 !cast<Register>("V"#!add(Index, 2)#"M2")]>, 439 DwarfRegAlias<!cast<Register>("V"#Index)> { 440 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1]; 441 } 442} 443 444foreach Index = [0, 8, 16, 24] in { 445 def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index, 446 [!cast<Register>("V"#Index#"M4"), 447 !cast<Register>("V"#!add(Index, 4)#"M4")]>, 448 DwarfRegAlias<!cast<Register>("V"#Index)> { 449 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1]; 450 } 451} 452 453def VTYPE : RISCVReg<0, "vtype">; 454def VL : RISCVReg<0, "vl">; 455def VXSAT : RISCVReg<0, "vxsat">; 456def VXRM : RISCVReg<0, "vxrm">; 457let isConstant = true in 458def VLENB : RISCVReg<0, "vlenb">, 459 DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>; 460 461def VCSR : RegisterClass<"RISCV", [XLenVT], 32, 462 (add VTYPE, VL, VLENB)> { 463 let RegInfos = XLenRI; 464} 465 466 467foreach m = [1, 2, 4] in { 468 foreach n = NFList<m>.L in { 469 def "VN" # n # "M" # m # "NoV0": RegisterTuples< 470 SubRegSet<n, m>.L, 471 VRegList<[], 0, n, m, false>.L>; 472 def "VN" # n # "M" # m # "V0" : RegisterTuples< 473 SubRegSet<n, m>.L, 474 VRegList<[], 0, n, m, true>.L>; 475 } 476} 477 478class VReg<list<ValueType> regTypes, dag regList, int Vlmul> 479 : RegisterClass<"RISCV", 480 regTypes, 481 64, // The maximum supported ELEN is 64. 482 regList> { 483 int VLMul = Vlmul; 484 int Size = !mul(Vlmul, 64); 485} 486 487defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, 488 vbool32_t, vbool64_t]; 489 490defvar VM1VTs = [vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, 491 vfloat16m1_t, vfloat32m1_t, vfloat64m1_t, 492 vint8mf2_t, vint8mf4_t, vint8mf8_t, 493 vint16mf2_t, vint16mf4_t, vint32mf2_t, 494 vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t]; 495 496defvar VM2VTs = [vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, 497 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t]; 498 499defvar VM4VTs = [vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, 500 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t]; 501 502defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, 503 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t]; 504 505def VR : VReg<!listconcat(VM1VTs, VMaskVTs), 506 (add (sequence "V%u", 8, 31), 507 (sequence "V%u", 0, 7)), 1>; 508 509def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), 510 (add (sequence "V%u", 8, 31), 511 (sequence "V%u", 1, 7)), 1>; 512 513def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), 514 (sequence "V%uM2", 0, 7, 2)), 2>; 515 516def VRM2NoV0 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), 517 (sequence "V%uM2", 2, 7, 2)), 2>; 518 519def VRM4 : VReg<VM4VTs, 520 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>; 521 522def VRM4NoV0 : VReg<VM4VTs, 523 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>; 524 525def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>; 526 527def VRM8NoV0 : VReg<VM8VTs, (add V8M8, V16M8, V24M8), 8>; 528 529def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { 530 let Size = 64; 531} 532 533let RegInfos = XLenRI in { 534def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>; 535def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>; 536} // RegInfos = XLenRI 537 538// Dummy zero register for use in the register pair containing X0 (as X1 is 539// not read to or written when the X0 register pair is used). 540def DUMMY_REG_PAIR_WITH_X0 : RISCVReg<0, "0">; 541 542// Must add DUMMY_REG_PAIR_WITH_X0 to a separate register class to prevent the 543// register's existence from changing codegen (due to the regPressureSetLimit 544// for the GPR register class being altered). 545def GPRAll : GPRRegisterClass<(add GPR, DUMMY_REG_PAIR_WITH_X0)>; 546 547let RegAltNameIndices = [ABIRegAltName] in { 548 def X0_PD : RISCVRegWithSubRegs<0, X0.AsmName, 549 [X0, DUMMY_REG_PAIR_WITH_X0], 550 X0.AltNames> { 551 let SubRegIndices = [sub_32, sub_32_hi]; 552 let CoveredBySubRegs = 1; 553 } 554 foreach I = 1-15 in { 555 defvar Index = !shl(I, 1); 556 defvar Reg = !cast<Register>("X"#Index); 557 defvar RegP1 = !cast<Register>("X"#!add(Index,1)); 558 def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName, 559 [Reg, RegP1], 560 Reg.AltNames> { 561 let SubRegIndices = [sub_32, sub_32_hi]; 562 let CoveredBySubRegs = 1; 563 } 564 } 565} 566 567let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in 568def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add 569 X10_PD, X12_PD, X14_PD, X16_PD, 570 X6_PD, 571 X28_PD, X30_PD, 572 X8_PD, 573 X18_PD, X20_PD, X22_PD, X24_PD, X26_PD, 574 X0_PD, X2_PD, X4_PD 575)>; 576 577// The register class is added for inline assembly for vector mask types. 578def VM : VReg<VMaskVTs, 579 (add (sequence "V%u", 8, 31), 580 (sequence "V%u", 0, 7)), 1>; 581 582foreach m = LMULList in { 583 foreach nf = NFList<m>.L in { 584 def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped], 585 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")), 586 !mul(nf, m)>; 587 def "VRN" # nf # "M" # m: VReg<[untyped], 588 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"), 589 !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")), 590 !mul(nf, m)>; 591 } 592} 593 594// Special registers 595def FFLAGS : RISCVReg<0, "fflags">; 596def FRM : RISCVReg<0, "frm">; 597