1//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the RISC-V register files 11//===----------------------------------------------------------------------===// 12 13let Namespace = "RISCV" in { 14class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 15 let HWEncoding{4-0} = Enc; 16 let AltNames = alt; 17} 18 19class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 20 let HWEncoding{4-0} = Enc; 21 let AltNames = alt; 22} 23 24def sub_16 : SubRegIndex<16>; 25class RISCVReg32<RISCVReg16 subreg> : Register<""> { 26 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 27 let SubRegs = [subreg]; 28 let SubRegIndices = [sub_16]; 29 let AsmName = subreg.AsmName; 30 let AltNames = subreg.AltNames; 31} 32 33// Because RISCVReg64 register have AsmName and AltNames that alias with their 34// 16/32-bit sub-register, RISCVAsmParser will need to coerce a register number 35// from a RISCVReg16/RISCVReg32 to the equivalent RISCVReg64 when appropriate. 36def sub_32 : SubRegIndex<32>; 37class RISCVReg64<RISCVReg32 subreg> : Register<""> { 38 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 39 let SubRegs = [subreg]; 40 let SubRegIndices = [sub_32]; 41 let AsmName = subreg.AsmName; 42 let AltNames = subreg.AltNames; 43} 44 45class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs, 46 list<string> alt = []> 47 : RegisterWithSubRegs<n, subregs> { 48 let HWEncoding{4-0} = Enc; 49 let AltNames = alt; 50} 51 52def ABIRegAltName : RegAltNameIndex; 53 54def sub_vrm1_0 : SubRegIndex<64, -1>; 55def sub_vrm1_1 : SubRegIndex<64, -1>; 56def sub_vrm1_2 : SubRegIndex<64, -1>; 57def sub_vrm1_3 : SubRegIndex<64, -1>; 58def sub_vrm1_4 : SubRegIndex<64, -1>; 59def sub_vrm1_5 : SubRegIndex<64, -1>; 60def sub_vrm1_6 : SubRegIndex<64, -1>; 61def sub_vrm1_7 : SubRegIndex<64, -1>; 62def sub_vrm2_0 : SubRegIndex<128, -1>; 63def sub_vrm2_1 : SubRegIndex<128, -1>; 64def sub_vrm2_2 : SubRegIndex<128, -1>; 65def sub_vrm2_3 : SubRegIndex<128, -1>; 66def sub_vrm4_0 : SubRegIndex<256, -1>; 67def sub_vrm4_1 : SubRegIndex<256, -1>; 68 69} // Namespace = "RISCV" 70 71// Integer registers 72// CostPerUse is set higher for registers that may not be compressible as they 73// are not part of GPRC, the most restrictive register class used by the 74// compressed instruction set. This will influence the greedy register 75// allocator to reduce the use of registers that can't be encoded in 16 bit 76// instructions. This affects register allocation even when compressed 77// instruction isn't targeted, we see no major negative codegen impact. 78 79let RegAltNameIndices = [ABIRegAltName] in { 80 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; 81 let CostPerUse = 1 in { 82 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; 83 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; 84 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; 85 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; 86 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; 87 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; 88 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; 89 } 90 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; 91 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; 92 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; 93 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; 94 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; 95 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; 96 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; 97 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; 98 let CostPerUse = 1 in { 99 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; 100 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; 101 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; 102 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; 103 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; 104 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; 105 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; 106 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; 107 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>; 108 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>; 109 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>; 110 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>; 111 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>; 112 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; 113 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; 114 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; 115 } 116} 117 118def XLenVT : ValueTypeByHwMode<[RV32, RV64], 119 [i32, i64]>; 120 121// The order of registers represents the preferred allocation sequence. 122// Registers are listed in the order caller-save, callee-save, specials. 123def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add 124 (sequence "X%u", 10, 17), 125 (sequence "X%u", 5, 7), 126 (sequence "X%u", 28, 31), 127 (sequence "X%u", 8, 9), 128 (sequence "X%u", 18, 27), 129 (sequence "X%u", 0, 4) 130 )> { 131 let RegInfos = RegInfoByHwMode< 132 [RV32, RV64], 133 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 134} 135 136def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> { 137 let RegInfos = RegInfoByHwMode< 138 [RV32, RV64], 139 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 140} 141 142// The order of registers represents the preferred allocation sequence. 143// Registers are listed in the order caller-save, callee-save, specials. 144def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add 145 (sequence "X%u", 10, 17), 146 (sequence "X%u", 5, 7), 147 (sequence "X%u", 28, 31), 148 (sequence "X%u", 8, 9), 149 (sequence "X%u", 18, 27), 150 (sequence "X%u", 1, 4) 151 )> { 152 let RegInfos = RegInfoByHwMode< 153 [RV32, RV64], 154 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 155} 156 157def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add 158 (sequence "X%u", 10, 17), 159 (sequence "X%u", 5, 7), 160 (sequence "X%u", 28, 31), 161 (sequence "X%u", 8, 9), 162 (sequence "X%u", 18, 27), 163 X1, X3, X4 164 )> { 165 let RegInfos = RegInfoByHwMode< 166 [RV32, RV64], 167 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 168} 169 170def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add 171 (sequence "X%u", 10, 15), 172 (sequence "X%u", 8, 9) 173 )> { 174 let RegInfos = RegInfoByHwMode< 175 [RV32, RV64], 176 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 177} 178 179// For indirect tail calls, we can't use callee-saved registers, as they are 180// restored to the saved value before the tail call, which would clobber a call 181// address. 182def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add 183 (sequence "X%u", 5, 7), 184 (sequence "X%u", 10, 17), 185 (sequence "X%u", 28, 31) 186 )> { 187 let RegInfos = RegInfoByHwMode< 188 [RV32, RV64], 189 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 190} 191 192def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { 193 let RegInfos = RegInfoByHwMode< 194 [RV32, RV64], 195 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 196} 197 198// Floating point registers 199let RegAltNameIndices = [ABIRegAltName] in { 200 def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; 201 def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; 202 def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; 203 def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; 204 def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; 205 def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; 206 def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; 207 def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; 208 def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; 209 def F9_H : RISCVReg16<9, "f9", ["fs1"]>, DwarfRegNum<[41]>; 210 def F10_H : RISCVReg16<10,"f10", ["fa0"]>, DwarfRegNum<[42]>; 211 def F11_H : RISCVReg16<11,"f11", ["fa1"]>, DwarfRegNum<[43]>; 212 def F12_H : RISCVReg16<12,"f12", ["fa2"]>, DwarfRegNum<[44]>; 213 def F13_H : RISCVReg16<13,"f13", ["fa3"]>, DwarfRegNum<[45]>; 214 def F14_H : RISCVReg16<14,"f14", ["fa4"]>, DwarfRegNum<[46]>; 215 def F15_H : RISCVReg16<15,"f15", ["fa5"]>, DwarfRegNum<[47]>; 216 def F16_H : RISCVReg16<16,"f16", ["fa6"]>, DwarfRegNum<[48]>; 217 def F17_H : RISCVReg16<17,"f17", ["fa7"]>, DwarfRegNum<[49]>; 218 def F18_H : RISCVReg16<18,"f18", ["fs2"]>, DwarfRegNum<[50]>; 219 def F19_H : RISCVReg16<19,"f19", ["fs3"]>, DwarfRegNum<[51]>; 220 def F20_H : RISCVReg16<20,"f20", ["fs4"]>, DwarfRegNum<[52]>; 221 def F21_H : RISCVReg16<21,"f21", ["fs5"]>, DwarfRegNum<[53]>; 222 def F22_H : RISCVReg16<22,"f22", ["fs6"]>, DwarfRegNum<[54]>; 223 def F23_H : RISCVReg16<23,"f23", ["fs7"]>, DwarfRegNum<[55]>; 224 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>; 225 def F25_H : RISCVReg16<25,"f25", ["fs9"]>, DwarfRegNum<[57]>; 226 def F26_H : RISCVReg16<26,"f26", ["fs10"]>, DwarfRegNum<[58]>; 227 def F27_H : RISCVReg16<27,"f27", ["fs11"]>, DwarfRegNum<[59]>; 228 def F28_H : RISCVReg16<28,"f28", ["ft8"]>, DwarfRegNum<[60]>; 229 def F29_H : RISCVReg16<29,"f29", ["ft9"]>, DwarfRegNum<[61]>; 230 def F30_H : RISCVReg16<30,"f30", ["ft10"]>, DwarfRegNum<[62]>; 231 def F31_H : RISCVReg16<31,"f31", ["ft11"]>, DwarfRegNum<[63]>; 232 233 foreach Index = 0-31 in { 234 def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>, 235 DwarfRegNum<[!add(Index, 32)]>; 236 } 237 238 foreach Index = 0-31 in { 239 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>, 240 DwarfRegNum<[!add(Index, 32)]>; 241 } 242} 243 244// The order of registers represents the preferred allocation sequence, 245// meaning caller-save regs are listed before callee-save. 246def FPR16 : RegisterClass<"RISCV", [f16], 16, (add 247 (sequence "F%u_H", 0, 7), 248 (sequence "F%u_H", 10, 17), 249 (sequence "F%u_H", 28, 31), 250 (sequence "F%u_H", 8, 9), 251 (sequence "F%u_H", 18, 27) 252)>; 253 254def FPR32 : RegisterClass<"RISCV", [f32], 32, (add 255 (sequence "F%u_F", 0, 7), 256 (sequence "F%u_F", 10, 17), 257 (sequence "F%u_F", 28, 31), 258 (sequence "F%u_F", 8, 9), 259 (sequence "F%u_F", 18, 27) 260)>; 261 262def FPR32C : RegisterClass<"RISCV", [f32], 32, (add 263 (sequence "F%u_F", 10, 15), 264 (sequence "F%u_F", 8, 9) 265)>; 266 267// The order of registers represents the preferred allocation sequence, 268// meaning caller-save regs are listed before callee-save. 269def FPR64 : RegisterClass<"RISCV", [f64], 64, (add 270 (sequence "F%u_D", 0, 7), 271 (sequence "F%u_D", 10, 17), 272 (sequence "F%u_D", 28, 31), 273 (sequence "F%u_D", 8, 9), 274 (sequence "F%u_D", 18, 27) 275)>; 276 277def FPR64C : RegisterClass<"RISCV", [f64], 64, (add 278 (sequence "F%u_D", 10, 15), 279 (sequence "F%u_D", 8, 9) 280)>; 281 282// Vector type mapping to LLVM types. 283// 284// Though the V extension allows that VLEN be as small as 8, 285// this approach assumes that VLEN>=64. 286// Additionally, the only supported ELEN values are 32 and 64, 287// thus `vscale` can be defined as VLEN/64, 288// allowing the same types with either ELEN value. 289// 290// MF8 MF4 MF2 M1 M2 M4 M8 291// i64* N/A N/A N/A nxv1i64 nxv2i64 nxv4i64 nxv8i64 292// i32 N/A N/A nxv1i32 nxv2i32 nxv4i32 nxv8i32 nxv16i32 293// i16 N/A nxv1i16 nxv2i16 nxv4i16 nxv8i16 nxv16i16 nxv32i16 294// i8 nxv1i8 nxv2i8 nxv4i8 nxv8i8 nxv16i8 nxv32i8 nxv64i8 295// double* N/A N/A N/A nxv1f64 nxv2f64 nxv4f64 nxv8f64 296// float N/A N/A nxv1f32 nxv2f32 nxv4f32 nxv8f32 nxv16f32 297// half N/A nxv1f16 nxv2f16 nxv4f16 nxv8f16 nxv16f16 nxv32f16 298// * ELEN=64 299 300defvar vint8mf8_t = nxv1i8; 301defvar vint8mf4_t = nxv2i8; 302defvar vint8mf2_t = nxv4i8; 303defvar vint8m1_t = nxv8i8; 304defvar vint8m2_t = nxv16i8; 305defvar vint8m4_t = nxv32i8; 306defvar vint8m8_t = nxv64i8; 307 308defvar vint16mf4_t = nxv1i16; 309defvar vint16mf2_t = nxv2i16; 310defvar vint16m1_t = nxv4i16; 311defvar vint16m2_t = nxv8i16; 312defvar vint16m4_t = nxv16i16; 313defvar vint16m8_t = nxv32i16; 314 315defvar vint32mf2_t = nxv1i32; 316defvar vint32m1_t = nxv2i32; 317defvar vint32m2_t = nxv4i32; 318defvar vint32m4_t = nxv8i32; 319defvar vint32m8_t = nxv16i32; 320 321defvar vint64m1_t = nxv1i64; 322defvar vint64m2_t = nxv2i64; 323defvar vint64m4_t = nxv4i64; 324defvar vint64m8_t = nxv8i64; 325 326defvar vfloat16mf4_t = nxv1f16; 327defvar vfloat16mf2_t = nxv2f16; 328defvar vfloat16m1_t = nxv4f16; 329defvar vfloat16m2_t = nxv8f16; 330defvar vfloat16m4_t = nxv16f16; 331defvar vfloat16m8_t = nxv32f16; 332 333defvar vfloat32mf2_t = nxv1f32; 334defvar vfloat32m1_t = nxv2f32; 335defvar vfloat32m2_t = nxv4f32; 336defvar vfloat32m4_t = nxv8f32; 337defvar vfloat32m8_t = nxv16f32; 338 339defvar vfloat64m1_t = nxv1f64; 340defvar vfloat64m2_t = nxv2f64; 341defvar vfloat64m4_t = nxv4f64; 342defvar vfloat64m8_t = nxv8f64; 343 344defvar vbool1_t = nxv64i1; 345defvar vbool2_t = nxv32i1; 346defvar vbool4_t = nxv16i1; 347defvar vbool8_t = nxv8i1; 348defvar vbool16_t = nxv4i1; 349defvar vbool32_t = nxv2i1; 350defvar vbool64_t = nxv1i1; 351 352// There is no need to define register classes for fractional LMUL. 353def LMULList { 354 list<int> m = [1, 2, 4, 8]; 355} 356 357//===----------------------------------------------------------------------===// 358// Utility classes for segment load/store. 359//===----------------------------------------------------------------------===// 360// The set of legal NF for LMUL = lmul. 361// LMUL == 1, NF = 2, 3, 4, 5, 6, 7, 8 362// LMUL == 2, NF = 2, 3, 4 363// LMUL == 4, NF = 2 364class NFList<int lmul> { 365 list<int> L = !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8], 366 !eq(lmul, 2): [2, 3, 4], 367 !eq(lmul, 4): [2], 368 !eq(lmul, 8): []); 369} 370 371// Generate [start, end) SubRegIndex list. 372class SubRegSet<list<SubRegIndex> LIn, int start, int nf, int lmul> { 373 list<SubRegIndex> L = !foldl([]<SubRegIndex>, 374 [0, 1, 2, 3, 4, 5, 6, 7], 375 AccList, i, 376 !listconcat(AccList, 377 !if(!lt(i, nf), 378 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)], 379 []))); 380} 381 382class IndexSet<int index, int nf, int lmul> { 383 list<int> R = 384 !foldl([]<int>, 385 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 386 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 387 23, 24, 25, 26, 27, 28, 29, 30, 31], 388 L, i, 389 !listconcat(L, 390 !if(!and( 391 !le(!mul(index, lmul), !mul(i, lmul)), 392 !le(!mul(i, lmul), 393 !sub(!add(32, !mul(index, lmul)), !mul(nf, lmul))) 394 ), [!mul(i, lmul)], []))); 395} 396 397class VRegList<list<dag> LIn, int start, int nf, int lmul> { 398 list<dag> L = 399 !if(!ge(start, nf), 400 LIn, 401 !listconcat( 402 [!dag(add, 403 !foreach(i, IndexSet<start, nf, lmul>.R, 404 !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2", 405 !eq(lmul, 4): "M4", 406 true: ""))), 407 !listsplat("", !size(IndexSet<start, nf, lmul>.R)))], 408 VRegList<LIn, !add(start, 1), nf, lmul>.L)); 409} 410 411// Vector registers 412let RegAltNameIndices = [ABIRegAltName] in { 413 foreach Index = 0-31 in { 414 def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 96)]>; 415 } 416 417 foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 418 24, 26, 28, 30] in { 419 def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index, 420 [!cast<Register>("V"#Index), 421 !cast<Register>("V"#!add(Index, 1))], 422 ["v"#Index]>, 423 DwarfRegAlias<!cast<Register>("V"#Index)> { 424 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1]; 425 } 426 } 427 428 foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in { 429 def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index, 430 [!cast<Register>("V"#Index#"M2"), 431 !cast<Register>("V"#!add(Index, 2)#"M2")], 432 ["v"#Index]>, 433 DwarfRegAlias<!cast<Register>("V"#Index)> { 434 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1]; 435 } 436 } 437 438 foreach Index = [0, 8, 16, 24] in { 439 def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index, 440 [!cast<Register>("V"#Index#"M4"), 441 !cast<Register>("V"#!add(Index, 4)#"M4")], 442 ["v"#Index]>, 443 DwarfRegAlias<!cast<Register>("V"#Index)> { 444 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1]; 445 } 446 } 447 448 def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; 449 def VL : RISCVReg<0, "vl", ["vl"]>; 450 def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>; 451 def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>; 452} 453 454foreach m = [1, 2, 4] in { 455 foreach n = NFList<m>.L in { 456 def "VN" # n # "M" # m: RegisterTuples<SubRegSet<[], 0, n, m>.L, 457 VRegList<[], 0, n, m>.L>; 458 } 459} 460 461class VReg<list<ValueType> regTypes, dag regList, int Vlmul> 462 : RegisterClass<"RISCV", 463 regTypes, 464 64, // The maximum supported ELEN is 64. 465 regList> { 466 int VLMul = Vlmul; 467 int Size = !mul(Vlmul, 64); 468} 469 470def VR : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t, 471 vint16mf2_t, vint16mf4_t, vint32mf2_t, 472 vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, 473 vfloat16mf4_t, vfloat16mf2_t, vfloat16m1_t, 474 vfloat32mf2_t, vfloat32m1_t, vfloat64m1_t, 475 vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, 476 vbool2_t, vbool1_t], 477 (add (sequence "V%u", 25, 31), 478 (sequence "V%u", 8, 24), 479 (sequence "V%u", 0, 7)), 1>; 480 481def VRNoV0 : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t, 482 vint16mf2_t, vint16mf4_t, vint32mf2_t, 483 vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, 484 vfloat16mf4_t, vfloat16mf2_t, vfloat16m1_t, 485 vfloat32mf2_t, vfloat32m1_t, vfloat64m1_t, 486 vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, 487 vbool2_t, vbool1_t], 488 (add (sequence "V%u", 25, 31), 489 (sequence "V%u", 8, 24), 490 (sequence "V%u", 1, 7)), 1>; 491 492def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, 493 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], 494 (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, 495 V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2), 2>; 496 497def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, 498 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], 499 (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, 500 V18M2, V20M2, V22M2, V24M2, V2M2, V4M2, V6M2), 2>; 501 502def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, 503 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], 504 (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4), 4>; 505 506def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, 507 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], 508 (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V4M4), 4>; 509 510def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, 511 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], 512 (add V8M8, V16M8, V24M8, V0M8), 8>; 513 514def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, 515 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], 516 (add V8M8, V16M8, V24M8), 8>; 517 518defvar VMaskVTs = [vbool64_t, vbool32_t, vbool16_t, vbool8_t, 519 vbool4_t, vbool2_t, vbool1_t]; 520 521def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { 522 let Size = 64; 523} 524 525foreach m = LMULList.m in { 526 foreach nf = NFList<m>.L in { 527 def "VRN" # nf # "M" # m : VReg<[untyped], 528 (add !cast<RegisterTuples>("VN" # nf # "M" # m)), 529 !mul(nf, m)>; 530 } 531} 532