1//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the RISC-V register files 11//===----------------------------------------------------------------------===// 12 13let Namespace = "RISCV" in { 14class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 15 let HWEncoding{4-0} = Enc; 16 let AltNames = alt; 17} 18 19class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs, 20 list<string> alt = []> 21 : RegisterWithSubRegs<n, subregs> { 22 let HWEncoding{4-0} = Enc; 23 let AltNames = alt; 24} 25 26class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 27 let HWEncoding{4-0} = Enc; 28 let AltNames = alt; 29} 30 31def sub_16 : SubRegIndex<16>; 32class RISCVReg32<RISCVReg16 subreg> 33 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg], 34 subreg.AltNames> { 35 let SubRegIndices = [sub_16]; 36} 37 38// Because RISCVReg64 register have AsmName and AltNames that alias with their 39// 16/32-bit sub-register, RISCVAsmParser will need to coerce a register number 40// from a RISCVReg16/RISCVReg32 to the equivalent RISCVReg64 when appropriate. 41def sub_32 : SubRegIndex<32>; 42class RISCVReg64<RISCVReg32 subreg> 43 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg], 44 subreg.AltNames> { 45 let SubRegIndices = [sub_32]; 46} 47 48let FallbackRegAltNameIndex = NoRegAltName in 49def ABIRegAltName : RegAltNameIndex; 50 51def sub_vrm4_0 : SubRegIndex<256>; 52def sub_vrm4_1 : SubRegIndex<256, 256>; 53def sub_vrm2_0 : SubRegIndex<128>; 54def sub_vrm2_1 : SubRegIndex<128, 128>; 55def sub_vrm2_2 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_0>; 56def sub_vrm2_3 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_1>; 57def sub_vrm1_0 : SubRegIndex<64>; 58def sub_vrm1_1 : SubRegIndex<64, 64>; 59def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>; 60def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>; 61def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>; 62def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>; 63def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>; 64def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>; 65 66def sub_32_hi : SubRegIndex<32, 32>; 67} // Namespace = "RISCV" 68 69// Integer registers 70// CostPerUse is set higher for registers that may not be compressible as they 71// are not part of GPRC, the most restrictive register class used by the 72// compressed instruction set. This will influence the greedy register 73// allocator to reduce the use of registers that can't be encoded in 16 bit 74// instructions. 75 76let RegAltNameIndices = [ABIRegAltName] in { 77 let isConstant = true in 78 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; 79 let CostPerUse = [0, 1] in { 80 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; 81 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; 82 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; 83 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; 84 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; 85 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; 86 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; 87 } 88 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; 89 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; 90 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; 91 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; 92 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; 93 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; 94 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; 95 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; 96 let CostPerUse = [0, 1] in { 97 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; 98 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; 99 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; 100 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; 101 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; 102 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; 103 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; 104 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; 105 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>; 106 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>; 107 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>; 108 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>; 109 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>; 110 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; 111 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; 112 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; 113 } 114} 115 116def XLenVT : ValueTypeByHwMode<[RV32, RV64], 117 [i32, i64]>; 118// Allow f64 in GPR for ZDINX on RV64. 119def XLenFVT : ValueTypeByHwMode<[RV64], 120 [f64]>; 121def XLenRI : RegInfoByHwMode< 122 [RV32, RV64], 123 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 124 125class GPRRegisterClass<dag regList> 126 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, regList> { 127 let RegInfos = XLenRI; 128} 129 130// The order of registers represents the preferred allocation sequence. 131// Registers are listed in the order caller-save, callee-save, specials. 132def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17), 133 (sequence "X%u", 5, 7), 134 (sequence "X%u", 28, 31), 135 (sequence "X%u", 8, 9), 136 (sequence "X%u", 18, 27), 137 (sequence "X%u", 0, 4))>; 138 139def GPRX0 : GPRRegisterClass<(add X0)>; 140 141def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>; 142 143def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)>; 144 145// Don't use X1 or X5 for JALR since that is a hint to pop the return address 146// stack on some microarchitectures. Also remove the reserved registers X0, X2, 147// X3, and X4 as it reduces the number of register classes that get synthesized 148// by tablegen. 149def GPRJALR : GPRRegisterClass<(sub GPR, (sequence "X%u", 0, 5))>; 150 151def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15), 152 (sequence "X%u", 8, 9))>; 153 154// For indirect tail calls, we can't use callee-saved registers, as they are 155// restored to the saved value before the tail call, which would clobber a call 156// address. We shouldn't use x5 since that is a hint for to pop the return 157// address stack on some microarchitectures. 158def GPRTC : GPRRegisterClass<(add (sequence "X%u", 6, 7), 159 (sequence "X%u", 10, 17), 160 (sequence "X%u", 28, 31))>; 161 162def SP : GPRRegisterClass<(add X2)>; 163 164// Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension 165def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9), 166 (sequence "X%u", 18, 23))>; 167 168// Floating point registers 169let RegAltNameIndices = [ABIRegAltName] in { 170 def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; 171 def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; 172 def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; 173 def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; 174 def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; 175 def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; 176 def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; 177 def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; 178 def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; 179 def F9_H : RISCVReg16<9, "f9", ["fs1"]>, DwarfRegNum<[41]>; 180 def F10_H : RISCVReg16<10,"f10", ["fa0"]>, DwarfRegNum<[42]>; 181 def F11_H : RISCVReg16<11,"f11", ["fa1"]>, DwarfRegNum<[43]>; 182 def F12_H : RISCVReg16<12,"f12", ["fa2"]>, DwarfRegNum<[44]>; 183 def F13_H : RISCVReg16<13,"f13", ["fa3"]>, DwarfRegNum<[45]>; 184 def F14_H : RISCVReg16<14,"f14", ["fa4"]>, DwarfRegNum<[46]>; 185 def F15_H : RISCVReg16<15,"f15", ["fa5"]>, DwarfRegNum<[47]>; 186 def F16_H : RISCVReg16<16,"f16", ["fa6"]>, DwarfRegNum<[48]>; 187 def F17_H : RISCVReg16<17,"f17", ["fa7"]>, DwarfRegNum<[49]>; 188 def F18_H : RISCVReg16<18,"f18", ["fs2"]>, DwarfRegNum<[50]>; 189 def F19_H : RISCVReg16<19,"f19", ["fs3"]>, DwarfRegNum<[51]>; 190 def F20_H : RISCVReg16<20,"f20", ["fs4"]>, DwarfRegNum<[52]>; 191 def F21_H : RISCVReg16<21,"f21", ["fs5"]>, DwarfRegNum<[53]>; 192 def F22_H : RISCVReg16<22,"f22", ["fs6"]>, DwarfRegNum<[54]>; 193 def F23_H : RISCVReg16<23,"f23", ["fs7"]>, DwarfRegNum<[55]>; 194 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>; 195 def F25_H : RISCVReg16<25,"f25", ["fs9"]>, DwarfRegNum<[57]>; 196 def F26_H : RISCVReg16<26,"f26", ["fs10"]>, DwarfRegNum<[58]>; 197 def F27_H : RISCVReg16<27,"f27", ["fs11"]>, DwarfRegNum<[59]>; 198 def F28_H : RISCVReg16<28,"f28", ["ft8"]>, DwarfRegNum<[60]>; 199 def F29_H : RISCVReg16<29,"f29", ["ft9"]>, DwarfRegNum<[61]>; 200 def F30_H : RISCVReg16<30,"f30", ["ft10"]>, DwarfRegNum<[62]>; 201 def F31_H : RISCVReg16<31,"f31", ["ft11"]>, DwarfRegNum<[63]>; 202 203 foreach Index = 0-31 in { 204 def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>, 205 DwarfRegNum<[!add(Index, 32)]>; 206 } 207 208 foreach Index = 0-31 in { 209 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>, 210 DwarfRegNum<[!add(Index, 32)]>; 211 } 212} 213 214// The order of registers represents the preferred allocation sequence, 215// meaning caller-save regs are listed before callee-save. 216// We start by allocating argument registers in reverse order since they are 217// compressible. 218def FPR16 : RegisterClass<"RISCV", [f16, bf16], 16, (add 219 (sequence "F%u_H", 15, 10), // fa5-fa0 220 (sequence "F%u_H", 0, 7), // ft0-f7 221 (sequence "F%u_H", 16, 17), // fa6-fa7 222 (sequence "F%u_H", 28, 31), // ft8-ft11 223 (sequence "F%u_H", 8, 9), // fs0-fs1 224 (sequence "F%u_H", 18, 27) // fs2-fs11 225)>; 226 227def FPR32 : RegisterClass<"RISCV", [f32], 32, (add 228 (sequence "F%u_F", 15, 10), 229 (sequence "F%u_F", 0, 7), 230 (sequence "F%u_F", 16, 17), 231 (sequence "F%u_F", 28, 31), 232 (sequence "F%u_F", 8, 9), 233 (sequence "F%u_F", 18, 27) 234)>; 235 236def FPR32C : RegisterClass<"RISCV", [f32], 32, (add 237 (sequence "F%u_F", 15, 10), 238 (sequence "F%u_F", 8, 9) 239)>; 240 241// The order of registers represents the preferred allocation sequence, 242// meaning caller-save regs are listed before callee-save. 243def FPR64 : RegisterClass<"RISCV", [f64], 64, (add 244 (sequence "F%u_D", 15, 10), 245 (sequence "F%u_D", 0, 7), 246 (sequence "F%u_D", 16, 17), 247 (sequence "F%u_D", 28, 31), 248 (sequence "F%u_D", 8, 9), 249 (sequence "F%u_D", 18, 27) 250)>; 251 252def FPR64C : RegisterClass<"RISCV", [f64], 64, (add 253 (sequence "F%u_D", 15, 10), 254 (sequence "F%u_D", 8, 9) 255)>; 256 257// Vector type mapping to LLVM types. 258// 259// The V vector extension requires that VLEN >= 128 and <= 65536. 260// Additionally, the only supported ELEN values are 32 and 64, 261// thus `vscale` can be defined as VLEN/64, 262// allowing the same types with either ELEN value. 263// 264// MF8 MF4 MF2 M1 M2 M4 M8 265// i64* N/A N/A N/A nxv1i64 nxv2i64 nxv4i64 nxv8i64 266// i32 N/A N/A nxv1i32 nxv2i32 nxv4i32 nxv8i32 nxv16i32 267// i16 N/A nxv1i16 nxv2i16 nxv4i16 nxv8i16 nxv16i16 nxv32i16 268// i8 nxv1i8 nxv2i8 nxv4i8 nxv8i8 nxv16i8 nxv32i8 nxv64i8 269// double* N/A N/A N/A nxv1f64 nxv2f64 nxv4f64 nxv8f64 270// float N/A N/A nxv1f32 nxv2f32 nxv4f32 nxv8f32 nxv16f32 271// half N/A nxv1f16 nxv2f16 nxv4f16 nxv8f16 nxv16f16 nxv32f16 272// * ELEN=64 273 274defvar vint8mf8_t = nxv1i8; 275defvar vint8mf4_t = nxv2i8; 276defvar vint8mf2_t = nxv4i8; 277defvar vint8m1_t = nxv8i8; 278defvar vint8m2_t = nxv16i8; 279defvar vint8m4_t = nxv32i8; 280defvar vint8m8_t = nxv64i8; 281 282defvar vint16mf4_t = nxv1i16; 283defvar vint16mf2_t = nxv2i16; 284defvar vint16m1_t = nxv4i16; 285defvar vint16m2_t = nxv8i16; 286defvar vint16m4_t = nxv16i16; 287defvar vint16m8_t = nxv32i16; 288 289defvar vint32mf2_t = nxv1i32; 290defvar vint32m1_t = nxv2i32; 291defvar vint32m2_t = nxv4i32; 292defvar vint32m4_t = nxv8i32; 293defvar vint32m8_t = nxv16i32; 294 295defvar vint64m1_t = nxv1i64; 296defvar vint64m2_t = nxv2i64; 297defvar vint64m4_t = nxv4i64; 298defvar vint64m8_t = nxv8i64; 299 300defvar vfloat16mf4_t = nxv1f16; 301defvar vfloat16mf2_t = nxv2f16; 302defvar vfloat16m1_t = nxv4f16; 303defvar vfloat16m2_t = nxv8f16; 304defvar vfloat16m4_t = nxv16f16; 305defvar vfloat16m8_t = nxv32f16; 306 307defvar vbfloat16mf4_t = nxv1bf16; 308defvar vbfloat16mf2_t = nxv2bf16; 309defvar vbfloat16m1_t = nxv4bf16; 310defvar vbfloat16m2_t = nxv8bf16; 311defvar vbfloat16m4_t = nxv16bf16; 312defvar vbfloat16m8_t = nxv32bf16; 313 314defvar vfloat32mf2_t = nxv1f32; 315defvar vfloat32m1_t = nxv2f32; 316defvar vfloat32m2_t = nxv4f32; 317defvar vfloat32m4_t = nxv8f32; 318defvar vfloat32m8_t = nxv16f32; 319 320defvar vfloat64m1_t = nxv1f64; 321defvar vfloat64m2_t = nxv2f64; 322defvar vfloat64m4_t = nxv4f64; 323defvar vfloat64m8_t = nxv8f64; 324 325defvar vbool1_t = nxv64i1; 326defvar vbool2_t = nxv32i1; 327defvar vbool4_t = nxv16i1; 328defvar vbool8_t = nxv8i1; 329defvar vbool16_t = nxv4i1; 330defvar vbool32_t = nxv2i1; 331defvar vbool64_t = nxv1i1; 332 333// There is no need to define register classes for fractional LMUL. 334defvar LMULList = [1, 2, 4, 8]; 335 336//===----------------------------------------------------------------------===// 337// Utility classes for segment load/store. 338//===----------------------------------------------------------------------===// 339// The set of legal NF for LMUL = lmul. 340// LMUL <= 1, NF = 2, 3, 4, 5, 6, 7, 8 341// LMUL == 2, NF = 2, 3, 4 342// LMUL == 4, NF = 2 343// LMUL == 8, no legal NF 344class NFList<int lmul> { 345 list<int> L = !cond(!eq(lmul, 8): [], 346 !eq(lmul, 4): [2], 347 !eq(lmul, 2): [2, 3, 4], 348 true: [2, 3, 4, 5, 6, 7, 8]); 349} 350 351// Generate [start, end) SubRegIndex list. 352class SubRegSet<int nf, int lmul> { 353 list<SubRegIndex> L = !foldl([]<SubRegIndex>, 354 !range(0, 8), 355 AccList, i, 356 !listconcat(AccList, 357 !if(!lt(i, nf), 358 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)], 359 []))); 360} 361 362// Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX. 363// When NF = 2, the valid TUPLE_INDEX is 0 and 1. 364// For example, when LMUL = 4, the potential valid indexes is 365// [8, 12, 16, 20, 24, 28, 4]. However, not all these indexes are valid under 366// NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0. 367// The filter is 368// (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul) 369// 370// Use START = 0, LMUL = 4 and NF = 2 as the example, 371// i x 4 <= 24 372// The class will return [8, 12, 16, 20, 24, 4]. 373// Use START = 1, LMUL = 4 and NF = 2 as the example, 374// (1 + i) x 4 <= 28 375// The class will return [12, 16, 20, 24, 28, 8]. 376// 377class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> { 378 list<int> R = 379 !foldl([]<int>, 380 !if(isV0, [0], 381 !cond( 382 !eq(lmul, 1): !listconcat(!range(8, 32), !range(1, 8)), 383 !eq(lmul, 2): !listconcat(!range(4, 16), !range(1, 4)), 384 !eq(lmul, 4): !listconcat(!range(2, 8), !range(1, 2)))), 385 L, i, 386 !listconcat(L, 387 !if(!le(!mul(!add(i, tuple_index), lmul), 388 !sub(!add(32, !mul(tuple_index, lmul)), !mul(nf, lmul))), 389 [!mul(!add(i, tuple_index), lmul)], []))); 390} 391 392// This class returns a list of vector register collections. 393// For example, for NF = 2 and LMUL = 4, 394// it will return 395// ([ V8M4, V12M4, V16M4, V20M4, V24M4, V4M4], 396// [V12M4, V16M4, V20M4, V24M4, V28M4, V8M4]) 397// 398class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> { 399 list<dag> L = 400 !if(!ge(start, nf), 401 LIn, 402 !listconcat( 403 [!dag(add, 404 !foreach(i, IndexSet<start, nf, lmul, isV0>.R, 405 !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2", 406 !eq(lmul, 4): "M4", 407 true: ""))), 408 !listsplat("", 409 !size(IndexSet<start, nf, lmul, isV0>.R)))], 410 VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L)); 411} 412 413// Vector registers 414foreach Index = !range(0, 32, 1) in { 415 def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>; 416} 417 418foreach Index = !range(0, 32, 2) in { 419 def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index, 420 [!cast<Register>("V"#Index), 421 !cast<Register>("V"#!add(Index, 1))]>, 422 DwarfRegAlias<!cast<Register>("V"#Index)> { 423 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1]; 424 } 425} 426 427foreach Index = !range(0, 32, 4) in { 428 def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index, 429 [!cast<Register>("V"#Index#"M2"), 430 !cast<Register>("V"#!add(Index, 2)#"M2")]>, 431 DwarfRegAlias<!cast<Register>("V"#Index)> { 432 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1]; 433 } 434} 435 436foreach Index = !range(0, 32, 8) in { 437 def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index, 438 [!cast<Register>("V"#Index#"M4"), 439 !cast<Register>("V"#!add(Index, 4)#"M4")]>, 440 DwarfRegAlias<!cast<Register>("V"#Index)> { 441 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1]; 442 } 443} 444 445def VTYPE : RISCVReg<0, "vtype">; 446def VL : RISCVReg<0, "vl">; 447def VXSAT : RISCVReg<0, "vxsat">; 448def VXRM : RISCVReg<0, "vxrm">; 449let isConstant = true in 450def VLENB : RISCVReg<0, "vlenb">, 451 DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>; 452 453def VCSR : RegisterClass<"RISCV", [XLenVT], 32, 454 (add VTYPE, VL, VLENB)> { 455 let RegInfos = XLenRI; 456 let isAllocatable = 0; 457} 458 459 460foreach m = [1, 2, 4] in { 461 foreach n = NFList<m>.L in { 462 def "VN" # n # "M" # m # "NoV0": RegisterTuples< 463 SubRegSet<n, m>.L, 464 VRegList<[], 0, n, m, false>.L>; 465 def "VN" # n # "M" # m # "V0" : RegisterTuples< 466 SubRegSet<n, m>.L, 467 VRegList<[], 0, n, m, true>.L>; 468 } 469} 470 471class VReg<list<ValueType> regTypes, dag regList, int Vlmul> 472 : RegisterClass<"RISCV", 473 regTypes, 474 64, // The maximum supported ELEN is 64. 475 regList> { 476 int VLMul = Vlmul; 477 int Size = !mul(Vlmul, 64); 478} 479 480defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, 481 vbool32_t, vbool64_t]; 482 483defvar VM1VTs = [vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, 484 vbfloat16m1_t, vfloat16m1_t, vfloat32m1_t, 485 vfloat64m1_t, vint8mf2_t, vint8mf4_t, vint8mf8_t, 486 vint16mf2_t, vint16mf4_t, vint32mf2_t, 487 vfloat16mf4_t, vfloat16mf2_t, vbfloat16mf4_t, 488 vbfloat16mf2_t, vfloat32mf2_t]; 489 490defvar VM2VTs = [vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, 491 vfloat16m2_t, vbfloat16m2_t, 492 vfloat32m2_t, vfloat64m2_t]; 493 494defvar VM4VTs = [vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, 495 vfloat16m4_t, vbfloat16m4_t, 496 vfloat32m4_t, vfloat64m4_t]; 497 498defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, 499 vfloat16m8_t, vbfloat16m8_t, 500 vfloat32m8_t, vfloat64m8_t]; 501 502def VR : VReg<!listconcat(VM1VTs, VMaskVTs), 503 (add (sequence "V%u", 8, 31), 504 (sequence "V%u", 0, 7)), 1>; 505 506def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), 507 (add (sequence "V%u", 8, 31), 508 (sequence "V%u", 1, 7)), 1>; 509 510def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), 511 (sequence "V%uM2", 0, 7, 2)), 2>; 512 513def VRM2NoV0 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), 514 (sequence "V%uM2", 2, 7, 2)), 2>; 515 516def VRM4 : VReg<VM4VTs, 517 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>; 518 519def VRM4NoV0 : VReg<VM4VTs, 520 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>; 521 522def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>; 523 524def VRM8NoV0 : VReg<VM8VTs, (add V8M8, V16M8, V24M8), 8>; 525 526def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { 527 let Size = 64; 528} 529 530let RegInfos = XLenRI in { 531def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>; 532def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>; 533} // RegInfos = XLenRI 534 535// Dummy zero register for use in the register pair containing X0 (as X1 is 536// not read to or written when the X0 register pair is used). 537def DUMMY_REG_PAIR_WITH_X0 : RISCVReg<0, "0">; 538 539// Must add DUMMY_REG_PAIR_WITH_X0 to a separate register class to prevent the 540// register's existence from changing codegen (due to the regPressureSetLimit 541// for the GPR register class being altered). 542def GPRAll : GPRRegisterClass<(add GPR, DUMMY_REG_PAIR_WITH_X0)>; 543 544let RegAltNameIndices = [ABIRegAltName] in { 545 def X0_PD : RISCVRegWithSubRegs<0, X0.AsmName, 546 [X0, DUMMY_REG_PAIR_WITH_X0], 547 X0.AltNames> { 548 let SubRegIndices = [sub_32, sub_32_hi]; 549 let CoveredBySubRegs = 1; 550 } 551 foreach I = 1-15 in { 552 defvar Index = !shl(I, 1); 553 defvar Reg = !cast<Register>("X"#Index); 554 defvar RegP1 = !cast<Register>("X"#!add(Index,1)); 555 def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName, 556 [Reg, RegP1], 557 Reg.AltNames> { 558 let SubRegIndices = [sub_32, sub_32_hi]; 559 let CoveredBySubRegs = 1; 560 } 561 } 562} 563 564let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in 565def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add 566 X10_PD, X12_PD, X14_PD, X16_PD, 567 X6_PD, 568 X28_PD, X30_PD, 569 X8_PD, 570 X18_PD, X20_PD, X22_PD, X24_PD, X26_PD, 571 X0_PD, X2_PD, X4_PD 572)>; 573 574// The register class is added for inline assembly for vector mask types. 575def VM : VReg<VMaskVTs, 576 (add (sequence "V%u", 8, 31), 577 (sequence "V%u", 0, 7)), 1>; 578 579foreach m = LMULList in { 580 foreach nf = NFList<m>.L in { 581 def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped], 582 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")), 583 !mul(nf, m)>; 584 def "VRN" # nf # "M" # m: VReg<[untyped], 585 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"), 586 !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")), 587 !mul(nf, m)>; 588 } 589} 590 591// Special registers 592def FFLAGS : RISCVReg<0, "fflags">; 593def FRM : RISCVReg<0, "frm">; 594