1//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the RISC-V register files 11//===----------------------------------------------------------------------===// 12 13let Namespace = "RISCV" in { 14class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 15 let HWEncoding{4-0} = Enc; 16 let AltNames = alt; 17} 18 19class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 20 let HWEncoding{4-0} = Enc; 21 let AltNames = alt; 22} 23 24def sub_16 : SubRegIndex<16>; 25class RISCVReg32<RISCVReg16 subreg> : Register<""> { 26 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 27 let SubRegs = [subreg]; 28 let SubRegIndices = [sub_16]; 29 let AsmName = subreg.AsmName; 30 let AltNames = subreg.AltNames; 31} 32 33// Because RISCVReg64 register have AsmName and AltNames that alias with their 34// 16/32-bit sub-register, RISCVAsmParser will need to coerce a register number 35// from a RISCVReg16/RISCVReg32 to the equivalent RISCVReg64 when appropriate. 36def sub_32 : SubRegIndex<32>; 37class RISCVReg64<RISCVReg32 subreg> : Register<""> { 38 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 39 let SubRegs = [subreg]; 40 let SubRegIndices = [sub_32]; 41 let AsmName = subreg.AsmName; 42 let AltNames = subreg.AltNames; 43} 44 45class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs, 46 list<string> alt = []> 47 : RegisterWithSubRegs<n, subregs> { 48 let HWEncoding{4-0} = Enc; 49 let AltNames = alt; 50} 51 52def ABIRegAltName : RegAltNameIndex; 53 54def sub_vrm4_0 : SubRegIndex<256>; 55def sub_vrm4_1 : SubRegIndex<256, 256>; 56def sub_vrm2_0 : SubRegIndex<128>; 57def sub_vrm2_1 : SubRegIndex<128, 128>; 58def sub_vrm2_2 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_0>; 59def sub_vrm2_3 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_1>; 60def sub_vrm1_0 : SubRegIndex<64>; 61def sub_vrm1_1 : SubRegIndex<64, 64>; 62def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>; 63def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>; 64def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>; 65def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>; 66def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>; 67def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>; 68 69def sub_32_hi : SubRegIndex<32, 32>; 70} // Namespace = "RISCV" 71 72// Integer registers 73// CostPerUse is set higher for registers that may not be compressible as they 74// are not part of GPRC, the most restrictive register class used by the 75// compressed instruction set. This will influence the greedy register 76// allocator to reduce the use of registers that can't be encoded in 16 bit 77// instructions. 78 79let RegAltNameIndices = [ABIRegAltName] in { 80 let isConstant = true in 81 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; 82 let CostPerUse = [0, 1] in { 83 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; 84 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; 85 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; 86 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; 87 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; 88 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; 89 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; 90 } 91 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; 92 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; 93 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; 94 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; 95 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; 96 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; 97 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; 98 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; 99 let CostPerUse = [0, 1] in { 100 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; 101 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; 102 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; 103 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; 104 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; 105 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; 106 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; 107 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; 108 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>; 109 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>; 110 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>; 111 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>; 112 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>; 113 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; 114 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; 115 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; 116 } 117} 118 119def XLenVT : ValueTypeByHwMode<[RV32, RV64], 120 [i32, i64]>; 121def XLenRI : RegInfoByHwMode< 122 [RV32, RV64], 123 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 124 125// The order of registers represents the preferred allocation sequence. 126// Registers are listed in the order caller-save, callee-save, specials. 127def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add 128 (sequence "X%u", 10, 17), 129 (sequence "X%u", 5, 7), 130 (sequence "X%u", 28, 31), 131 (sequence "X%u", 8, 9), 132 (sequence "X%u", 18, 27), 133 (sequence "X%u", 0, 4) 134 )> { 135 let RegInfos = XLenRI; 136} 137 138def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> { 139 let RegInfos = XLenRI; 140} 141 142def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X0)> { 143 let RegInfos = XLenRI; 144} 145 146def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X0, X2)> { 147 let RegInfos = XLenRI; 148} 149 150// Don't use X1 or X5 for JALR since that is a hint to pop the return address 151// stack on some microarchitectures. Also remove the reserved registers X0, X2, 152// X3, and X4 as it reduces the number of register classes that get synthesized 153// by tablegen. 154def GPRJALR : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, (sequence "X%u", 0, 5))> { 155 let RegInfos = XLenRI; 156} 157 158def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add 159 (sequence "X%u", 10, 15), 160 (sequence "X%u", 8, 9) 161 )> { 162 let RegInfos = XLenRI; 163} 164 165// For indirect tail calls, we can't use callee-saved registers, as they are 166// restored to the saved value before the tail call, which would clobber a call 167// address. We shouldn't use x5 since that is a hint for to pop the return 168// address stack on some microarchitectures. 169def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add 170 (sequence "X%u", 6, 7), 171 (sequence "X%u", 10, 17), 172 (sequence "X%u", 28, 31) 173 )> { 174 let RegInfos = XLenRI; 175} 176 177def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { 178 let RegInfos = XLenRI; 179} 180 181// Floating point registers 182let RegAltNameIndices = [ABIRegAltName] in { 183 def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; 184 def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; 185 def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; 186 def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; 187 def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; 188 def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; 189 def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; 190 def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; 191 def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; 192 def F9_H : RISCVReg16<9, "f9", ["fs1"]>, DwarfRegNum<[41]>; 193 def F10_H : RISCVReg16<10,"f10", ["fa0"]>, DwarfRegNum<[42]>; 194 def F11_H : RISCVReg16<11,"f11", ["fa1"]>, DwarfRegNum<[43]>; 195 def F12_H : RISCVReg16<12,"f12", ["fa2"]>, DwarfRegNum<[44]>; 196 def F13_H : RISCVReg16<13,"f13", ["fa3"]>, DwarfRegNum<[45]>; 197 def F14_H : RISCVReg16<14,"f14", ["fa4"]>, DwarfRegNum<[46]>; 198 def F15_H : RISCVReg16<15,"f15", ["fa5"]>, DwarfRegNum<[47]>; 199 def F16_H : RISCVReg16<16,"f16", ["fa6"]>, DwarfRegNum<[48]>; 200 def F17_H : RISCVReg16<17,"f17", ["fa7"]>, DwarfRegNum<[49]>; 201 def F18_H : RISCVReg16<18,"f18", ["fs2"]>, DwarfRegNum<[50]>; 202 def F19_H : RISCVReg16<19,"f19", ["fs3"]>, DwarfRegNum<[51]>; 203 def F20_H : RISCVReg16<20,"f20", ["fs4"]>, DwarfRegNum<[52]>; 204 def F21_H : RISCVReg16<21,"f21", ["fs5"]>, DwarfRegNum<[53]>; 205 def F22_H : RISCVReg16<22,"f22", ["fs6"]>, DwarfRegNum<[54]>; 206 def F23_H : RISCVReg16<23,"f23", ["fs7"]>, DwarfRegNum<[55]>; 207 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>; 208 def F25_H : RISCVReg16<25,"f25", ["fs9"]>, DwarfRegNum<[57]>; 209 def F26_H : RISCVReg16<26,"f26", ["fs10"]>, DwarfRegNum<[58]>; 210 def F27_H : RISCVReg16<27,"f27", ["fs11"]>, DwarfRegNum<[59]>; 211 def F28_H : RISCVReg16<28,"f28", ["ft8"]>, DwarfRegNum<[60]>; 212 def F29_H : RISCVReg16<29,"f29", ["ft9"]>, DwarfRegNum<[61]>; 213 def F30_H : RISCVReg16<30,"f30", ["ft10"]>, DwarfRegNum<[62]>; 214 def F31_H : RISCVReg16<31,"f31", ["ft11"]>, DwarfRegNum<[63]>; 215 216 foreach Index = 0-31 in { 217 def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>, 218 DwarfRegNum<[!add(Index, 32)]>; 219 } 220 221 foreach Index = 0-31 in { 222 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>, 223 DwarfRegNum<[!add(Index, 32)]>; 224 } 225} 226 227// The order of registers represents the preferred allocation sequence, 228// meaning caller-save regs are listed before callee-save. 229def FPR16 : RegisterClass<"RISCV", [f16], 16, (add 230 (sequence "F%u_H", 0, 7), 231 (sequence "F%u_H", 10, 17), 232 (sequence "F%u_H", 28, 31), 233 (sequence "F%u_H", 8, 9), 234 (sequence "F%u_H", 18, 27) 235)>; 236 237def FPR32 : RegisterClass<"RISCV", [f32], 32, (add 238 (sequence "F%u_F", 0, 7), 239 (sequence "F%u_F", 10, 17), 240 (sequence "F%u_F", 28, 31), 241 (sequence "F%u_F", 8, 9), 242 (sequence "F%u_F", 18, 27) 243)>; 244 245def FPR32C : RegisterClass<"RISCV", [f32], 32, (add 246 (sequence "F%u_F", 10, 15), 247 (sequence "F%u_F", 8, 9) 248)>; 249 250// The order of registers represents the preferred allocation sequence, 251// meaning caller-save regs are listed before callee-save. 252def FPR64 : RegisterClass<"RISCV", [f64], 64, (add 253 (sequence "F%u_D", 0, 7), 254 (sequence "F%u_D", 10, 17), 255 (sequence "F%u_D", 28, 31), 256 (sequence "F%u_D", 8, 9), 257 (sequence "F%u_D", 18, 27) 258)>; 259 260def FPR64C : RegisterClass<"RISCV", [f64], 64, (add 261 (sequence "F%u_D", 10, 15), 262 (sequence "F%u_D", 8, 9) 263)>; 264 265// Vector type mapping to LLVM types. 266// 267// The V vector extension requires that VLEN >= 128 and <= 65536. 268// Additionally, the only supported ELEN values are 32 and 64, 269// thus `vscale` can be defined as VLEN/64, 270// allowing the same types with either ELEN value. 271// 272// MF8 MF4 MF2 M1 M2 M4 M8 273// i64* N/A N/A N/A nxv1i64 nxv2i64 nxv4i64 nxv8i64 274// i32 N/A N/A nxv1i32 nxv2i32 nxv4i32 nxv8i32 nxv16i32 275// i16 N/A nxv1i16 nxv2i16 nxv4i16 nxv8i16 nxv16i16 nxv32i16 276// i8 nxv1i8 nxv2i8 nxv4i8 nxv8i8 nxv16i8 nxv32i8 nxv64i8 277// double* N/A N/A N/A nxv1f64 nxv2f64 nxv4f64 nxv8f64 278// float N/A N/A nxv1f32 nxv2f32 nxv4f32 nxv8f32 nxv16f32 279// half N/A nxv1f16 nxv2f16 nxv4f16 nxv8f16 nxv16f16 nxv32f16 280// * ELEN=64 281 282defvar vint8mf8_t = nxv1i8; 283defvar vint8mf4_t = nxv2i8; 284defvar vint8mf2_t = nxv4i8; 285defvar vint8m1_t = nxv8i8; 286defvar vint8m2_t = nxv16i8; 287defvar vint8m4_t = nxv32i8; 288defvar vint8m8_t = nxv64i8; 289 290defvar vint16mf4_t = nxv1i16; 291defvar vint16mf2_t = nxv2i16; 292defvar vint16m1_t = nxv4i16; 293defvar vint16m2_t = nxv8i16; 294defvar vint16m4_t = nxv16i16; 295defvar vint16m8_t = nxv32i16; 296 297defvar vint32mf2_t = nxv1i32; 298defvar vint32m1_t = nxv2i32; 299defvar vint32m2_t = nxv4i32; 300defvar vint32m4_t = nxv8i32; 301defvar vint32m8_t = nxv16i32; 302 303defvar vint64m1_t = nxv1i64; 304defvar vint64m2_t = nxv2i64; 305defvar vint64m4_t = nxv4i64; 306defvar vint64m8_t = nxv8i64; 307 308defvar vfloat16mf4_t = nxv1f16; 309defvar vfloat16mf2_t = nxv2f16; 310defvar vfloat16m1_t = nxv4f16; 311defvar vfloat16m2_t = nxv8f16; 312defvar vfloat16m4_t = nxv16f16; 313defvar vfloat16m8_t = nxv32f16; 314 315defvar vfloat32mf2_t = nxv1f32; 316defvar vfloat32m1_t = nxv2f32; 317defvar vfloat32m2_t = nxv4f32; 318defvar vfloat32m4_t = nxv8f32; 319defvar vfloat32m8_t = nxv16f32; 320 321defvar vfloat64m1_t = nxv1f64; 322defvar vfloat64m2_t = nxv2f64; 323defvar vfloat64m4_t = nxv4f64; 324defvar vfloat64m8_t = nxv8f64; 325 326defvar vbool1_t = nxv64i1; 327defvar vbool2_t = nxv32i1; 328defvar vbool4_t = nxv16i1; 329defvar vbool8_t = nxv8i1; 330defvar vbool16_t = nxv4i1; 331defvar vbool32_t = nxv2i1; 332defvar vbool64_t = nxv1i1; 333 334// There is no need to define register classes for fractional LMUL. 335def LMULList { 336 list<int> m = [1, 2, 4, 8]; 337} 338 339//===----------------------------------------------------------------------===// 340// Utility classes for segment load/store. 341//===----------------------------------------------------------------------===// 342// The set of legal NF for LMUL = lmul. 343// LMUL == 1, NF = 2, 3, 4, 5, 6, 7, 8 344// LMUL == 2, NF = 2, 3, 4 345// LMUL == 4, NF = 2 346class NFList<int lmul> { 347 list<int> L = !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8], 348 !eq(lmul, 2): [2, 3, 4], 349 !eq(lmul, 4): [2], 350 !eq(lmul, 8): []); 351} 352 353// Generate [start, end) SubRegIndex list. 354class SubRegSet<int nf, int lmul> { 355 list<SubRegIndex> L = !foldl([]<SubRegIndex>, 356 [0, 1, 2, 3, 4, 5, 6, 7], 357 AccList, i, 358 !listconcat(AccList, 359 !if(!lt(i, nf), 360 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)], 361 []))); 362} 363 364// Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX. 365// When NF = 2, the valid TUPLE_INDEX is 0 and 1. 366// For example, when LMUL = 4, the potential valid indexes is 367// [8, 12, 16, 20, 24, 28, 4]. However, not all these indexes are valid under 368// NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0. 369// The filter is 370// (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul) 371// 372// Use START = 0, LMUL = 4 and NF = 2 as the example, 373// i x 4 <= 24 374// The class will return [8, 12, 16, 20, 24, 4]. 375// Use START = 1, LMUL = 4 and NF = 2 as the example, 376// (1 + i) x 4 <= 28 377// The class will return [12, 16, 20, 24, 28, 8]. 378// 379class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> { 380 list<int> R = 381 !foldl([]<int>, 382 !if(isV0, [0], 383 !cond( 384 !eq(lmul, 1): 385 [8, 9, 10, 11, 12, 13, 14, 15, 386 16, 17, 18, 19, 20, 21, 22, 23, 387 24, 25, 26, 27, 28, 29, 30, 31, 388 1, 2, 3, 4, 5, 6, 7], 389 !eq(lmul, 2): 390 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 1, 2, 3], 391 !eq(lmul, 4): 392 [2, 3, 4, 5, 6, 7, 1])), 393 L, i, 394 !listconcat(L, 395 !if(!le(!mul(!add(i, tuple_index), lmul), 396 !sub(!add(32, !mul(tuple_index, lmul)), !mul(nf, lmul))), 397 [!mul(!add(i, tuple_index), lmul)], []))); 398} 399 400// This class returns a list of vector register collections. 401// For example, for NF = 2 and LMUL = 4, 402// it will return 403// ([ V8M4, V12M4, V16M4, V20M4, V24M4, V4M4], 404// [V12M4, V16M4, V20M4, V24M4, V28M4, V8M4]) 405// 406class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> { 407 list<dag> L = 408 !if(!ge(start, nf), 409 LIn, 410 !listconcat( 411 [!dag(add, 412 !foreach(i, IndexSet<start, nf, lmul, isV0>.R, 413 !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2", 414 !eq(lmul, 4): "M4", 415 true: ""))), 416 !listsplat("", 417 !size(IndexSet<start, nf, lmul, isV0>.R)))], 418 VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L)); 419} 420 421// Vector registers 422let RegAltNameIndices = [ABIRegAltName] in { 423 foreach Index = 0-31 in { 424 def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 96)]>; 425 } 426 427 foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 428 24, 26, 28, 30] in { 429 def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index, 430 [!cast<Register>("V"#Index), 431 !cast<Register>("V"#!add(Index, 1))], 432 ["v"#Index]>, 433 DwarfRegAlias<!cast<Register>("V"#Index)> { 434 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1]; 435 } 436 } 437 438 foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in { 439 def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index, 440 [!cast<Register>("V"#Index#"M2"), 441 !cast<Register>("V"#!add(Index, 2)#"M2")], 442 ["v"#Index]>, 443 DwarfRegAlias<!cast<Register>("V"#Index)> { 444 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1]; 445 } 446 } 447 448 foreach Index = [0, 8, 16, 24] in { 449 def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index, 450 [!cast<Register>("V"#Index#"M4"), 451 !cast<Register>("V"#!add(Index, 4)#"M4")], 452 ["v"#Index]>, 453 DwarfRegAlias<!cast<Register>("V"#Index)> { 454 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1]; 455 } 456 } 457 458 def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; 459 def VL : RISCVReg<0, "vl", ["vl"]>; 460 def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>; 461 def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>; 462 let isConstant = true in 463 def VLENB : RISCVReg<0, "vlenb", ["vlenb"]>, 464 DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>; 465} 466 467def VCSR : RegisterClass<"RISCV", [XLenVT], 32, 468 (add VTYPE, VL, VLENB)> { 469 let RegInfos = XLenRI; 470} 471 472 473foreach m = [1, 2, 4] in { 474 foreach n = NFList<m>.L in { 475 def "VN" # n # "M" # m # "NoV0": RegisterTuples< 476 SubRegSet<n, m>.L, 477 VRegList<[], 0, n, m, false>.L>; 478 def "VN" # n # "M" # m # "V0" : RegisterTuples< 479 SubRegSet<n, m>.L, 480 VRegList<[], 0, n, m, true>.L>; 481 } 482} 483 484class VReg<list<ValueType> regTypes, dag regList, int Vlmul> 485 : RegisterClass<"RISCV", 486 regTypes, 487 64, // The maximum supported ELEN is 64. 488 regList> { 489 int VLMul = Vlmul; 490 int Size = !mul(Vlmul, 64); 491} 492 493defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, 494 vbool32_t, vbool64_t]; 495 496defvar VM1VTs = [vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, 497 vfloat16m1_t, vfloat32m1_t, vfloat64m1_t, 498 vint8mf2_t, vint8mf4_t, vint8mf8_t, 499 vint16mf2_t, vint16mf4_t, vint32mf2_t, 500 vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t]; 501 502defvar VM2VTs = [vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, 503 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t]; 504 505defvar VM4VTs = [vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, 506 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t]; 507 508defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, 509 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t]; 510 511def VR : VReg<!listconcat(VM1VTs, VMaskVTs), 512 (add (sequence "V%u", 8, 31), 513 (sequence "V%u", 0, 7)), 1>; 514 515def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), 516 (add (sequence "V%u", 8, 31), 517 (sequence "V%u", 1, 7)), 1>; 518 519def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), 520 (sequence "V%uM2", 0, 7, 2)), 2>; 521 522def VRM2NoV0 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), 523 (sequence "V%uM2", 2, 7, 2)), 2>; 524 525def VRM4 : VReg<VM4VTs, 526 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>; 527 528def VRM4NoV0 : VReg<VM4VTs, 529 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>; 530 531def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>; 532 533def VRM8NoV0 : VReg<VM8VTs, (add V8M8, V16M8, V24M8), 8>; 534 535def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { 536 let Size = 64; 537} 538 539let RegInfos = XLenRI in { 540def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>; 541def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>; 542def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; 543} // RegInfos = XLenRI 544 545let RegAltNameIndices = [ABIRegAltName] in { 546 foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 547 24, 26, 28, 30] in { 548 defvar Reg = !cast<Register>("X"#Index); 549 def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName, 550 [!cast<Register>("X"#Index), 551 !cast<Register>("X"#!add(Index, 1))], 552 Reg.AltNames> { 553 let SubRegIndices = [sub_32, sub_32_hi]; 554 } 555 } 556} 557 558let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in 559def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add 560 X10_PD, X12_PD, X14_PD, X16_PD, 561 X6_PD, 562 X28_PD, X30_PD, 563 X8_PD, 564 X18_PD, X20_PD, X22_PD, X24_PD, X26_PD, 565 X0_PD, X2_PD, X4_PD 566)>; 567 568// The register class is added for inline assembly for vector mask types. 569def VM : VReg<VMaskVTs, 570 (add (sequence "V%u", 8, 31), 571 (sequence "V%u", 0, 7)), 1>; 572 573foreach m = LMULList.m in { 574 foreach nf = NFList<m>.L in { 575 def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped], 576 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")), 577 !mul(nf, m)>; 578 def "VRN" # nf # "M" # m: VReg<[untyped], 579 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"), 580 !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")), 581 !mul(nf, m)>; 582 } 583} 584 585// Special registers 586def FFLAGS : RISCVReg<0, "fflags">; 587def FRM : RISCVReg<0, "frm">; 588 589// Any type register. Used for .insn directives when we don't know what the 590// register types could be. 591// NOTE: The alignment and size are bogus values. The Size needs to be non-zero 592// or tablegen will use "untyped" to determine the size which will assert. 593let isAllocatable = 0 in 594def AnyReg : RegisterClass<"RISCV", [untyped], 32, 595 (add (sequence "X%u", 0, 31), 596 (sequence "F%u_D", 0, 31), 597 (sequence "V%u", 0, 31))> { 598 let Size = 32; 599} 600