1//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10 11// SCR1: https://github.com/syntacore/scr1 12 13// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max). 14// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially 15// same scheduling characteristics. 16 17// SCR1 is single-issue in-order processor 18def SyntacoreSCR1Model : SchedMachineModel { 19 let MicroOpBufferSize = 0; 20 let IssueWidth = 1; 21 let LoadLatency = 2; 22 let MispredictPenalty = 3; 23 let CompleteModel = 0; 24 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, 25 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, 26 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, 27 HasVInstructions]; 28} 29 30let SchedModel = SyntacoreSCR1Model in { 31 32let BufferSize = 0 in { 33def SCR1_ALU : ProcResource<1>; 34def SCR1_LSU : ProcResource<1>; 35def SCR1_MUL : ProcResource<1>; 36def SCR1_DIV : ProcResource<1>; 37def SCR1_CFU : ProcResource<1>; 38} 39 40// Branching 41def : WriteRes<WriteJmp, [SCR1_CFU]>; 42def : WriteRes<WriteJal, [SCR1_CFU]>; 43def : WriteRes<WriteJalr, [SCR1_CFU]>; 44 45// Integer arithmetic and logic 46def : WriteRes<WriteIALU32, [SCR1_ALU]>; 47def : WriteRes<WriteIALU, [SCR1_ALU]>; 48def : WriteRes<WriteShiftImm32, [SCR1_ALU]>; 49def : WriteRes<WriteShiftImm, [SCR1_ALU]>; 50def : WriteRes<WriteShiftReg32, [SCR1_ALU]>; 51def : WriteRes<WriteShiftReg, [SCR1_ALU]>; 52 53// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX 54def : WriteRes<WriteIMul, [SCR1_MUL]>; 55def : WriteRes<WriteIMul32, [SCR1_MUL]>; 56 57// Integer division: latency 33, inverse throughput 33 58let Latency = 33, ResourceCycles = [33] in { 59def : WriteRes<WriteIDiv32, [SCR1_DIV]>; 60def : WriteRes<WriteIDiv, [SCR1_DIV]>; 61} 62 63// Load/store instructions on SCR1 have latency 2 and inverse throughput 2 64// (SCR1_CFG_RV32IMC_MAX includes TCM) 65let Latency = 2, ResourceCycles=[2] in { 66// Memory 67def : WriteRes<WriteSTB, [SCR1_LSU]>; 68def : WriteRes<WriteSTH, [SCR1_LSU]>; 69def : WriteRes<WriteSTW, [SCR1_LSU]>; 70def : WriteRes<WriteSTD, [SCR1_LSU]>; 71def : WriteRes<WriteLDB, [SCR1_LSU]>; 72def : WriteRes<WriteLDH, [SCR1_LSU]>; 73def : WriteRes<WriteLDW, [SCR1_LSU]>; 74def : WriteRes<WriteLDD, [SCR1_LSU]>; 75} 76 77let Unsupported = true in { 78// Atomic memory 79def : WriteRes<WriteAtomicW, [SCR1_LSU]>; 80def : WriteRes<WriteAtomicD, [SCR1_LSU]>; 81def : WriteRes<WriteAtomicLDW, [SCR1_LSU]>; 82def : WriteRes<WriteAtomicLDD, [SCR1_LSU]>; 83def : WriteRes<WriteAtomicSTW, [SCR1_LSU]>; 84def : WriteRes<WriteAtomicSTD, [SCR1_LSU]>; 85 86// FP load/store 87def : WriteRes<WriteFST32, [SCR1_LSU]>; 88def : WriteRes<WriteFST64, [SCR1_LSU]>; 89def : WriteRes<WriteFLD32, [SCR1_LSU]>; 90def : WriteRes<WriteFLD64, [SCR1_LSU]>; 91 92// FP instructions 93def : WriteRes<WriteFAdd32, []>; 94def : WriteRes<WriteFSGNJ32, []>; 95def : WriteRes<WriteFMinMax32, []>; 96def : WriteRes<WriteFAdd64, []>; 97def : WriteRes<WriteFSGNJ64, []>; 98def : WriteRes<WriteFMinMax64, []>; 99def : WriteRes<WriteFCvtI32ToF32, []>; 100def : WriteRes<WriteFCvtI32ToF64, []>; 101def : WriteRes<WriteFCvtI64ToF32, []>; 102def : WriteRes<WriteFCvtI64ToF64, []>; 103def : WriteRes<WriteFCvtF32ToI32, []>; 104def : WriteRes<WriteFCvtF32ToI64, []>; 105def : WriteRes<WriteFCvtF64ToI32, []>; 106def : WriteRes<WriteFCvtF64ToI64, []>; 107def : WriteRes<WriteFCvtF32ToF64, []>; 108def : WriteRes<WriteFCvtF64ToF32, []>; 109def : WriteRes<WriteFClass32, []>; 110def : WriteRes<WriteFClass64, []>; 111def : WriteRes<WriteFCmp32, []>; 112def : WriteRes<WriteFCmp64, []>; 113def : WriteRes<WriteFMovF32ToI32, []>; 114def : WriteRes<WriteFMovI32ToF32, []>; 115def : WriteRes<WriteFMovF64ToI64, []>; 116def : WriteRes<WriteFMovI64ToF64, []>; 117def : WriteRes<WriteFMul32, []>; 118def : WriteRes<WriteFMA32, []>; 119def : WriteRes<WriteFMul64, []>; 120def : WriteRes<WriteFMA64, []>; 121def : WriteRes<WriteFDiv32, []>; 122def : WriteRes<WriteFDiv64, []>; 123def : WriteRes<WriteFSqrt32, []>; 124def : WriteRes<WriteFSqrt64, []>; 125 126def : WriteRes<WriteSFB, []>; 127} 128 129// Others 130def : WriteRes<WriteCSR, []>; 131def : WriteRes<WriteNop, []>; 132 133def : InstRW<[WriteIALU], (instrs COPY)>; 134 135//===----------------------------------------------------------------------===// 136// Bypasses (none) 137def : ReadAdvance<ReadJmp, 0>; 138def : ReadAdvance<ReadJalr, 0>; 139def : ReadAdvance<ReadCSR, 0>; 140def : ReadAdvance<ReadStoreData, 0>; 141def : ReadAdvance<ReadMemBase, 0>; 142def : ReadAdvance<ReadIALU, 0>; 143def : ReadAdvance<ReadIALU32, 0>; 144def : ReadAdvance<ReadShiftImm, 0>; 145def : ReadAdvance<ReadShiftImm32, 0>; 146def : ReadAdvance<ReadShiftReg, 0>; 147def : ReadAdvance<ReadShiftReg32, 0>; 148def : ReadAdvance<ReadIDiv, 0>; 149def : ReadAdvance<ReadIDiv32, 0>; 150def : ReadAdvance<ReadIMul, 0>; 151def : ReadAdvance<ReadIMul32, 0>; 152def : ReadAdvance<ReadAtomicWA, 0>; 153def : ReadAdvance<ReadAtomicWD, 0>; 154def : ReadAdvance<ReadAtomicDA, 0>; 155def : ReadAdvance<ReadAtomicDD, 0>; 156def : ReadAdvance<ReadAtomicLDW, 0>; 157def : ReadAdvance<ReadAtomicLDD, 0>; 158def : ReadAdvance<ReadAtomicSTW, 0>; 159def : ReadAdvance<ReadAtomicSTD, 0>; 160def : ReadAdvance<ReadFStoreData, 0>; 161def : ReadAdvance<ReadFMemBase, 0>; 162def : ReadAdvance<ReadFAdd32, 0>; 163def : ReadAdvance<ReadFAdd64, 0>; 164def : ReadAdvance<ReadFMul32, 0>; 165def : ReadAdvance<ReadFMul64, 0>; 166def : ReadAdvance<ReadFMA32, 0>; 167def : ReadAdvance<ReadFMA64, 0>; 168def : ReadAdvance<ReadFDiv32, 0>; 169def : ReadAdvance<ReadFDiv64, 0>; 170def : ReadAdvance<ReadFSqrt32, 0>; 171def : ReadAdvance<ReadFSqrt64, 0>; 172def : ReadAdvance<ReadFCmp32, 0>; 173def : ReadAdvance<ReadFCmp64, 0>; 174def : ReadAdvance<ReadFSGNJ32, 0>; 175def : ReadAdvance<ReadFSGNJ64, 0>; 176def : ReadAdvance<ReadFMinMax32, 0>; 177def : ReadAdvance<ReadFMinMax64, 0>; 178def : ReadAdvance<ReadFCvtF32ToI32, 0>; 179def : ReadAdvance<ReadFCvtF32ToI64, 0>; 180def : ReadAdvance<ReadFCvtF64ToI32, 0>; 181def : ReadAdvance<ReadFCvtF64ToI64, 0>; 182def : ReadAdvance<ReadFCvtI32ToF32, 0>; 183def : ReadAdvance<ReadFCvtI32ToF64, 0>; 184def : ReadAdvance<ReadFCvtI64ToF32, 0>; 185def : ReadAdvance<ReadFCvtI64ToF64, 0>; 186def : ReadAdvance<ReadFCvtF32ToF64, 0>; 187def : ReadAdvance<ReadFCvtF64ToF32, 0>; 188def : ReadAdvance<ReadFMovF32ToI32, 0>; 189def : ReadAdvance<ReadFMovI32ToF32, 0>; 190def : ReadAdvance<ReadFMovF64ToI64, 0>; 191def : ReadAdvance<ReadFMovI64ToF64, 0>; 192def : ReadAdvance<ReadFClass32, 0>; 193def : ReadAdvance<ReadFClass64, 0>; 194def : ReadAdvance<ReadSFBJmp, 0>; 195def : ReadAdvance<ReadSFBALU, 0>; 196 197//===----------------------------------------------------------------------===// 198// Unsupported extensions 199defm : UnsupportedSchedV; 200defm : UnsupportedSchedZba; 201defm : UnsupportedSchedZbb; 202defm : UnsupportedSchedZbc; 203defm : UnsupportedSchedZbs; 204defm : UnsupportedSchedZbkb; 205defm : UnsupportedSchedZbkx; 206defm : UnsupportedSchedZfa; 207defm : UnsupportedSchedZfh; 208} 209