1 //===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISC-V specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "GISel/RISCVCallLowering.h"
15 #include "GISel/RISCVLegalizerInfo.h"
16 #include "GISel/RISCVRegisterBankInfo.h"
17 #include "RISCV.h"
18 #include "RISCVFrameLowering.h"
19 #include "RISCVMacroFusion.h"
20 #include "RISCVTargetMachine.h"
21 #include "llvm/MC/TargetRegistry.h"
22 #include "llvm/Support/ErrorHandling.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "riscv-subtarget"
27 
28 #define GET_SUBTARGETINFO_TARGET_DESC
29 #define GET_SUBTARGETINFO_CTOR
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
33                                           cl::init(true), cl::Hidden);
34 
35 static cl::opt<unsigned> RVVVectorLMULMax(
36     "riscv-v-fixed-length-vector-lmul-max",
37     cl::desc("The maximum LMUL value to use for fixed length vectors. "
38              "Fractional LMUL values are not supported."),
39     cl::init(8), cl::Hidden);
40 
41 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
42     "riscv-disable-using-constant-pool-for-large-ints",
43     cl::desc("Disable using constant pool for large integers."),
44     cl::init(false), cl::Hidden);
45 
46 static cl::opt<unsigned> RISCVMaxBuildIntsCost(
47     "riscv-max-build-ints-cost",
48     cl::desc("The maximum cost used for building integers."), cl::init(0),
49     cl::Hidden);
50 
51 void RISCVSubtarget::anchor() {}
52 
53 RISCVSubtarget &
54 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
55                                                 StringRef TuneCPU, StringRef FS,
56                                                 StringRef ABIName) {
57   // Determine default and user-specified characteristics
58   bool Is64Bit = TT.isArch64Bit();
59   if (CPU.empty() || CPU == "generic")
60     CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
61 
62   if (TuneCPU.empty())
63     TuneCPU = CPU;
64 
65   ParseSubtargetFeatures(CPU, TuneCPU, FS);
66   if (Is64Bit) {
67     XLenVT = MVT::i64;
68     XLen = 64;
69   }
70 
71   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
72   RISCVFeatures::validate(TT, getFeatureBits());
73   return *this;
74 }
75 
76 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
77                                StringRef TuneCPU, StringRef FS,
78                                StringRef ABIName, unsigned RVVVectorBitsMin,
79                                unsigned RVVVectorBitsMax,
80                                const TargetMachine &TM)
81     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
82       RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
83       FrameLowering(
84           initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
85       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
86   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
87   Legalizer.reset(new RISCVLegalizerInfo(*this));
88 
89   auto *RBI = new RISCVRegisterBankInfo(getHwMode());
90   RegBankInfo.reset(RBI);
91   InstSelector.reset(createRISCVInstructionSelector(
92       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
93 }
94 
95 const CallLowering *RISCVSubtarget::getCallLowering() const {
96   return CallLoweringInfo.get();
97 }
98 
99 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
100   return InstSelector.get();
101 }
102 
103 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
104   return Legalizer.get();
105 }
106 
107 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
108   return RegBankInfo.get();
109 }
110 
111 bool RISCVSubtarget::useConstantPoolForLargeInts() const {
112   return !RISCVDisableUsingConstantPoolForLargeInts;
113 }
114 
115 unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
116   // Loading integer from constant pool needs two instructions (the reason why
117   // the minimum cost is 2): an address calculation instruction and a load
118   // instruction. Usually, address calculation and instructions used for
119   // building integers (addi, slli, etc.) can be done in one cycle, so here we
120   // set the default cost to (LoadLatency + 1) if no threshold is provided.
121   return RISCVMaxBuildIntsCost == 0
122              ? getSchedModel().LoadLatency + 1
123              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
124 }
125 
126 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
127   assert(hasVInstructions() &&
128          "Tried to get vector length without Zve or V extension support!");
129 
130   // ZvlLen specifies the minimum required vlen. The upper bound provided by
131   // riscv-v-vector-bits-max should be no less than it.
132   if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
133     report_fatal_error("riscv-v-vector-bits-max specified is lower "
134                        "than the Zvl*b limitation");
135 
136   return RVVVectorBitsMax;
137 }
138 
139 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
140   assert(hasVInstructions() &&
141          "Tried to get vector length without Zve or V extension support!");
142 
143   if (RVVVectorBitsMin == -1U)
144     return ZvlLen;
145 
146   // ZvlLen specifies the minimum required vlen. The lower bound provided by
147   // riscv-v-vector-bits-min should be no less than it.
148   if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
149     report_fatal_error("riscv-v-vector-bits-min specified is lower "
150                        "than the Zvl*b limitation");
151 
152   return RVVVectorBitsMin;
153 }
154 
155 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
156   assert(hasVInstructions() &&
157          "Tried to get vector length without Zve or V extension support!");
158   assert(RVVVectorLMULMax <= 8 &&
159          llvm::has_single_bit<uint32_t>(RVVVectorLMULMax) &&
160          "V extension requires a LMUL to be at most 8 and a power of 2!");
161   return llvm::bit_floor(std::clamp<unsigned>(RVVVectorLMULMax, 1, 8));
162 }
163 
164 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
165   return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
166 }
167 
168 bool RISCVSubtarget::enableSubRegLiveness() const {
169   // FIXME: Enable subregister liveness by default for RVV to better handle
170   // LMUL>1 and segment load/store.
171   return EnableSubRegLiveness;
172 }
173 
174 void RISCVSubtarget::getPostRAMutations(
175     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
176   Mutations.push_back(createRISCVMacroFusionDAGMutation());
177 }
178