1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "riscv-subtarget"
25 
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "RISCVGenSubtargetInfo.inc"
29 
30 void RISCVSubtarget::anchor() {}
31 
32 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
33     const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
34   // Determine default and user-specified characteristics
35   bool Is64Bit = TT.isArch64Bit();
36   std::string CPUName = std::string(CPU);
37   std::string TuneCPUName = std::string(TuneCPU);
38   if (CPUName.empty())
39     CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
40   if (TuneCPUName.empty())
41     TuneCPUName = CPUName;
42   ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
43   if (Is64Bit) {
44     XLenVT = MVT::i64;
45     XLen = 64;
46   }
47 
48   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
49   RISCVFeatures::validate(TT, getFeatureBits());
50   return *this;
51 }
52 
53 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
54                                StringRef TuneCPU, StringRef FS,
55                                StringRef ABIName, const TargetMachine &TM)
56     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
57       UserReservedRegister(RISCV::NUM_TARGET_REGS),
58       FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
59       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
60   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
61   Legalizer.reset(new RISCVLegalizerInfo(*this));
62 
63   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
64   RegBankInfo.reset(RBI);
65   InstSelector.reset(createRISCVInstructionSelector(
66       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
67 }
68 
69 const CallLowering *RISCVSubtarget::getCallLowering() const {
70   return CallLoweringInfo.get();
71 }
72 
73 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
74   return InstSelector.get();
75 }
76 
77 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
78   return Legalizer.get();
79 }
80 
81 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
82   return RegBankInfo.get();
83 }
84