1 //===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISC-V specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
16 #include "MCTargetDesc/RISCVBaseInfo.h"
17 #include "RISCVFrameLowering.h"
18 #include "RISCVISelLowering.h"
19 #include "RISCVInstrInfo.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23 #include "llvm/CodeGen/RegisterBankInfo.h"
24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/Target/TargetMachine.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
35 class RISCVSubtarget : public RISCVGenSubtargetInfo {
36 public:
37   enum RISCVProcFamilyEnum : uint8_t {
38     Others,
39     SiFive7,
40   };
41 
42 private:
43   virtual void anchor();
44 
45   RISCVProcFamilyEnum RISCVProcFamily = Others;
46 
47 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
48   bool ATTRIBUTE = DEFAULT;
49 #include "RISCVGenSubtargetInfo.inc"
50 
51   unsigned XLen = 32;
52   unsigned ZvlLen = 0;
53   MVT XLenVT = MVT::i32;
54   unsigned RVVVectorBitsMin;
55   unsigned RVVVectorBitsMax;
56   uint8_t MaxInterleaveFactor = 2;
57   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
58   std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
59   Align PrefFunctionAlignment;
60   Align PrefLoopAlignment;
61 
62   RISCVFrameLowering FrameLowering;
63   RISCVInstrInfo InstrInfo;
64   RISCVRegisterInfo RegInfo;
65   RISCVTargetLowering TLInfo;
66   SelectionDAGTargetInfo TSInfo;
67 
68   /// Initializes using the passed in CPU and feature strings so that we can
69   /// use initializer lists for subtarget initialization.
70   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
71                                                   StringRef CPU,
72                                                   StringRef TuneCPU,
73                                                   StringRef FS,
74                                                   StringRef ABIName);
75 
76 public:
77   // Initializes the data members to match that of the specified triple.
78   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
79                  StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
80                  unsigned RVVVectorLMULMax, const TargetMachine &TM);
81 
82   // Parses features string setting specified subtarget options. The
83   // definition of this function is auto-generated by tblgen.
84   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
85 
86   const RISCVFrameLowering *getFrameLowering() const override {
87     return &FrameLowering;
88   }
89   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
90   const RISCVRegisterInfo *getRegisterInfo() const override {
91     return &RegInfo;
92   }
93   const RISCVTargetLowering *getTargetLowering() const override {
94     return &TLInfo;
95   }
96   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
97     return &TSInfo;
98   }
99   bool enableMachineScheduler() const override { return true; }
100 
101   Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
102   Align getPrefLoopAlignment() const { return PrefLoopAlignment; }
103 
104   /// Returns RISC-V processor family.
105   /// Avoid this function! CPU specifics should be kept local to this class
106   /// and preferably modeled with SubtargetFeatures or properties in
107   /// initializeProperties().
108   RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
109 
110 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
111   bool GETTER() const { return ATTRIBUTE; }
112 #include "RISCVGenSubtargetInfo.inc"
113 
114   bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
115   bool hasStdExtZvl() const { return ZvlLen != 0; }
116   bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
117   bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
118   bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
119   bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
120   bool hasStdExtZhinxOrZhinxmin() const {
121     return HasStdExtZhinx || HasStdExtZhinxmin;
122   }
123   bool hasStdExtZfhOrZfhminOrZhinxOrZhinxmin() const {
124     return hasStdExtZfhOrZfhmin() || hasStdExtZhinxOrZhinxmin();
125   }
126   bool hasHalfFPLoadStoreMove() const {
127     return HasStdExtZfh || HasStdExtZfhmin || HasStdExtZfbfmin ||
128            HasStdExtZvfbfwma;
129   }
130   bool is64Bit() const { return IsRV64; }
131   MVT getXLenVT() const { return XLenVT; }
132   unsigned getXLen() const { return XLen; }
133   unsigned getFLen() const {
134     if (HasStdExtD)
135       return 64;
136 
137     if (HasStdExtF)
138       return 32;
139 
140     return 0;
141   }
142   unsigned getELEN() const {
143     assert(hasVInstructions() && "Expected V extension");
144     return hasVInstructionsI64() ? 64 : 32;
145   }
146   unsigned getRealMinVLen() const {
147     unsigned VLen = getMinRVVVectorSizeInBits();
148     return VLen == 0 ? ZvlLen : VLen;
149   }
150   unsigned getRealMaxVLen() const {
151     unsigned VLen = getMaxRVVVectorSizeInBits();
152     return VLen == 0 ? 65536 : VLen;
153   }
154   RISCVABI::ABI getTargetABI() const { return TargetABI; }
155   bool isSoftFPABI() const {
156     return TargetABI == RISCVABI::ABI_LP64 ||
157            TargetABI == RISCVABI::ABI_ILP32 ||
158            TargetABI == RISCVABI::ABI_ILP32E;
159   }
160   bool isRegisterReservedByUser(Register i) const {
161     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
162     return UserReservedRegister[i];
163   }
164 
165   bool hasMacroFusion() const { return hasLUIADDIFusion(); }
166 
167   // Vector codegen related methods.
168   bool hasVInstructions() const { return HasStdExtZve32x; }
169   bool hasVInstructionsI64() const { return HasStdExtZve64x; }
170   bool hasVInstructionsF16() const { return HasStdExtZvfh; }
171   // FIXME: Consider Zfinx in the future
172   bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
173   // FIXME: Consider Zdinx in the future
174   bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
175   // F16 and F64 both require F32.
176   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
177   bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
178   unsigned getMaxInterleaveFactor() const {
179     return hasVInstructions() ? MaxInterleaveFactor : 1;
180   }
181 
182   // Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
183   // vector hardware implementation which may be less than VLEN.
184   unsigned getDLenFactor() const {
185     if (DLenFactor2)
186       return 2;
187     return 1;
188   }
189 
190 protected:
191   // GlobalISel related APIs.
192   std::unique_ptr<CallLowering> CallLoweringInfo;
193   std::unique_ptr<InstructionSelector> InstSelector;
194   std::unique_ptr<LegalizerInfo> Legalizer;
195   std::unique_ptr<RegisterBankInfo> RegBankInfo;
196 
197   // Return the known range for the bit length of RVV data registers as set
198   // at the command line. A value of 0 means nothing is known about that particular
199   // limit beyond what's implied by the architecture.
200   // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
201   unsigned getMaxRVVVectorSizeInBits() const;
202   unsigned getMinRVVVectorSizeInBits() const;
203 
204 public:
205   const CallLowering *getCallLowering() const override;
206   InstructionSelector *getInstructionSelector() const override;
207   const LegalizerInfo *getLegalizerInfo() const override;
208   const RegisterBankInfo *getRegBankInfo() const override;
209 
210   bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
211 
212   bool useConstantPoolForLargeInts() const;
213 
214   // Maximum cost used for building integers, integers will be put into constant
215   // pool if exceeded.
216   unsigned getMaxBuildIntsCost() const;
217 
218   unsigned getMaxLMULForFixedLengthVectors() const;
219   bool useRVVForFixedLengthVectors() const;
220 
221   bool enableSubRegLiveness() const override;
222 
223   void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
224                               &Mutations) const override;
225 };
226 } // End llvm namespace
227 
228 #endif
229