1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
14 #include "MCTargetDesc/RISCVBaseInfo.h"
15 #include "RISCV.h"
16 #include "RISCVTargetObjectFile.h"
17 #include "RISCVTargetTransformInfo.h"
18 #include "TargetInfo/RISCVTargetInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
22 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
23 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
24 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/InitializePasses.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Target/TargetOptions.h"
33 using namespace llvm;
34 
35 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
36   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
37   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
38   auto *PR = PassRegistry::getPassRegistry();
39   initializeGlobalISel(*PR);
40   initializeRISCVMergeBaseOffsetOptPass(*PR);
41   initializeRISCVExpandPseudoPass(*PR);
42   initializeRISCVCleanupVSETVLIPass(*PR);
43 }
44 
45 static StringRef computeDataLayout(const Triple &TT) {
46   if (TT.isArch64Bit())
47     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
48   assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
49   return "e-m:e-p:32:32-i64:64-n32-S128";
50 }
51 
52 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
53                                            Optional<Reloc::Model> RM) {
54   if (!RM.hasValue())
55     return Reloc::Static;
56   return *RM;
57 }
58 
59 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
60                                        StringRef CPU, StringRef FS,
61                                        const TargetOptions &Options,
62                                        Optional<Reloc::Model> RM,
63                                        Optional<CodeModel::Model> CM,
64                                        CodeGenOpt::Level OL, bool JIT)
65     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
66                         getEffectiveRelocModel(TT, RM),
67                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
68       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
69   initAsmInfo();
70 
71   // RISC-V supports the MachineOutliner.
72   setMachineOutliner(true);
73 }
74 
75 const RISCVSubtarget *
76 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
77   Attribute CPUAttr = F.getFnAttribute("target-cpu");
78   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
79   Attribute FSAttr = F.getFnAttribute("target-features");
80 
81   std::string CPU =
82       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
83   std::string TuneCPU =
84       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
85   std::string FS =
86       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
87   std::string Key = CPU + TuneCPU + FS;
88   auto &I = SubtargetMap[Key];
89   if (!I) {
90     // This needs to be done before we create a new subtarget since any
91     // creation will depend on the TM and the code generation flags on the
92     // function that reside in TargetOptions.
93     resetTargetOptions(F);
94     auto ABIName = Options.MCOptions.getABIName();
95     if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
96             F.getParent()->getModuleFlag("target-abi"))) {
97       auto TargetABI = RISCVABI::getTargetABI(ABIName);
98       if (TargetABI != RISCVABI::ABI_Unknown &&
99           ModuleTargetABI->getString() != ABIName) {
100         report_fatal_error("-target-abi option != target-abi module flag");
101       }
102       ABIName = ModuleTargetABI->getString();
103     }
104     I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
105   }
106   return I.get();
107 }
108 
109 TargetTransformInfo
110 RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
111   return TargetTransformInfo(RISCVTTIImpl(this, F));
112 }
113 
114 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
115 // for all memory accesses, so it is reasonable to assume that an
116 // implementation has no-op address space casts. If an implementation makes a
117 // change to this, they can override it here.
118 bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
119                                              unsigned DstAS) const {
120   return true;
121 }
122 
123 namespace {
124 class RISCVPassConfig : public TargetPassConfig {
125 public:
126   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
127       : TargetPassConfig(TM, PM) {}
128 
129   RISCVTargetMachine &getRISCVTargetMachine() const {
130     return getTM<RISCVTargetMachine>();
131   }
132 
133   void addIRPasses() override;
134   bool addInstSelector() override;
135   bool addIRTranslator() override;
136   bool addLegalizeMachineIR() override;
137   bool addRegBankSelect() override;
138   bool addGlobalInstructionSelect() override;
139   void addPreEmitPass() override;
140   void addPreEmitPass2() override;
141   void addPreSched2() override;
142   void addPreRegAlloc() override;
143 };
144 } // namespace
145 
146 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
147   return new RISCVPassConfig(*this, PM);
148 }
149 
150 void RISCVPassConfig::addIRPasses() {
151   addPass(createAtomicExpandPass());
152   TargetPassConfig::addIRPasses();
153 }
154 
155 bool RISCVPassConfig::addInstSelector() {
156   addPass(createRISCVISelDag(getRISCVTargetMachine()));
157 
158   return false;
159 }
160 
161 bool RISCVPassConfig::addIRTranslator() {
162   addPass(new IRTranslator(getOptLevel()));
163   return false;
164 }
165 
166 bool RISCVPassConfig::addLegalizeMachineIR() {
167   addPass(new Legalizer());
168   return false;
169 }
170 
171 bool RISCVPassConfig::addRegBankSelect() {
172   addPass(new RegBankSelect());
173   return false;
174 }
175 
176 bool RISCVPassConfig::addGlobalInstructionSelect() {
177   addPass(new InstructionSelect());
178   return false;
179 }
180 
181 void RISCVPassConfig::addPreSched2() {}
182 
183 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
184 
185 void RISCVPassConfig::addPreEmitPass2() {
186   addPass(createRISCVExpandPseudoPass());
187   // Schedule the expansion of AMOs at the last possible moment, avoiding the
188   // possibility for other passes to break the requirements for forward
189   // progress in the LR/SC block.
190   addPass(createRISCVExpandAtomicPseudoPass());
191 }
192 
193 void RISCVPassConfig::addPreRegAlloc() {
194   if (TM->getOptLevel() != CodeGenOpt::None) {
195     addPass(createRISCVMergeBaseOffsetOptPass());
196     addPass(createRISCVCleanupVSETVLIPass());
197   }
198 }
199