1 //===-- SPIRVAsmBackend.cpp - SPIR-V Assembler Backend ---------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/SPIRVMCTargetDesc.h"
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "llvm/MC/MCAssembler.h"
12 #include "llvm/MC/MCObjectWriter.h"
13 #include "llvm/Support/EndianStream.h"
14
15 using namespace llvm;
16
17 namespace {
18
19 class SPIRVAsmBackend : public MCAsmBackend {
20 public:
SPIRVAsmBackend(llvm::endianness Endian)21 SPIRVAsmBackend(llvm::endianness Endian) : MCAsmBackend(Endian) {}
22
applyFixup(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target,MutableArrayRef<char> Data,uint64_t Value,bool IsResolved,const MCSubtargetInfo * STI) const23 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
24 const MCValue &Target, MutableArrayRef<char> Data,
25 uint64_t Value, bool IsResolved,
26 const MCSubtargetInfo *STI) const override {}
27
28 std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const29 createObjectTargetWriter() const override {
30 return createSPIRVObjectTargetWriter();
31 }
32
33 // No instruction requires relaxation.
fixupNeedsRelaxation(const MCFixup & Fixup,uint64_t Value,const MCRelaxableFragment * DF,const MCAsmLayout & Layout) const34 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
35 const MCRelaxableFragment *DF,
36 const MCAsmLayout &Layout) const override {
37 return false;
38 }
39
getNumFixupKinds() const40 unsigned getNumFixupKinds() const override { return 1; }
41
mayNeedRelaxation(const MCInst & Inst,const MCSubtargetInfo & STI) const42 bool mayNeedRelaxation(const MCInst &Inst,
43 const MCSubtargetInfo &STI) const override {
44 return false;
45 }
46
relaxInstruction(MCInst & Inst,const MCSubtargetInfo & STI) const47 void relaxInstruction(MCInst &Inst,
48 const MCSubtargetInfo &STI) const override {}
49
writeNopData(raw_ostream & OS,uint64_t Count,const MCSubtargetInfo * STI) const50 bool writeNopData(raw_ostream &OS, uint64_t Count,
51 const MCSubtargetInfo *STI) const override {
52 return false;
53 }
54 };
55
56 } // end anonymous namespace
57
createSPIRVAsmBackend(const Target & T,const MCSubtargetInfo & STI,const MCRegisterInfo & MRI,const MCTargetOptions &)58 MCAsmBackend *llvm::createSPIRVAsmBackend(const Target &T,
59 const MCSubtargetInfo &STI,
60 const MCRegisterInfo &MRI,
61 const MCTargetOptions &) {
62 return new SPIRVAsmBackend(llvm::endianness::little);
63 }
64