1//===-- SPIRVInstrFormats.td - SPIR-V Instruction Formats --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9def StringImm: Operand<i32>{
10  let PrintMethod="printStringImm";
11}
12
13class Op<bits<16> Opcode, dag outs, dag ins, string asmstr, list<dag> pattern = []>
14  : Instruction {
15  field bits<16> Inst;
16
17  let Inst = Opcode;
18
19  let Namespace = "SPIRV";
20  let DecoderNamespace = "SPIRV";
21
22  dag OutOperandList = outs;
23  dag InOperandList = ins;
24  let AsmString = asmstr;
25  let Pattern = pattern;
26}
27
28// Pseudo instructions
29class Pseudo<dag outs, dag ins> : Op<0, outs, ins, ""> {
30  let isPseudo = 1;
31}
32