1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SparcMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/SparcFixupKinds.h"
14 #include "SparcMCExpr.h"
15 #include "SparcMCTargetDesc.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectFileInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/Endian.h"
31 #include "llvm/Support/EndianStream.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/TargetParser/SubtargetFeature.h"
35 #include <cassert>
36 #include <cstdint>
37
38 using namespace llvm;
39
40 #define DEBUG_TYPE "mccodeemitter"
41
42 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43
44 namespace {
45
46 class SparcMCCodeEmitter : public MCCodeEmitter {
47 MCContext &Ctx;
48
49 public:
SparcMCCodeEmitter(const MCInstrInfo &,MCContext & ctx)50 SparcMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
51 : Ctx(ctx) {}
52 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
53 SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
54 ~SparcMCCodeEmitter() override = default;
55
56 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
57 SmallVectorImpl<MCFixup> &Fixups,
58 const MCSubtargetInfo &STI) const override;
59
60 // getBinaryCodeForInstr - TableGen'erated function for getting the
61 // binary encoding for an instruction.
62 uint64_t getBinaryCodeForInstr(const MCInst &MI,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &STI) const;
65
66 /// getMachineOpValue - Return binary encoding of operand. If the machine
67 /// operand requires relocation, record the relocation and return zero.
68 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
69 SmallVectorImpl<MCFixup> &Fixups,
70 const MCSubtargetInfo &STI) const;
71 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
72 SmallVectorImpl<MCFixup> &Fixups,
73 const MCSubtargetInfo &STI) const;
74 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
77 unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
78 SmallVectorImpl<MCFixup> &Fixups,
79 const MCSubtargetInfo &STI) const;
80 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
81 SmallVectorImpl<MCFixup> &Fixups,
82 const MCSubtargetInfo &STI) const;
83 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
84 SmallVectorImpl<MCFixup> &Fixups,
85 const MCSubtargetInfo &STI) const;
86 };
87
88 } // end anonymous namespace
89
encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const90 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI,
91 SmallVectorImpl<char> &CB,
92 SmallVectorImpl<MCFixup> &Fixups,
93 const MCSubtargetInfo &STI) const {
94 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
95 support::endian::write(CB, Bits,
96 Ctx.getAsmInfo()->isLittleEndian()
97 ? llvm::endianness::little
98 : llvm::endianness::big);
99
100 // Some instructions have phantom operands that only contribute a fixup entry.
101 unsigned SymOpNo = 0;
102 switch (MI.getOpcode()) {
103 default: break;
104 case SP::TLS_CALL: SymOpNo = 1; break;
105 case SP::GDOP_LDrr:
106 case SP::GDOP_LDXrr:
107 case SP::TLS_ADDrr:
108 case SP::TLS_LDrr:
109 case SP::TLS_LDXrr: SymOpNo = 3; break;
110 }
111 if (SymOpNo != 0) {
112 const MCOperand &MO = MI.getOperand(SymOpNo);
113 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
114 assert(op == 0 && "Unexpected operand value!");
115 (void)op; // suppress warning.
116 }
117
118 ++MCNumEmitted; // Keep track of the # of mi's emitted.
119 }
120
121 unsigned SparcMCCodeEmitter::
getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const122 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
123 SmallVectorImpl<MCFixup> &Fixups,
124 const MCSubtargetInfo &STI) const {
125 if (MO.isReg())
126 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
127
128 if (MO.isImm())
129 return MO.getImm();
130
131 assert(MO.isExpr());
132 const MCExpr *Expr = MO.getExpr();
133 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
134 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
135 Fixups.push_back(MCFixup::create(0, Expr, Kind));
136 return 0;
137 }
138
139 int64_t Res;
140 if (Expr->evaluateAsAbsolute(Res))
141 return Res;
142
143 llvm_unreachable("Unhandled expression!");
144 return 0;
145 }
146
147 unsigned
getSImm13OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const148 SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const {
151 const MCOperand &MO = MI.getOperand(OpNo);
152
153 if (MO.isImm())
154 return MO.getImm();
155
156 assert(MO.isExpr() &&
157 "getSImm13OpValue expects only expressions or an immediate");
158
159 const MCExpr *Expr = MO.getExpr();
160
161 // Constant value, no fixup is needed
162 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
163 return CE->getValue();
164
165 MCFixupKind Kind;
166 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
167 Kind = MCFixupKind(SExpr->getFixupKind());
168 } else {
169 bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
170 Kind = IsPic ? MCFixupKind(Sparc::fixup_sparc_got13)
171 : MCFixupKind(Sparc::fixup_sparc_13);
172 }
173
174 Fixups.push_back(MCFixup::create(0, Expr, Kind));
175 return 0;
176 }
177
178 unsigned SparcMCCodeEmitter::
getCallTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const179 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
180 SmallVectorImpl<MCFixup> &Fixups,
181 const MCSubtargetInfo &STI) const {
182 const MCOperand &MO = MI.getOperand(OpNo);
183 const MCExpr *Expr = MO.getExpr();
184 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
185
186 if (MI.getOpcode() == SP::TLS_CALL) {
187 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
188 // encodeInstruction.
189 #ifndef NDEBUG
190 // Verify that the callee is actually __tls_get_addr.
191 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
192 "Unexpected expression in TLS_CALL");
193 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
194 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
195 "Unexpected function for TLS_CALL");
196 #endif
197 return 0;
198 }
199
200 MCFixupKind Kind = MCFixupKind(SExpr->getFixupKind());
201 Fixups.push_back(MCFixup::create(0, Expr, Kind));
202 return 0;
203 }
204
205 unsigned SparcMCCodeEmitter::
getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const206 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
207 SmallVectorImpl<MCFixup> &Fixups,
208 const MCSubtargetInfo &STI) const {
209 const MCOperand &MO = MI.getOperand(OpNo);
210 if (MO.isReg() || MO.isImm())
211 return getMachineOpValue(MI, MO, Fixups, STI);
212
213 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
214 (MCFixupKind)Sparc::fixup_sparc_br22));
215 return 0;
216 }
217
218 unsigned SparcMCCodeEmitter::
getBranchPredTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const219 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
220 SmallVectorImpl<MCFixup> &Fixups,
221 const MCSubtargetInfo &STI) const {
222 const MCOperand &MO = MI.getOperand(OpNo);
223 if (MO.isReg() || MO.isImm())
224 return getMachineOpValue(MI, MO, Fixups, STI);
225
226 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
227 (MCFixupKind)Sparc::fixup_sparc_br19));
228 return 0;
229 }
230
231 unsigned SparcMCCodeEmitter::
getBranchOnRegTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const232 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
233 SmallVectorImpl<MCFixup> &Fixups,
234 const MCSubtargetInfo &STI) const {
235 const MCOperand &MO = MI.getOperand(OpNo);
236 if (MO.isReg() || MO.isImm())
237 return getMachineOpValue(MI, MO, Fixups, STI);
238
239 Fixups.push_back(
240 MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br16));
241
242 return 0;
243 }
244
245 #include "SparcGenMCCodeEmitter.inc"
246
createSparcMCCodeEmitter(const MCInstrInfo & MCII,MCContext & Ctx)247 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
248 MCContext &Ctx) {
249 return new SparcMCCodeEmitter(MCII, Ctx);
250 }
251