1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Sparc implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SparcFrameLowering.h"
14 #include "SparcInstrInfo.h"
15 #include "SparcMachineFunctionInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Target/TargetOptions.h"
26 
27 using namespace llvm;
28 
29 static cl::opt<bool>
30 DisableLeafProc("disable-sparc-leaf-proc",
31                 cl::init(false),
32                 cl::desc("Disable Sparc leaf procedure optimization."),
33                 cl::Hidden);
34 
35 SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
36     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
37                           ST.is64Bit() ? Align(16) : Align(8), 0,
38                           ST.is64Bit() ? Align(16) : Align(8)) {}
39 
40 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
41                                           MachineBasicBlock &MBB,
42                                           MachineBasicBlock::iterator MBBI,
43                                           int NumBytes,
44                                           unsigned ADDrr,
45                                           unsigned ADDri) const {
46 
47   DebugLoc dl;
48   const SparcInstrInfo &TII =
49       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
50 
51   if (NumBytes >= -4096 && NumBytes < 4096) {
52     BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53       .addReg(SP::O6).addImm(NumBytes);
54     return;
55   }
56 
57   // Emit this the hard way.  This clobbers G1 which we always know is
58   // available here.
59   if (NumBytes >= 0) {
60     // Emit nonnegative numbers with sethi + or.
61     // sethi %hi(NumBytes), %g1
62     // or %g1, %lo(NumBytes), %g1
63     // add %sp, %g1, %sp
64     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
65       .addImm(HI22(NumBytes));
66     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67       .addReg(SP::G1).addImm(LO10(NumBytes));
68     BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69       .addReg(SP::O6).addReg(SP::G1);
70     return ;
71   }
72 
73   // Emit negative numbers with sethi + xor.
74   // sethi %hix(NumBytes), %g1
75   // xor %g1, %lox(NumBytes), %g1
76   // add %sp, %g1, %sp
77   BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
78     .addImm(HIX22(NumBytes));
79   BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80     .addReg(SP::G1).addImm(LOX10(NumBytes));
81   BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82     .addReg(SP::O6).addReg(SP::G1);
83 }
84 
85 void SparcFrameLowering::emitPrologue(MachineFunction &MF,
86                                       MachineBasicBlock &MBB) const {
87   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
88 
89   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
90   MachineFrameInfo &MFI = MF.getFrameInfo();
91   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
92   const SparcInstrInfo &TII =
93       *static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo());
94   const SparcRegisterInfo &RegInfo =
95       *static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo());
96   MachineBasicBlock::iterator MBBI = MBB.begin();
97   // Debug location must be unknown since the first debug location is used
98   // to determine the end of the prologue.
99   DebugLoc dl;
100   bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF);
101 
102   if (NeedsStackRealignment && !RegInfo.canRealignStack(MF))
103     report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
104                        "stack re-alignment, but LLVM couldn't handle it "
105                        "(probably because it has a dynamic alloca).");
106 
107   // Get the number of bytes to allocate from the FrameInfo
108   int NumBytes = (int) MFI.getStackSize();
109 
110   unsigned SAVEri = SP::SAVEri;
111   unsigned SAVErr = SP::SAVErr;
112   if (FuncInfo->isLeafProc()) {
113     if (NumBytes == 0)
114       return;
115     SAVEri = SP::ADDri;
116     SAVErr = SP::ADDrr;
117   }
118 
119   // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
120   // (128 in v9) area in the user's stack, starting at %sp. Thus, the
121   // first part of the stack that can actually be used is located at
122   // %sp + 92.
123   //
124   // We therefore need to add that offset to the total stack size
125   // after all the stack objects are placed by
126   // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
127   // aligned *after* the extra size is added, we need to disable
128   // calculateFrameObjectOffsets's built-in stack alignment, by having
129   // targetHandlesStackFrameRounding return true.
130 
131 
132   // Add the extra call frame stack size, if needed. (This is the same
133   // code as in PrologEpilogInserter, but also gets disabled by
134   // targetHandlesStackFrameRounding)
135   if (MFI.adjustsStack() && hasReservedCallFrame(MF))
136     NumBytes += MFI.getMaxCallFrameSize();
137 
138   // Adds the SPARC subtarget-specific spill area to the stack
139   // size. Also ensures target-required alignment.
140   NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
141 
142   // Finally, ensure that the size is sufficiently aligned for the
143   // data on the stack.
144   NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
145 
146   // Update stack size with corrected value.
147   MFI.setStackSize(NumBytes);
148 
149   emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
150 
151   unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
152 
153   // Emit ".cfi_def_cfa_register 30".
154   unsigned CFIIndex =
155       MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
156   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
157       .addCFIIndex(CFIIndex);
158 
159   // Emit ".cfi_window_save".
160   CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
161   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
162       .addCFIIndex(CFIIndex);
163 
164   unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
165   unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
166   // Emit ".cfi_register 15, 31".
167   CFIIndex = MF.addFrameInst(
168       MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
169   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
170       .addCFIIndex(CFIIndex);
171 
172   if (NeedsStackRealignment) {
173     int64_t Bias = Subtarget.getStackPointerBias();
174     unsigned regUnbiased;
175     if (Bias) {
176       // This clobbers G1 which we always know is available here.
177       regUnbiased = SP::G1;
178       // add %o6, BIAS, %g1
179       BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
180         .addReg(SP::O6).addImm(Bias);
181     } else
182       regUnbiased = SP::O6;
183 
184     // andn %regUnbiased, MaxAlign-1, %regUnbiased
185     Align MaxAlign = MFI.getMaxAlign();
186     BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
187         .addReg(regUnbiased)
188         .addImm(MaxAlign.value() - 1U);
189 
190     if (Bias) {
191       // add %g1, -BIAS, %o6
192       BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
193         .addReg(regUnbiased).addImm(-Bias);
194     }
195   }
196 }
197 
198 MachineBasicBlock::iterator SparcFrameLowering::
199 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
200                               MachineBasicBlock::iterator I) const {
201   if (!hasReservedCallFrame(MF)) {
202     MachineInstr &MI = *I;
203     int Size = MI.getOperand(0).getImm();
204     if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
205       Size = -Size;
206 
207     if (Size)
208       emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
209   }
210   return MBB.erase(I);
211 }
212 
213 
214 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
215                                   MachineBasicBlock &MBB) const {
216   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
217   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
218   const SparcInstrInfo &TII =
219       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
220   DebugLoc dl = MBBI->getDebugLoc();
221   assert(MBBI->getOpcode() == SP::RETL &&
222          "Can only put epilog before 'retl' instruction!");
223   if (!FuncInfo->isLeafProc()) {
224     BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
225       .addReg(SP::G0);
226     return;
227   }
228   MachineFrameInfo &MFI = MF.getFrameInfo();
229 
230   int NumBytes = (int) MFI.getStackSize();
231   if (NumBytes == 0)
232     return;
233 
234   emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
235 }
236 
237 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
238   // Reserve call frame if there are no variable sized objects on the stack.
239   return !MF.getFrameInfo().hasVarSizedObjects();
240 }
241 
242 // hasFP - Return true if the specified function should have a dedicated frame
243 // pointer register.  This is true if the function has variable sized allocas or
244 // if frame pointer elimination is disabled.
245 bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
246   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
247 
248   const MachineFrameInfo &MFI = MF.getFrameInfo();
249   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
250          RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
251          MFI.isFrameAddressTaken();
252 }
253 
254 StackOffset
255 SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
256                                            Register &FrameReg) const {
257   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
258   const MachineFrameInfo &MFI = MF.getFrameInfo();
259   const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
260   const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
261   bool isFixed = MFI.isFixedObjectIndex(FI);
262 
263   // Addressable stack objects are accessed using neg. offsets from
264   // %fp, or positive offsets from %sp.
265   bool UseFP;
266 
267   // Sparc uses FP-based references in general, even when "hasFP" is
268   // false. That function is rather a misnomer, because %fp is
269   // actually always available, unless isLeafProc.
270   if (FuncInfo->isLeafProc()) {
271     // If there's a leaf proc, all offsets need to be %sp-based,
272     // because we haven't caused %fp to actually point to our frame.
273     UseFP = false;
274   } else if (isFixed) {
275     // Otherwise, argument access should always use %fp.
276     UseFP = true;
277   } else if (RegInfo->hasStackRealignment(MF)) {
278     // If there is dynamic stack realignment, all local object
279     // references need to be via %sp, to take account of the
280     // re-alignment.
281     UseFP = false;
282   } else {
283     // Finally, default to using %fp.
284     UseFP = true;
285   }
286 
287   int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) +
288       Subtarget.getStackPointerBias();
289 
290   if (UseFP) {
291     FrameReg = RegInfo->getFrameRegister(MF);
292     return StackOffset::getFixed(FrameOffset);
293   } else {
294     FrameReg = SP::O6; // %sp
295     return StackOffset::getFixed(FrameOffset + MF.getFrameInfo().getStackSize());
296   }
297 }
298 
299 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
300 {
301 
302   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
303     if (MRI->isPhysRegUsed(reg))
304       return false;
305 
306   for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
307     if (MRI->isPhysRegUsed(reg))
308       return false;
309 
310   return true;
311 }
312 
313 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
314 {
315 
316   MachineRegisterInfo &MRI = MF.getRegInfo();
317   MachineFrameInfo    &MFI = MF.getFrameInfo();
318 
319   return !(MFI.hasCalls()                  // has calls
320            || MRI.isPhysRegUsed(SP::L0)    // Too many registers needed
321            || MRI.isPhysRegUsed(SP::O6)    // %sp is used
322            || hasFP(MF));                  // need %fp
323 }
324 
325 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
326   MachineRegisterInfo &MRI = MF.getRegInfo();
327   // Remap %i[0-7] to %o[0-7].
328   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
329     if (!MRI.isPhysRegUsed(reg))
330       continue;
331 
332     unsigned mapped_reg = reg - SP::I0 + SP::O0;
333 
334     // Replace I register with O register.
335     MRI.replaceRegWith(reg, mapped_reg);
336 
337     // Also replace register pair super-registers.
338     if ((reg - SP::I0) % 2 == 0) {
339       unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
340       unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
341       MRI.replaceRegWith(preg, mapped_preg);
342     }
343   }
344 
345   // Rewrite MBB's Live-ins.
346   for (MachineBasicBlock &MBB : MF) {
347     for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
348       if (!MBB.isLiveIn(reg))
349         continue;
350       MBB.removeLiveIn(reg);
351       MBB.addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
352     }
353     for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
354       if (!MBB.isLiveIn(reg))
355         continue;
356       MBB.removeLiveIn(reg);
357       MBB.addLiveIn(reg - SP::I0 + SP::O0);
358     }
359   }
360 
361   assert(verifyLeafProcRegUse(&MRI));
362 #ifdef EXPENSIVE_CHECKS
363   MF.verify(0, "After LeafProc Remapping");
364 #endif
365 }
366 
367 void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
368                                               BitVector &SavedRegs,
369                                               RegScavenger *RS) const {
370   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
371   if (!DisableLeafProc && isLeafProc(MF)) {
372     SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
373     MFI->setLeafProc(true);
374 
375     remapRegsForLeafProc(MF);
376   }
377 
378 }
379