1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that Sparc uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 15 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 16 17 #include "Sparc.h" 18 #include "llvm/CodeGen/TargetLowering.h" 19 20 namespace llvm { 21 class SparcSubtarget; 22 23 namespace SPISD { 24 enum NodeType : unsigned { 25 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 CMPICC, // Compare two GPR operands, set icc+xcc. 27 CMPFCC, // Compare two FP operands, set fcc. 28 BRICC, // Branch to dest on icc condition 29 BRXCC, // Branch to dest on xcc condition (64-bit only). 30 BRFCC, // Branch to dest on fcc condition 31 SELECT_ICC, // Select between two values using the current ICC flags. 32 SELECT_XCC, // Select between two values using the current XCC flags. 33 SELECT_FCC, // Select between two values using the current FCC flags. 34 35 Hi, Lo, // Hi/Lo operations, typically on a global address. 36 37 FTOI, // FP to Int within a FP register. 38 ITOF, // Int to FP within a FP register. 39 FTOX, // FP to Int64 within a FP register. 40 XTOF, // Int64 to FP within a FP register. 41 42 CALL, // A call instruction. 43 RET_FLAG, // Return with a flag operand. 44 GLOBAL_BASE_REG, // Global base reg for PIC. 45 FLUSHW, // FLUSH register windows to stack. 46 47 TAIL_CALL, // Tail call 48 49 TLS_ADD, // For Thread Local Storage (TLS). 50 TLS_LD, 51 TLS_CALL, 52 53 LOAD_GDOP, // Load operation w/ gdop relocation. 54 }; 55 } 56 57 class SparcTargetLowering : public TargetLowering { 58 const SparcSubtarget *Subtarget; 59 public: 60 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI); 61 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 62 63 bool useSoftFloat() const override; 64 65 /// computeKnownBitsForTargetNode - Determine which of the bits specified 66 /// in Mask are known to be either zero or one and return them in the 67 /// KnownZero/KnownOne bitsets. 68 void computeKnownBitsForTargetNode(const SDValue Op, 69 KnownBits &Known, 70 const APInt &DemandedElts, 71 const SelectionDAG &DAG, 72 unsigned Depth = 0) const override; 73 74 MachineBasicBlock * 75 EmitInstrWithCustomInserter(MachineInstr &MI, 76 MachineBasicBlock *MBB) const override; 77 78 const char *getTargetNodeName(unsigned Opcode) const override; 79 80 ConstraintType getConstraintType(StringRef Constraint) const override; 81 ConstraintWeight 82 getSingleConstraintMatchWeight(AsmOperandInfo &info, 83 const char *constraint) const override; 84 void LowerAsmOperandForConstraint(SDValue Op, 85 std::string &Constraint, 86 std::vector<SDValue> &Ops, 87 SelectionDAG &DAG) const override; 88 89 std::pair<unsigned, const TargetRegisterClass *> 90 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 91 StringRef Constraint, MVT VT) const override; 92 93 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 94 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 95 return MVT::i32; 96 } 97 98 Register getRegisterByName(const char* RegName, LLT VT, 99 const MachineFunction &MF) const override; 100 101 /// If a physical register, this returns the register that receives the 102 /// exception address on entry to an EH pad. 103 Register 104 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 105 return SP::I0; 106 } 107 108 /// If a physical register, this returns the register that receives the 109 /// exception typeid on entry to a landing pad. 110 Register 111 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 112 return SP::I1; 113 } 114 115 /// Override to support customized stack guard loading. 116 bool useLoadStackGuardNode() const override; 117 void insertSSPDeclarations(Module &M) const override; 118 119 /// getSetCCResultType - Return the ISD::SETCC ValueType 120 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 121 EVT VT) const override; 122 123 SDValue 124 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 125 const SmallVectorImpl<ISD::InputArg> &Ins, 126 const SDLoc &dl, SelectionDAG &DAG, 127 SmallVectorImpl<SDValue> &InVals) const override; 128 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, 129 bool isVarArg, 130 const SmallVectorImpl<ISD::InputArg> &Ins, 131 const SDLoc &dl, SelectionDAG &DAG, 132 SmallVectorImpl<SDValue> &InVals) const; 133 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, 134 bool isVarArg, 135 const SmallVectorImpl<ISD::InputArg> &Ins, 136 const SDLoc &dl, SelectionDAG &DAG, 137 SmallVectorImpl<SDValue> &InVals) const; 138 139 SDValue 140 LowerCall(TargetLowering::CallLoweringInfo &CLI, 141 SmallVectorImpl<SDValue> &InVals) const override; 142 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 143 SmallVectorImpl<SDValue> &InVals) const; 144 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 145 SmallVectorImpl<SDValue> &InVals) const; 146 147 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 148 const SmallVectorImpl<ISD::OutputArg> &Outs, 149 const SmallVectorImpl<SDValue> &OutVals, 150 const SDLoc &dl, SelectionDAG &DAG) const override; 151 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, 152 bool IsVarArg, 153 const SmallVectorImpl<ISD::OutputArg> &Outs, 154 const SmallVectorImpl<SDValue> &OutVals, 155 const SDLoc &DL, SelectionDAG &DAG) const; 156 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, 157 bool IsVarArg, 158 const SmallVectorImpl<ISD::OutputArg> &Outs, 159 const SmallVectorImpl<SDValue> &OutVals, 160 const SDLoc &DL, SelectionDAG &DAG) const; 161 162 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 163 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 164 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 165 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 166 167 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 168 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 169 SelectionDAG &DAG) const; 170 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 171 172 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, 173 const SDLoc &DL, SelectionDAG &DAG) const; 174 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, 175 const char *LibFuncName, 176 unsigned numArgs) const; 177 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, 178 const SDLoc &DL, SelectionDAG &DAG) const; 179 180 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 181 182 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const; 183 184 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, 185 SelectionDAG &DAG) const; 186 187 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 188 189 bool IsEligibleForTailCallOptimization(CCState &CCInfo, 190 CallLoweringInfo &CLI, 191 MachineFunction &MF) const; 192 193 bool ShouldShrinkFPConstant(EVT VT) const override { 194 // Do not shrink FP constpool if VT == MVT::f128. 195 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 196 return VT != MVT::f128; 197 } 198 199 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 200 // FIXME: We insert fences for each atomics and generate 201 // sub-optimal code for PSO/TSO. (Approximately nobody uses any 202 // mode but TSO, which makes this even more silly) 203 return true; 204 } 205 206 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 207 208 void ReplaceNodeResults(SDNode *N, 209 SmallVectorImpl<SDValue>& Results, 210 SelectionDAG &DAG) const override; 211 212 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, 213 unsigned BROpcode) const; 214 }; 215 } // end namespace llvm 216 217 #endif // SPARC_ISELLOWERING_H 218