1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains instruction definitions and patterns needed for 64-bit 10// code generation on SPARC v9. 11// 12// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can 13// also be used in 32-bit code running on a SPARC v9 CPU. 14// 15//===----------------------------------------------------------------------===// 16 17let Predicates = [Is64Bit] in { 18// The same integer registers are used for i32 and i64 values. 19// When registers hold i32 values, the high bits are don't care. 20// This give us free trunc and anyext. 21def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>; 22def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>; 23 24} // Predicates = [Is64Bit] 25 26 27//===----------------------------------------------------------------------===// 28// 64-bit Shift Instructions. 29//===----------------------------------------------------------------------===// 30// 31// The 32-bit shift instructions are still available. The left shift srl 32// instructions shift all 64 bits, but it only accepts a 5-bit shift amount. 33// 34// The srl instructions only shift the low 32 bits and clear the high 32 bits. 35// Finally, sra shifts the low 32 bits and sign-extends to 64 bits. 36 37let Predicates = [Is64Bit] in { 38 39def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>; 40def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>; 41 42def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>; 43def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>; 44 45defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, shift_imm6, I64Regs>; 46defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, shift_imm6, I64Regs>; 47defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>; 48 49} // Predicates = [Is64Bit] 50 51 52//===----------------------------------------------------------------------===// 53// 64-bit Immediates. 54//===----------------------------------------------------------------------===// 55// 56// All 32-bit immediates can be materialized with sethi+or, but 64-bit 57// immediates may require more code. There may be a point where it is 58// preferable to use a constant pool load instead, depending on the 59// microarchitecture. 60 61// Single-instruction patterns. 62 63// The ALU instructions want their simm13 operands as i32 immediates. 64def as_i32imm : SDNodeXForm<imm, [{ 65 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 66}]>; 67def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; 68def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; 69 70// Double-instruction patterns. 71 72// All unsigned i32 immediates can be handled by sethi+or. 73def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 74def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>, 75 Requires<[Is64Bit]>; 76 77// All negative i33 immediates can be handled by sethi+xor. 78def nimm33 : PatLeaf<(imm), [{ 79 int64_t Imm = N->getSExtValue(); 80 return Imm < 0 && isInt<33>(Imm); 81}]>; 82// Bits 10-31 inverted. Same as assembler's %hix. 83def HIX22 : SDNodeXForm<imm, [{ 84 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); 85 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 86}]>; 87// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. 88def LOX10 : SDNodeXForm<imm, [{ 89 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N), 90 MVT::i32); 91}]>; 92def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, 93 Requires<[Is64Bit]>; 94 95// More possible patterns: 96// 97// (sllx sethi, n) 98// (sllx simm13, n) 99// 100// 3 instrs: 101// 102// (xor (sllx sethi), simm13) 103// (sllx (xor sethi, simm13)) 104// 105// 4 instrs: 106// 107// (or sethi, (sllx sethi)) 108// (xnor sethi, (sllx sethi)) 109// 110// 5 instrs: 111// 112// (or (sllx sethi), (or sethi, simm13)) 113// (xnor (sllx sethi), (or sethi, simm13)) 114// (or (sllx sethi), (sllx sethi)) 115// (xnor (sllx sethi), (sllx sethi)) 116// 117// Worst case is 6 instrs: 118// 119// (or (sllx (or sethi, simmm13)), (or sethi, simm13)) 120 121// Bits 42-63, same as assembler's %hh. 122def HH22 : SDNodeXForm<imm, [{ 123 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); 124 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 125}]>; 126// Bits 32-41, same as assembler's %hm. 127def HM10 : SDNodeXForm<imm, [{ 128 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); 129 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 130}]>; 131def : Pat<(i64 imm:$val), 132 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), 133 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>, 134 Requires<[Is64Bit]>; 135 136 137//===----------------------------------------------------------------------===// 138// 64-bit Integer Arithmetic and Logic. 139//===----------------------------------------------------------------------===// 140 141let Predicates = [Is64Bit] in { 142 143// Register-register instructions. 144let isCodeGenOnly = 1 in { 145defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>; 146defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>; 147defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>; 148 149def ANDXNrr : F3_1<2, 0b000101, 150 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 151 "andn $b, $c, $dst", 152 [(set i64:$dst, (and i64:$b, (not i64:$c)))]>; 153def ORXNrr : F3_1<2, 0b000110, 154 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 155 "orn $b, $c, $dst", 156 [(set i64:$dst, (or i64:$b, (not i64:$c)))]>; 157def XNORXrr : F3_1<2, 0b000111, 158 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 159 "xnor $b, $c, $dst", 160 [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>; 161 162defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>; 163defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>; 164 165def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd), 166 (ins I64Regs:$rs1, I64Regs:$rs2, TailRelocSymTLSAdd:$sym), 167 "add $rs1, $rs2, $rd, $sym", 168 [(set i64:$rd, 169 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>; 170 171// "LEA" form of add 172def LEAX_ADDri : F3_2<2, 0b000000, 173 (outs I64Regs:$dst), (ins MEMri:$addr), 174 "add ${addr:arith}, $dst", 175 [(set iPTR:$dst, ADDRri:$addr)]>; 176} 177 178def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; 179def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; 180def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>; 181 182} // Predicates = [Is64Bit] 183 184 185//===----------------------------------------------------------------------===// 186// 64-bit Integer Multiply and Divide. 187//===----------------------------------------------------------------------===// 188 189let Predicates = [Is64Bit] in { 190 191def MULXrr : F3_1<2, 0b001001, 192 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 193 "mulx $rs1, $rs2, $rd", 194 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 195def MULXri : F3_2<2, 0b001001, 196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 197 "mulx $rs1, $simm13, $rd", 198 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 199 200// Division can trap. 201let hasSideEffects = 1 in { 202def SDIVXrr : F3_1<2, 0b101101, 203 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 204 "sdivx $rs1, $rs2, $rd", 205 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; 206def SDIVXri : F3_2<2, 0b101101, 207 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 208 "sdivx $rs1, $simm13, $rd", 209 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; 210 211def UDIVXrr : F3_1<2, 0b001101, 212 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 213 "udivx $rs1, $rs2, $rd", 214 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; 215def UDIVXri : F3_2<2, 0b001101, 216 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 217 "udivx $rs1, $simm13, $rd", 218 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; 219} // hasSideEffects = 1 220 221} // Predicates = [Is64Bit] 222 223 224//===----------------------------------------------------------------------===// 225// 64-bit Loads and Stores. 226//===----------------------------------------------------------------------===// 227// 228// All the 32-bit loads and stores are available. The extending loads are sign 229// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits 230// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned 231// Word). 232// 233// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads. 234 235let Predicates = [Is64Bit] in { 236 237// 64-bit loads. 238let DecoderMethod = "DecodeLoadInt" in 239 defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>; 240 241let mayLoad = 1, isAsmParserOnly = 1 in { 242 def TLS_LDXrr : F3_1<3, 0b001011, 243 (outs IntRegs:$dst), 244 (ins MEMrr:$addr, TailRelocSymTLSLoad:$sym), 245 "ldx [$addr], $dst, $sym", 246 [(set i64:$dst, 247 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 248 def GDOP_LDXrr : F3_1<3, 0b001011, 249 (outs I64Regs:$dst), 250 (ins MEMrr:$addr, TailRelocSymGOTLoad:$sym), 251 "ldx [$addr], $dst, $sym", 252 [(set i64:$dst, 253 (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>; 254} 255 256// Extending loads to i64. 257def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 258def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 259def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 260def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 261 262def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 263def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 264def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 265def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 266def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>; 267def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>; 268 269def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 270def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 271def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 272def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 273def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>; 274def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>; 275 276def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 277def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 278def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 279def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 280 281// Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 282let DecoderMethod = "DecodeLoadInt" in 283 defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>; 284 285// 64-bit stores. 286let DecoderMethod = "DecodeStoreInt" in 287 defm STX : Store<"stx", 0b001110, store, I64Regs, i64>; 288 289// Truncating stores from i64 are identical to the i32 stores. 290def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 291def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>; 292def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>; 293def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>; 294def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>; 295def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>; 296 297// store 0, addr -> store %g0, addr 298def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>; 299def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>; 300 301} // Predicates = [Is64Bit] 302 303 304//===----------------------------------------------------------------------===// 305// 64-bit Conditionals. 306//===----------------------------------------------------------------------===// 307 308// 309// Flag-setting instructions like subcc and addcc set both icc and xcc flags. 310// The icc flags correspond to the 32-bit result, and the xcc are for the 311// full 64-bit result. 312// 313// We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for 314// 64-bit compares. See LowerBR_CC. 315 316let Predicates = [Is64Bit] in { 317 318let Uses = [ICC], cc = 0b10 in 319 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>; 320 321// Conditional moves on %xcc. 322let Uses = [ICC], Constraints = "$f = $rd" in { 323let intcc = 1, cc = 0b10 in { 324def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd), 325 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 326 "mov$cond %xcc, $rs2, $rd", 327 [(set i32:$rd, 328 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; 329def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd), 330 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 331 "mov$cond %xcc, $simm11, $rd", 332 [(set i32:$rd, 333 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>; 334} // cc 335 336let intcc = 1, opf_cc = 0b10 in { 337def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 338 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 339 "fmovs$cond %xcc, $rs2, $rd", 340 [(set f32:$rd, 341 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; 342def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 343 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 344 "fmovd$cond %xcc, $rs2, $rd", 345 [(set f64:$rd, 346 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 347let Predicates = [Is64Bit, HasHardQuad] in 348def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 349 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 350 "fmovq$cond %xcc, $rs2, $rd", 351 [(set f128:$rd, 352 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>; 353} // opf_cc 354} // Uses, Constraints 355 356// Branch On integer register with Prediction (BPr). 357let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in 358multiclass BranchOnReg<bits<3> cond, string OpcStr> { 359 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 360 !strconcat(OpcStr, " $rs1, $imm16"), []>; 361 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 362 !strconcat(OpcStr, ",a $rs1, $imm16"), []>; 363 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 364 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>; 365 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 366 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>; 367} 368 369multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> { 370 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"), 371 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>; 372 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"), 373 (APT I64Regs:$rs1, bprtarget16:$imm16), 0>; 374} 375 376defm BPZ : BranchOnReg<0b001, "brz">; 377defm BPLEZ : BranchOnReg<0b010, "brlez">; 378defm BPLZ : BranchOnReg<0b011, "brlz">; 379defm BPNZ : BranchOnReg<0b101, "brnz">; 380defm BPGZ : BranchOnReg<0b110, "brgz">; 381defm BPGEZ : BranchOnReg<0b111, "brgez">; 382 383defm : bpr_alias<"brz", BPZnapt, BPZapt >; 384defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>; 385defm : bpr_alias<"brlz", BPLZnapt, BPLZapt >; 386defm : bpr_alias<"brnz", BPNZnapt, BPNZapt >; 387defm : bpr_alias<"brgz", BPGZnapt, BPGZapt >; 388defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>; 389 390// Move integer register on register condition (MOVr). 391multiclass MOVR< bits<3> rcond, string OpcStr> { 392 def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd), 393 (ins I64Regs:$rs1, IntRegs:$rs2), 394 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 395 396 def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd), 397 (ins I64Regs:$rs1, i64imm:$simm10), 398 !strconcat(OpcStr, " $rs1, $simm10, $rd"), []>; 399} 400 401defm MOVRRZ : MOVR<0b001, "movrz">; 402defm MOVRLEZ : MOVR<0b010, "movrlez">; 403defm MOVRLZ : MOVR<0b011, "movrlz">; 404defm MOVRNZ : MOVR<0b101, "movrnz">; 405defm MOVRGZ : MOVR<0b110, "movrgz">; 406defm MOVRGEZ : MOVR<0b111, "movrgez">; 407 408// Move FP register on integer register condition (FMOVr). 409multiclass FMOVR<bits<3> rcond, string OpcStr> { 410 411 def S : F4_4r<0b110101, 0b00101, rcond, 412 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 413 !strconcat(!strconcat("fmovrs", OpcStr)," $rs1, $rs2, $rd"), 414 []>; 415 def D : F4_4r<0b110101, 0b00110, rcond, 416 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 417 !strconcat(!strconcat("fmovrd", OpcStr)," $rs1, $rs2, $rd"), 418 []>; 419 def Q : F4_4r<0b110101, 0b00111, rcond, 420 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 421 !strconcat(!strconcat("fmovrq", OpcStr)," $rs1, $rs2, $rd"), 422 []>, Requires<[HasHardQuad]>; 423} 424 425let Predicates = [HasV9] in { 426 defm FMOVRZ : FMOVR<0b001, "z">; 427 defm FMOVRLEZ : FMOVR<0b010, "lez">; 428 defm FMOVRLZ : FMOVR<0b011, "lz">; 429 defm FMOVRNZ : FMOVR<0b101, "nz">; 430 defm FMOVRGZ : FMOVR<0b110, "gz">; 431 defm FMOVRGEZ : FMOVR<0b111, "gez">; 432} 433 434//===----------------------------------------------------------------------===// 435// 64-bit Floating Point Conversions. 436//===----------------------------------------------------------------------===// 437 438let Predicates = [Is64Bit] in { 439 440def FXTOS : F3_3u<2, 0b110100, 0b010000100, 441 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 442 "fxtos $rs2, $rd", 443 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 444def FXTOD : F3_3u<2, 0b110100, 0b010001000, 445 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 446 "fxtod $rs2, $rd", 447 [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 448let Predicates = [Is64Bit, HasHardQuad] in 449def FXTOQ : F3_3u<2, 0b110100, 0b010001100, 450 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 451 "fxtoq $rs2, $rd", 452 [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 453 454def FSTOX : F3_3u<2, 0b110100, 0b010000001, 455 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 456 "fstox $rs2, $rd", 457 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>; 458def FDTOX : F3_3u<2, 0b110100, 0b010000010, 459 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 460 "fdtox $rs2, $rd", 461 [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>; 462let Predicates = [Is64Bit, HasHardQuad] in 463def FQTOX : F3_3u<2, 0b110100, 0b010000011, 464 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 465 "fqtox $rs2, $rd", 466 [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>; 467 468} // Predicates = [Is64Bit] 469 470def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), 471 (MOVXCCrr $t, $f, imm:$cond)>; 472def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond), 473 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>; 474 475def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond), 476 (MOVICCrr $t, $f, imm:$cond)>; 477def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond), 478 (MOVICCri (as_i32imm $t), $f, imm:$cond)>; 479 480def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond), 481 (MOVFCCrr $t, $f, imm:$cond)>; 482def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond), 483 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>; 484 485} // Predicates = [Is64Bit] 486 487 488// 64 bit SETHI 489let Predicates = [Is64Bit], isCodeGenOnly = 1 in { 490def SETHIXi : F2_1<0b100, 491 (outs IntRegs:$rd), (ins i64imm:$imm22), 492 "sethi $imm22, $rd", 493 [(set i64:$rd, SETHIimm:$imm22)]>; 494} 495 496// ATOMICS. 497let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in { 498 def CASXrr: F3_1_asi<3, 0b111110, 499 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, 500 I64Regs:$swap), 501 "casx [$rs1], $rs2, $rd", 502 [(set i64:$rd, 503 (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>; 504 505} // Predicates = [Is64Bit], Constraints = ... 506 507let Predicates = [Is64Bit] in { 508 509// atomic_load_64 addr -> load addr 510def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>; 511def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>; 512 513// atomic_store_64 val, addr -> store val, addr 514def : Pat<(atomic_store_64 ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>; 515def : Pat<(atomic_store_64 ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>; 516 517} // Predicates = [Is64Bit] 518 519let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in 520 defm TXCC : TRAP<"%xcc">; 521 522// Global addresses, constant pool entries 523let Predicates = [Is64Bit] in { 524 525def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 526def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>; 527def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 528def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>; 529 530// GlobalTLS addresses 531def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 532def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>; 533def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 534 (ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 535def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 536 (XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 537 538// Blockaddress 539def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 540def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>; 541 542// Add reg, lo. This is used when taking the addr of a global/constpool entry. 543def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>; 544def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>; 545def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 546 (ADDXri $r, tblockaddress:$in)>; 547} 548