1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
10             InstrItinClass itin = NoItinerary>
11   : Instruction {
12  field bits<32> Inst;
13
14  let Namespace = "SP";
15  let Size = 4;
16
17  bits<2> op;
18  let Inst{31-30} = op;               // Top two bits are the 'op' field
19
20  dag OutOperandList = outs;
21  dag InOperandList = ins;
22  let AsmString   = asmstr;
23  let Pattern = pattern;
24
25  let DecoderNamespace = "Sparc";
26  field bits<32> SoftFail = 0;
27
28  let Itinerary = itin;
29}
30
31//===----------------------------------------------------------------------===//
32// Format #2 instruction classes in the Sparc
33//===----------------------------------------------------------------------===//
34
35// Format 2 instructions
36class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
37         InstrItinClass itin = NoItinerary>
38   : InstSP<outs, ins, asmstr, pattern, itin> {
39  bits<3>  op2;
40  bits<22> imm22;
41  let op          = 0;    // op = 0
42  let Inst{24-22} = op2;
43  let Inst{21-0}  = imm22;
44}
45
46// Specific F2 classes: SparcV8 manual, page 44
47//
48class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
49           InstrItinClass itin = NoItinerary>
50   : F2<outs, ins, asmstr, pattern, itin> {
51  bits<5>  rd;
52
53  let op2         = op2Val;
54
55  let Inst{29-25} = rd;
56}
57
58class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
59           list<dag> pattern, InstrItinClass itin = NoItinerary>
60   : F2<outs, ins, asmstr, pattern, itin> {
61  bits<4>   cond;
62  let op2         = op2Val;
63
64  let Inst{29}    = annul;
65  let Inst{28-25} = cond;
66}
67
68class F2_3<bits<3> op2Val, bit annul, bit pred,
69           dag outs, dag ins, string asmstr, list<dag> pattern,
70           InstrItinClass itin = NoItinerary>
71   : InstSP<outs, ins, asmstr, pattern, itin> {
72  bits<2>  cc;
73  bits<4>  cond;
74  bits<19> imm19;
75
76  let op          = 0;    // op = 0
77
78  let Inst{29}    = annul;
79  let Inst{28-25} = cond;
80  let Inst{24-22} = op2Val;
81  let Inst{21-20} = cc;
82  let Inst{19}    = pred;
83  let Inst{18-0}  = imm19;
84}
85
86class F2_4<bit annul, bit pred, dag outs, dag ins,
87           string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
88   : InstSP<outs, ins, asmstr, pattern, itin> {
89  bits<16> imm16;
90  bits<5>  rs1;
91  bits<3>  rcond;
92
93  let op          = 0;    // op = 0
94
95  let Inst{29}    = annul;
96  let Inst{28}    = 0;
97  let Inst{27-25} = rcond;
98  let Inst{24-22} = 0b011;
99  let Inst{21-20} = imm16{15-14};
100  let Inst{19}    = pred;
101  let Inst{18-14} = rs1;
102  let Inst{13-0}  = imm16{13-0};
103}
104
105
106//===----------------------------------------------------------------------===//
107// Format #3 instruction classes in the Sparc
108//===----------------------------------------------------------------------===//
109
110class F3<dag outs, dag ins, string asmstr, list<dag> pattern,
111         InstrItinClass itin = NoItinerary>
112   : InstSP<outs, ins, asmstr, pattern, itin> {
113  bits<5> rd;
114  bits<6> op3;
115  bits<5> rs1;
116  let op{1} = 1;   // Op = 2 or 3
117  let Inst{29-25} = rd;
118  let Inst{24-19} = op3;
119  let Inst{18-14} = rs1;
120}
121
122// Specific F3 classes: SparcV8 manual, page 44
123//
124class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
125           string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
126   : F3<outs, ins, asmstr, pattern, itin> {
127  bits<8> asi;
128  bits<5> rs2;
129
130  let op         = opVal;
131  let op3        = op3val;
132
133  let Inst{13}   = 0;     // i field = 0
134  let Inst{12-5} = asi;   // address space identifier
135  let Inst{4-0}  = rs2;
136}
137
138class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
139       list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
140  : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {
141  let asi = 0;
142}
143
144class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
145           string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
146   : F3<outs, ins, asmstr, pattern, itin> {
147  bits<13> simm13;
148
149  let op         = opVal;
150  let op3        = op3val;
151
152  let Inst{13}   = 1;     // i field = 1
153  let Inst{12-0} = simm13;
154}
155
156// floating-point
157class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
158           string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
159   : F3<outs, ins, asmstr, pattern, itin> {
160  bits<5> rs2;
161
162  let op         = opVal;
163  let op3        = op3val;
164
165  let Inst{13-5} = opfval;   // fp opcode
166  let Inst{4-0}  = rs2;
167}
168
169// floating-point unary operations.
170class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
171           string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
172   : F3<outs, ins, asmstr, pattern, itin> {
173  bits<5> rs2;
174
175  let op         = opVal;
176  let op3        = op3val;
177  let rs1        = 0;
178
179  let Inst{13-5} = opfval;   // fp opcode
180  let Inst{4-0}  = rs2;
181}
182
183// floating-point compares.
184class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
185           string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
186   : F3<outs, ins, asmstr, pattern, itin> {
187  bits<5> rs2;
188
189  let op         = opVal;
190  let op3        = op3val;
191
192  let Inst{13-5} = opfval;   // fp opcode
193  let Inst{4-0}  = rs2;
194}
195
196// Shift by register rs2.
197class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
198            string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
199   : F3<outs, ins, asmstr, pattern, itin> {
200  bit x = xVal;           // 1 for 64-bit shifts.
201  bits<5> rs2;
202
203  let op         = opVal;
204  let op3        = op3val;
205
206  let Inst{13}   = 0;     // i field = 0
207  let Inst{12}   = x;     // extended registers.
208  let Inst{4-0}  = rs2;
209}
210
211// Shift by immediate.
212class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
213            string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
214   : F3<outs, ins, asmstr, pattern, itin> {
215  bit x = xVal;           // 1 for 64-bit shifts.
216  bits<6> shcnt;          // shcnt32 / shcnt64.
217
218  let op         = opVal;
219  let op3        = op3val;
220
221  let Inst{13}   = 1;     // i field = 1
222  let Inst{12}   = x;     // extended registers.
223  let Inst{5-0}  = shcnt;
224}
225
226// Define rr and ri shift instructions with patterns.
227multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
228                ValueType VT, Operand SIT, RegisterClass RC,
229                InstrItinClass itin = IIC_iu_instr> {
230  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
231                 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
232                 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],
233                 itin>;
234  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, SIT:$shcnt),
235                 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
236                 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))],
237                 itin>;
238}
239
240class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
241         InstrItinClass itin = NoItinerary>
242   : InstSP<outs, ins, asmstr, pattern, itin> {
243  bits<5> rd;
244
245  let op          = 2;
246  let Inst{29-25} = rd;
247  let Inst{24-19} = op3;
248}
249
250
251class F4_1<bits<6> op3, dag outs, dag ins,
252           string asmstr, list<dag> pattern,
253           InstrItinClass itin = NoItinerary>
254   : F4<op3, outs, ins, asmstr, pattern, itin> {
255  bit    intcc;
256  bits<2> cc;
257  bits<4> cond;
258  bits<5> rs2;
259
260  let Inst{4-0}   = rs2;
261  let Inst{12-11} = cc;
262  let Inst{13}    = 0;
263  let Inst{17-14} = cond;
264  let Inst{18}    = intcc;
265}
266
267class F4_2<bits<6> op3, dag outs, dag ins,
268            string asmstr, list<dag> pattern,
269            InstrItinClass itin = NoItinerary>
270   : F4<op3, outs, ins, asmstr, pattern, itin> {
271  bit      intcc;
272  bits<2>  cc;
273  bits<4>  cond;
274  bits<11> simm11;
275
276  let Inst{10-0}  = simm11;
277  let Inst{12-11} = cc;
278  let Inst{13}    = 1;
279  let Inst{17-14} = cond;
280  let Inst{18}    = intcc;
281}
282
283class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
284           string asmstr, list<dag> pattern,
285           InstrItinClass itin = NoItinerary>
286   : F4<op3, outs, ins, asmstr, pattern, itin> {
287  bits<4> cond;
288  bit     intcc;
289  bits<2> opf_cc;
290  bits<5> rs2;
291
292  let Inst{18}     = 0;
293  let Inst{17-14}  = cond;
294  let Inst{13}     = intcc;
295  let Inst{12-11}  = opf_cc;
296  let Inst{10-5}   = opf_low;
297  let Inst{4-0}    = rs2;
298}
299
300class F4_4r<bits<6> op3, bits<5> opf_low, dag outs, dag ins,
301            string asmstr, list<dag> pattern,
302            InstrItinClass itin = NoItinerary>
303   : F4<op3, outs, ins, asmstr, pattern, itin> {
304  bits<5> rs1;
305  bits<5> rs2;
306  bits<3> rcond;
307  let Inst{18-14} = rs1;
308  let Inst{13}    = 0;  // IsImm
309  let Inst{12-10} = rcond;
310  let Inst{9-5}   = opf_low;
311  let Inst{4-0}   = rs2;
312}
313
314
315class F4_4i<bits<6> op3, dag outs, dag ins,
316            string asmstr, list<dag> pattern,
317           InstrItinClass itin = NoItinerary>
318   : F4<op3, outs, ins, asmstr, pattern, itin> {
319  bits<5>  rs1;
320  bits<10> simm10;
321  bits<3>  rcond;
322  let Inst{18-14} = rs1;
323  let Inst{13}    = 1;  // IsImm
324  let Inst{12-10} = rcond;
325  let Inst{9-0}   = simm10;
326}
327
328
329class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins,
330             string asmstr, list<dag> pattern,
331             InstrItinClass itin = NoItinerary>
332   : F3<outs, ins, asmstr, pattern, itin> {
333   bits<4> cond;
334   bits<2> cc;
335
336   let op = 0b10;
337   let rd{4} = 0;
338   let rd{3-0} = cond;
339   let op3 = op3Val;
340   let Inst{13} = isimm;
341   let Inst{12-11} = cc;
342
343}
344
345class TRAPSPrr<bits<6> op3Val, dag outs, dag ins,
346               string asmstr, list<dag> pattern,
347               InstrItinClass itin = NoItinerary>
348   : TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> {
349   bits<5> rs2;
350
351   let Inst{10-5} = 0;
352   let Inst{4-0}  = rs2;
353}
354
355class TRAPSPri<bits<6> op3Val, dag outs, dag ins,
356               string asmstr, list<dag> pattern,
357               InstrItinClass itin = NoItinerary>
358   : TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> {
359   bits<8> imm;
360
361   let Inst{10-8} = 0;
362   let Inst{7-0}  = imm;
363}
364
365// Pseudo-instructions for alternate assembly syntax (never used by codegen).
366// These are aliases that require C++ handling to convert to the target
367// instruction, while InstAliases can be handled directly by tblgen.
368class AsmPseudoInst<dag outs, dag ins, string asm>
369  : InstSP<outs, ins, asm, []> {
370  let isPseudo = 1;
371}
372