1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/SystemZInstPrinter.h"
10 #include "MCTargetDesc/SystemZMCAsmInfo.h"
11 #include "MCTargetDesc/SystemZMCTargetDesc.h"
12 #include "SystemZTargetStreamer.h"
13 #include "TargetInfo/SystemZTargetInfo.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstBuilder.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCParser/MCAsmLexer.h"
24 #include "llvm/MC/MCParser/MCAsmParser.h"
25 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
26 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
27 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/SMLoc.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstddef>
37 #include <cstdint>
38 #include <iterator>
39 #include <memory>
40 #include <string>
41 
42 using namespace llvm;
43 
44 // Return true if Expr is in the range [MinValue, MaxValue]. If AllowSymbol
45 // is true any MCExpr is accepted (address displacement).
46 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue,
47                     bool AllowSymbol = false) {
48   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
49     int64_t Value = CE->getValue();
50     return Value >= MinValue && Value <= MaxValue;
51   }
52   return AllowSymbol;
53 }
54 
55 namespace {
56 
57 enum RegisterKind {
58   GR32Reg,
59   GRH32Reg,
60   GR64Reg,
61   GR128Reg,
62   FP32Reg,
63   FP64Reg,
64   FP128Reg,
65   VR32Reg,
66   VR64Reg,
67   VR128Reg,
68   AR32Reg,
69   CR64Reg,
70 };
71 
72 enum MemoryKind {
73   BDMem,
74   BDXMem,
75   BDLMem,
76   BDRMem,
77   BDVMem
78 };
79 
80 class SystemZOperand : public MCParsedAsmOperand {
81 private:
82   enum OperandKind {
83     KindInvalid,
84     KindToken,
85     KindReg,
86     KindImm,
87     KindImmTLS,
88     KindMem
89   };
90 
91   OperandKind Kind;
92   SMLoc StartLoc, EndLoc;
93 
94   // A string of length Length, starting at Data.
95   struct TokenOp {
96     const char *Data;
97     unsigned Length;
98   };
99 
100   // LLVM register Num, which has kind Kind.  In some ways it might be
101   // easier for this class to have a register bank (general, floating-point
102   // or access) and a raw register number (0-15).  This would postpone the
103   // interpretation of the operand to the add*() methods and avoid the need
104   // for context-dependent parsing.  However, we do things the current way
105   // because of the virtual getReg() method, which needs to distinguish
106   // between (say) %r0 used as a single register and %r0 used as a pair.
107   // Context-dependent parsing can also give us slightly better error
108   // messages when invalid pairs like %r1 are used.
109   struct RegOp {
110     RegisterKind Kind;
111     unsigned Num;
112   };
113 
114   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
115   // MemKind says what type of memory this is and RegKind says what type
116   // the base register has (GR32Reg or GR64Reg).  Length is the operand
117   // length for D(L,B)-style operands, otherwise it is null.
118   struct MemOp {
119     unsigned Base : 12;
120     unsigned Index : 12;
121     unsigned MemKind : 4;
122     unsigned RegKind : 4;
123     const MCExpr *Disp;
124     union {
125       const MCExpr *Imm;
126       unsigned Reg;
127     } Length;
128   };
129 
130   // Imm is an immediate operand, and Sym is an optional TLS symbol
131   // for use with a __tls_get_offset marker relocation.
132   struct ImmTLSOp {
133     const MCExpr *Imm;
134     const MCExpr *Sym;
135   };
136 
137   union {
138     TokenOp Token;
139     RegOp Reg;
140     const MCExpr *Imm;
141     ImmTLSOp ImmTLS;
142     MemOp Mem;
143   };
144 
145   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
146     // Add as immediates when possible.  Null MCExpr = 0.
147     if (!Expr)
148       Inst.addOperand(MCOperand::createImm(0));
149     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
150       Inst.addOperand(MCOperand::createImm(CE->getValue()));
151     else
152       Inst.addOperand(MCOperand::createExpr(Expr));
153   }
154 
155 public:
156   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
157       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
158 
159   // Create particular kinds of operand.
160   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
161                                                        SMLoc EndLoc) {
162     return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
163   }
164 
165   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
166     auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
167     Op->Token.Data = Str.data();
168     Op->Token.Length = Str.size();
169     return Op;
170   }
171 
172   static std::unique_ptr<SystemZOperand>
173   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
174     auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
175     Op->Reg.Kind = Kind;
176     Op->Reg.Num = Num;
177     return Op;
178   }
179 
180   static std::unique_ptr<SystemZOperand>
181   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
182     auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
183     Op->Imm = Expr;
184     return Op;
185   }
186 
187   static std::unique_ptr<SystemZOperand>
188   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
189             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
190             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
191     auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
192     Op->Mem.MemKind = MemKind;
193     Op->Mem.RegKind = RegKind;
194     Op->Mem.Base = Base;
195     Op->Mem.Index = Index;
196     Op->Mem.Disp = Disp;
197     if (MemKind == BDLMem)
198       Op->Mem.Length.Imm = LengthImm;
199     if (MemKind == BDRMem)
200       Op->Mem.Length.Reg = LengthReg;
201     return Op;
202   }
203 
204   static std::unique_ptr<SystemZOperand>
205   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
206                SMLoc StartLoc, SMLoc EndLoc) {
207     auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
208     Op->ImmTLS.Imm = Imm;
209     Op->ImmTLS.Sym = Sym;
210     return Op;
211   }
212 
213   // Token operands
214   bool isToken() const override {
215     return Kind == KindToken;
216   }
217   StringRef getToken() const {
218     assert(Kind == KindToken && "Not a token");
219     return StringRef(Token.Data, Token.Length);
220   }
221 
222   // Register operands.
223   bool isReg() const override {
224     return Kind == KindReg;
225   }
226   bool isReg(RegisterKind RegKind) const {
227     return Kind == KindReg && Reg.Kind == RegKind;
228   }
229   unsigned getReg() const override {
230     assert(Kind == KindReg && "Not a register");
231     return Reg.Num;
232   }
233 
234   // Immediate operands.
235   bool isImm() const override {
236     return Kind == KindImm;
237   }
238   bool isImm(int64_t MinValue, int64_t MaxValue) const {
239     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
240   }
241   const MCExpr *getImm() const {
242     assert(Kind == KindImm && "Not an immediate");
243     return Imm;
244   }
245 
246   // Immediate operands with optional TLS symbol.
247   bool isImmTLS() const {
248     return Kind == KindImmTLS;
249   }
250 
251   const ImmTLSOp getImmTLS() const {
252     assert(Kind == KindImmTLS && "Not a TLS immediate");
253     return ImmTLS;
254   }
255 
256   // Memory operands.
257   bool isMem() const override {
258     return Kind == KindMem;
259   }
260   bool isMem(MemoryKind MemKind) const {
261     return (Kind == KindMem &&
262             (Mem.MemKind == MemKind ||
263              // A BDMem can be treated as a BDXMem in which the index
264              // register field is 0.
265              (Mem.MemKind == BDMem && MemKind == BDXMem)));
266   }
267   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
268     return isMem(MemKind) && Mem.RegKind == RegKind;
269   }
270   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
271     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true);
272   }
273   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
274     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true);
275   }
276   bool isMemDisp12Len4(RegisterKind RegKind) const {
277     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
278   }
279   bool isMemDisp12Len8(RegisterKind RegKind) const {
280     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
281   }
282 
283   const MemOp& getMem() const {
284     assert(Kind == KindMem && "Not a Mem operand");
285     return Mem;
286   }
287 
288   // Override MCParsedAsmOperand.
289   SMLoc getStartLoc() const override { return StartLoc; }
290   SMLoc getEndLoc() const override { return EndLoc; }
291   void print(raw_ostream &OS) const override;
292 
293   /// getLocRange - Get the range between the first and last token of this
294   /// operand.
295   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
296 
297   // Used by the TableGen code to add particular types of operand
298   // to an instruction.
299   void addRegOperands(MCInst &Inst, unsigned N) const {
300     assert(N == 1 && "Invalid number of operands");
301     Inst.addOperand(MCOperand::createReg(getReg()));
302   }
303   void addImmOperands(MCInst &Inst, unsigned N) const {
304     assert(N == 1 && "Invalid number of operands");
305     addExpr(Inst, getImm());
306   }
307   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
308     assert(N == 2 && "Invalid number of operands");
309     assert(isMem(BDMem) && "Invalid operand type");
310     Inst.addOperand(MCOperand::createReg(Mem.Base));
311     addExpr(Inst, Mem.Disp);
312   }
313   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
314     assert(N == 3 && "Invalid number of operands");
315     assert(isMem(BDXMem) && "Invalid operand type");
316     Inst.addOperand(MCOperand::createReg(Mem.Base));
317     addExpr(Inst, Mem.Disp);
318     Inst.addOperand(MCOperand::createReg(Mem.Index));
319   }
320   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
321     assert(N == 3 && "Invalid number of operands");
322     assert(isMem(BDLMem) && "Invalid operand type");
323     Inst.addOperand(MCOperand::createReg(Mem.Base));
324     addExpr(Inst, Mem.Disp);
325     addExpr(Inst, Mem.Length.Imm);
326   }
327   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
328     assert(N == 3 && "Invalid number of operands");
329     assert(isMem(BDRMem) && "Invalid operand type");
330     Inst.addOperand(MCOperand::createReg(Mem.Base));
331     addExpr(Inst, Mem.Disp);
332     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
333   }
334   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
335     assert(N == 3 && "Invalid number of operands");
336     assert(isMem(BDVMem) && "Invalid operand type");
337     Inst.addOperand(MCOperand::createReg(Mem.Base));
338     addExpr(Inst, Mem.Disp);
339     Inst.addOperand(MCOperand::createReg(Mem.Index));
340   }
341   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
342     assert(N == 2 && "Invalid number of operands");
343     assert(Kind == KindImmTLS && "Invalid operand type");
344     addExpr(Inst, ImmTLS.Imm);
345     if (ImmTLS.Sym)
346       addExpr(Inst, ImmTLS.Sym);
347   }
348 
349   // Used by the TableGen code to check for particular operand types.
350   bool isGR32() const { return isReg(GR32Reg); }
351   bool isGRH32() const { return isReg(GRH32Reg); }
352   bool isGRX32() const { return false; }
353   bool isGR64() const { return isReg(GR64Reg); }
354   bool isGR128() const { return isReg(GR128Reg); }
355   bool isADDR32() const { return isReg(GR32Reg); }
356   bool isADDR64() const { return isReg(GR64Reg); }
357   bool isADDR128() const { return false; }
358   bool isFP32() const { return isReg(FP32Reg); }
359   bool isFP64() const { return isReg(FP64Reg); }
360   bool isFP128() const { return isReg(FP128Reg); }
361   bool isVR32() const { return isReg(VR32Reg); }
362   bool isVR64() const { return isReg(VR64Reg); }
363   bool isVF128() const { return false; }
364   bool isVR128() const { return isReg(VR128Reg); }
365   bool isAR32() const { return isReg(AR32Reg); }
366   bool isCR64() const { return isReg(CR64Reg); }
367   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
368   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
369   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
370   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
371   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
372   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
373   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
374   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
375   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
376   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
377   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
378   bool isU1Imm() const { return isImm(0, 1); }
379   bool isU2Imm() const { return isImm(0, 3); }
380   bool isU3Imm() const { return isImm(0, 7); }
381   bool isU4Imm() const { return isImm(0, 15); }
382   bool isU6Imm() const { return isImm(0, 63); }
383   bool isU8Imm() const { return isImm(0, 255); }
384   bool isS8Imm() const { return isImm(-128, 127); }
385   bool isU12Imm() const { return isImm(0, 4095); }
386   bool isU16Imm() const { return isImm(0, 65535); }
387   bool isS16Imm() const { return isImm(-32768, 32767); }
388   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
389   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
390   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
391 };
392 
393 class SystemZAsmParser : public MCTargetAsmParser {
394 #define GET_ASSEMBLER_HEADER
395 #include "SystemZGenAsmMatcher.inc"
396 
397 private:
398   MCAsmParser &Parser;
399   enum RegisterGroup {
400     RegGR,
401     RegFP,
402     RegV,
403     RegAR,
404     RegCR
405   };
406   struct Register {
407     RegisterGroup Group;
408     unsigned Num;
409     SMLoc StartLoc, EndLoc;
410   };
411 
412   SystemZTargetStreamer &getTargetStreamer() {
413     assert(getParser().getStreamer().getTargetStreamer() &&
414            "do not have a target streamer");
415     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
416     return static_cast<SystemZTargetStreamer &>(TS);
417   }
418 
419   bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
420 
421   bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
422 
423   OperandMatchResultTy parseRegister(OperandVector &Operands,
424                                      RegisterKind Kind);
425 
426   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
427 
428   bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
429                     Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
430                     bool HasLength = false, bool HasVectorIndex = false);
431   bool parseAddressRegister(Register &Reg);
432 
433   bool ParseDirectiveInsn(SMLoc L);
434   bool ParseDirectiveMachine(SMLoc L);
435 
436   OperandMatchResultTy parseAddress(OperandVector &Operands,
437                                     MemoryKind MemKind,
438                                     RegisterKind RegKind);
439 
440   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
441                                   int64_t MaxVal, bool AllowTLS);
442 
443   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
444 
445   // Both the hlasm and att variants still rely on the basic gnu asm
446   // format with respect to inputs, clobbers, outputs etc.
447   //
448   // However, calling the overriden getAssemblerDialect() method in
449   // AsmParser is problematic. It either returns the AssemblerDialect field
450   // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
451   // unset, otherwise it returns the private AssemblerDialect field in
452   // AsmParser.
453   //
454   // The problematic part is because, we forcibly set the inline asm dialect
455   // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
456   // to the overriden getAssemblerDialect function in AsmParser.cpp, will
457   // not return the assembler dialect set in the respective MCAsmInfo instance.
458   //
459   // For this purpose, we explicitly query the SystemZMCAsmInfo instance
460   // here, to get the "correct" assembler dialect, and use it in various
461   // functions.
462   unsigned getMAIAssemblerDialect() {
463     return Parser.getContext().getAsmInfo()->getAssemblerDialect();
464   }
465 
466   // An alphabetic character in HLASM is a letter from 'A' through 'Z',
467   // or from 'a' through 'z', or '$', '_','#', or '@'.
468   inline bool isHLASMAlpha(char C) {
469     return isAlpha(C) || llvm::is_contained("_@#$", C);
470   }
471 
472   // A digit in HLASM is a number from 0 to 9.
473   inline bool isHLASMAlnum(char C) { return isHLASMAlpha(C) || isDigit(C); }
474 
475   // Are we parsing using the AD_HLASM dialect?
476   inline bool isParsingHLASM() { return getMAIAssemblerDialect() == AD_HLASM; }
477 
478   // Are we parsing using the AD_ATT dialect?
479   inline bool isParsingATT() { return getMAIAssemblerDialect() == AD_ATT; }
480 
481 public:
482   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
483                    const MCInstrInfo &MII,
484                    const MCTargetOptions &Options)
485     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
486     MCAsmParserExtension::Initialize(Parser);
487 
488     // Alias the .word directive to .short.
489     parser.addAliasForDirective(".word", ".short");
490 
491     // Initialize the set of available features.
492     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
493   }
494 
495   // Override MCTargetAsmParser.
496   bool ParseDirective(AsmToken DirectiveID) override;
497   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
498   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
499                      bool RestoreOnFailure);
500   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
501                                         SMLoc &EndLoc) override;
502   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
503                         SMLoc NameLoc, OperandVector &Operands) override;
504   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
505                                OperandVector &Operands, MCStreamer &Out,
506                                uint64_t &ErrorInfo,
507                                bool MatchingInlineAsm) override;
508   bool isLabel(AsmToken &Token) override;
509 
510   // Used by the TableGen code to parse particular operand types.
511   OperandMatchResultTy parseGR32(OperandVector &Operands) {
512     return parseRegister(Operands, GR32Reg);
513   }
514   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
515     return parseRegister(Operands, GRH32Reg);
516   }
517   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
518     llvm_unreachable("GRX32 should only be used for pseudo instructions");
519   }
520   OperandMatchResultTy parseGR64(OperandVector &Operands) {
521     return parseRegister(Operands, GR64Reg);
522   }
523   OperandMatchResultTy parseGR128(OperandVector &Operands) {
524     return parseRegister(Operands, GR128Reg);
525   }
526   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
527     // For the AsmParser, we will accept %r0 for ADDR32 as well.
528     return parseRegister(Operands, GR32Reg);
529   }
530   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
531     // For the AsmParser, we will accept %r0 for ADDR64 as well.
532     return parseRegister(Operands, GR64Reg);
533   }
534   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
535     llvm_unreachable("Shouldn't be used as an operand");
536   }
537   OperandMatchResultTy parseFP32(OperandVector &Operands) {
538     return parseRegister(Operands, FP32Reg);
539   }
540   OperandMatchResultTy parseFP64(OperandVector &Operands) {
541     return parseRegister(Operands, FP64Reg);
542   }
543   OperandMatchResultTy parseFP128(OperandVector &Operands) {
544     return parseRegister(Operands, FP128Reg);
545   }
546   OperandMatchResultTy parseVR32(OperandVector &Operands) {
547     return parseRegister(Operands, VR32Reg);
548   }
549   OperandMatchResultTy parseVR64(OperandVector &Operands) {
550     return parseRegister(Operands, VR64Reg);
551   }
552   OperandMatchResultTy parseVF128(OperandVector &Operands) {
553     llvm_unreachable("Shouldn't be used as an operand");
554   }
555   OperandMatchResultTy parseVR128(OperandVector &Operands) {
556     return parseRegister(Operands, VR128Reg);
557   }
558   OperandMatchResultTy parseAR32(OperandVector &Operands) {
559     return parseRegister(Operands, AR32Reg);
560   }
561   OperandMatchResultTy parseCR64(OperandVector &Operands) {
562     return parseRegister(Operands, CR64Reg);
563   }
564   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
565     return parseAnyRegister(Operands);
566   }
567   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
568     return parseAddress(Operands, BDMem, GR32Reg);
569   }
570   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
571     return parseAddress(Operands, BDMem, GR64Reg);
572   }
573   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
574     return parseAddress(Operands, BDXMem, GR64Reg);
575   }
576   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
577     return parseAddress(Operands, BDLMem, GR64Reg);
578   }
579   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
580     return parseAddress(Operands, BDRMem, GR64Reg);
581   }
582   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
583     return parseAddress(Operands, BDVMem, GR64Reg);
584   }
585   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
586     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
587   }
588   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
589     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
590   }
591   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
592     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
593   }
594   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
595     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
596   }
597   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
598     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
599   }
600   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
601     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
602   }
603 };
604 
605 } // end anonymous namespace
606 
607 #define GET_REGISTER_MATCHER
608 #define GET_SUBTARGET_FEATURE_NAME
609 #define GET_MATCHER_IMPLEMENTATION
610 #define GET_MNEMONIC_SPELL_CHECKER
611 #include "SystemZGenAsmMatcher.inc"
612 
613 // Used for the .insn directives; contains information needed to parse the
614 // operands in the directive.
615 struct InsnMatchEntry {
616   StringRef Format;
617   uint64_t Opcode;
618   int32_t NumOperands;
619   MatchClassKind OperandKinds[7];
620 };
621 
622 // For equal_range comparison.
623 struct CompareInsn {
624   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
625     return LHS.Format < RHS;
626   }
627   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
628     return LHS < RHS.Format;
629   }
630   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
631     return LHS.Format < RHS.Format;
632   }
633 };
634 
635 // Table initializing information for parsing the .insn directive.
636 static struct InsnMatchEntry InsnMatchTable[] = {
637   /* Format, Opcode, NumOperands, OperandKinds */
638   { "e", SystemZ::InsnE, 1,
639     { MCK_U16Imm } },
640   { "ri", SystemZ::InsnRI, 3,
641     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
642   { "rie", SystemZ::InsnRIE, 4,
643     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
644   { "ril", SystemZ::InsnRIL, 3,
645     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
646   { "rilu", SystemZ::InsnRILU, 3,
647     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
648   { "ris", SystemZ::InsnRIS, 5,
649     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
650   { "rr", SystemZ::InsnRR, 3,
651     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
652   { "rre", SystemZ::InsnRRE, 3,
653     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
654   { "rrf", SystemZ::InsnRRF, 5,
655     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
656   { "rrs", SystemZ::InsnRRS, 5,
657     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
658   { "rs", SystemZ::InsnRS, 4,
659     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
660   { "rse", SystemZ::InsnRSE, 4,
661     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
662   { "rsi", SystemZ::InsnRSI, 4,
663     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
664   { "rsy", SystemZ::InsnRSY, 4,
665     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
666   { "rx", SystemZ::InsnRX, 3,
667     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
668   { "rxe", SystemZ::InsnRXE, 3,
669     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
670   { "rxf", SystemZ::InsnRXF, 4,
671     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
672   { "rxy", SystemZ::InsnRXY, 3,
673     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
674   { "s", SystemZ::InsnS, 2,
675     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
676   { "si", SystemZ::InsnSI, 3,
677     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
678   { "sil", SystemZ::InsnSIL, 3,
679     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
680   { "siy", SystemZ::InsnSIY, 3,
681     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
682   { "ss", SystemZ::InsnSS, 4,
683     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
684   { "sse", SystemZ::InsnSSE, 3,
685     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
686   { "ssf", SystemZ::InsnSSF, 4,
687     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
688   { "vri", SystemZ::InsnVRI, 6,
689     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
690   { "vrr", SystemZ::InsnVRR, 7,
691     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
692       MCK_U4Imm } },
693   { "vrs", SystemZ::InsnVRS, 5,
694     { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
695   { "vrv", SystemZ::InsnVRV, 4,
696     { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
697   { "vrx", SystemZ::InsnVRX, 4,
698     { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
699   { "vsi", SystemZ::InsnVSI, 4,
700     { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
701 };
702 
703 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
704   if (!E)
705     return;
706   if (auto *CE = dyn_cast<MCConstantExpr>(E))
707     OS << *CE;
708   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
709     OS << *UE;
710   else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
711     OS << *BE;
712   else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
713     OS << *SRE;
714   else
715     OS << *E;
716 }
717 
718 void SystemZOperand::print(raw_ostream &OS) const {
719   switch (Kind) {
720   case KindToken:
721     OS << "Token:" << getToken();
722     break;
723   case KindReg:
724     OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
725     break;
726   case KindImm:
727     OS << "Imm:";
728     printMCExpr(getImm(), OS);
729     break;
730   case KindImmTLS:
731     OS << "ImmTLS:";
732     printMCExpr(getImmTLS().Imm, OS);
733     if (getImmTLS().Sym) {
734       OS << ", ";
735       printMCExpr(getImmTLS().Sym, OS);
736     }
737     break;
738   case KindMem: {
739     const MemOp &Op = getMem();
740     OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
741     if (Op.Base) {
742       OS << "(";
743       if (Op.MemKind == BDLMem)
744         OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
745       else if (Op.MemKind == BDRMem)
746         OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
747       if (Op.Index)
748         OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
749       OS << SystemZInstPrinter::getRegisterName(Op.Base);
750       OS << ")";
751     }
752     break;
753   }
754   case KindInvalid:
755     break;
756   }
757 }
758 
759 // Parse one register of the form %<prefix><number>.
760 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
761   Reg.StartLoc = Parser.getTok().getLoc();
762 
763   // Eat the % prefix.
764   if (Parser.getTok().isNot(AsmToken::Percent))
765     return Error(Parser.getTok().getLoc(), "register expected");
766   const AsmToken &PercentTok = Parser.getTok();
767   Parser.Lex();
768 
769   // Expect a register name.
770   if (Parser.getTok().isNot(AsmToken::Identifier)) {
771     if (RestoreOnFailure)
772       getLexer().UnLex(PercentTok);
773     return Error(Reg.StartLoc, "invalid register");
774   }
775 
776   // Check that there's a prefix.
777   StringRef Name = Parser.getTok().getString();
778   if (Name.size() < 2) {
779     if (RestoreOnFailure)
780       getLexer().UnLex(PercentTok);
781     return Error(Reg.StartLoc, "invalid register");
782   }
783   char Prefix = Name[0];
784 
785   // Treat the rest of the register name as a register number.
786   if (Name.substr(1).getAsInteger(10, Reg.Num)) {
787     if (RestoreOnFailure)
788       getLexer().UnLex(PercentTok);
789     return Error(Reg.StartLoc, "invalid register");
790   }
791 
792   // Look for valid combinations of prefix and number.
793   if (Prefix == 'r' && Reg.Num < 16)
794     Reg.Group = RegGR;
795   else if (Prefix == 'f' && Reg.Num < 16)
796     Reg.Group = RegFP;
797   else if (Prefix == 'v' && Reg.Num < 32)
798     Reg.Group = RegV;
799   else if (Prefix == 'a' && Reg.Num < 16)
800     Reg.Group = RegAR;
801   else if (Prefix == 'c' && Reg.Num < 16)
802     Reg.Group = RegCR;
803   else {
804     if (RestoreOnFailure)
805       getLexer().UnLex(PercentTok);
806     return Error(Reg.StartLoc, "invalid register");
807   }
808 
809   Reg.EndLoc = Parser.getTok().getLoc();
810   Parser.Lex();
811   return false;
812 }
813 
814 // Parse a register of kind Kind and add it to Operands.
815 OperandMatchResultTy
816 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
817   Register Reg;
818   RegisterGroup Group;
819   switch (Kind) {
820   case GR32Reg:
821   case GRH32Reg:
822   case GR64Reg:
823   case GR128Reg:
824     Group = RegGR;
825     break;
826   case FP32Reg:
827   case FP64Reg:
828   case FP128Reg:
829     Group = RegFP;
830     break;
831   case VR32Reg:
832   case VR64Reg:
833   case VR128Reg:
834     Group = RegV;
835     break;
836   case AR32Reg:
837     Group = RegAR;
838     break;
839   case CR64Reg:
840     Group = RegCR;
841     break;
842   }
843 
844   // Handle register names of the form %<prefix><number>
845   if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
846     if (parseRegister(Reg))
847       return MatchOperand_ParseFail;
848 
849     // Check the parsed register group "Reg.Group" with the expected "Group"
850     // Have to error out if user specified wrong prefix.
851     switch (Group) {
852     case RegGR:
853     case RegFP:
854     case RegAR:
855     case RegCR:
856       if (Group != Reg.Group) {
857         Error(Reg.StartLoc, "invalid operand for instruction");
858         return MatchOperand_ParseFail;
859       }
860       break;
861     case RegV:
862       if (Reg.Group != RegV && Reg.Group != RegFP) {
863         Error(Reg.StartLoc, "invalid operand for instruction");
864         return MatchOperand_ParseFail;
865       }
866       break;
867     }
868   } else if (Parser.getTok().is(AsmToken::Integer)) {
869     if (parseIntegerRegister(Reg, Group))
870       return MatchOperand_ParseFail;
871   }
872   // Otherwise we didn't match a register operand.
873   else
874     return MatchOperand_NoMatch;
875 
876   // Determine the LLVM register number according to Kind.
877   const unsigned *Regs;
878   switch (Kind) {
879   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
880   case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
881   case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
882   case GR128Reg: Regs = SystemZMC::GR128Regs; break;
883   case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
884   case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
885   case FP128Reg: Regs = SystemZMC::FP128Regs; break;
886   case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
887   case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
888   case VR128Reg: Regs = SystemZMC::VR128Regs; break;
889   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
890   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
891   }
892   if (Regs[Reg.Num] == 0) {
893     Error(Reg.StartLoc, "invalid register pair");
894     return MatchOperand_ParseFail;
895   }
896 
897   Operands.push_back(
898       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
899   return MatchOperand_Success;
900 }
901 
902 // Parse any type of register (including integers) and add it to Operands.
903 OperandMatchResultTy
904 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
905   SMLoc StartLoc = Parser.getTok().getLoc();
906 
907   // Handle integer values.
908   if (Parser.getTok().is(AsmToken::Integer)) {
909     const MCExpr *Register;
910     if (Parser.parseExpression(Register))
911       return MatchOperand_ParseFail;
912 
913     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
914       int64_t Value = CE->getValue();
915       if (Value < 0 || Value > 15) {
916         Error(StartLoc, "invalid register");
917         return MatchOperand_ParseFail;
918       }
919     }
920 
921     SMLoc EndLoc =
922       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
923 
924     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
925   }
926   else {
927     if (isParsingHLASM())
928       return MatchOperand_NoMatch;
929 
930     Register Reg;
931     if (parseRegister(Reg))
932       return MatchOperand_ParseFail;
933 
934     if (Reg.Num > 15) {
935       Error(StartLoc, "invalid register");
936       return MatchOperand_ParseFail;
937     }
938 
939     // Map to the correct register kind.
940     RegisterKind Kind;
941     unsigned RegNo;
942     if (Reg.Group == RegGR) {
943       Kind = GR64Reg;
944       RegNo = SystemZMC::GR64Regs[Reg.Num];
945     }
946     else if (Reg.Group == RegFP) {
947       Kind = FP64Reg;
948       RegNo = SystemZMC::FP64Regs[Reg.Num];
949     }
950     else if (Reg.Group == RegV) {
951       Kind = VR128Reg;
952       RegNo = SystemZMC::VR128Regs[Reg.Num];
953     }
954     else if (Reg.Group == RegAR) {
955       Kind = AR32Reg;
956       RegNo = SystemZMC::AR32Regs[Reg.Num];
957     }
958     else if (Reg.Group == RegCR) {
959       Kind = CR64Reg;
960       RegNo = SystemZMC::CR64Regs[Reg.Num];
961     }
962     else {
963       return MatchOperand_ParseFail;
964     }
965 
966     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
967                                                  Reg.StartLoc, Reg.EndLoc));
968   }
969   return MatchOperand_Success;
970 }
971 
972 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
973                                             RegisterGroup Group) {
974   Reg.StartLoc = Parser.getTok().getLoc();
975   // We have an integer token
976   const MCExpr *Register;
977   if (Parser.parseExpression(Register))
978     return true;
979 
980   const auto *CE = dyn_cast<MCConstantExpr>(Register);
981   if (!CE)
982     return true;
983 
984   int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
985   int64_t Value = CE->getValue();
986   if (Value < 0 || Value > MaxRegNum) {
987     Error(Parser.getTok().getLoc(), "invalid register");
988     return true;
989   }
990 
991   // Assign the Register Number
992   Reg.Num = (unsigned)Value;
993   Reg.Group = Group;
994   Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
995 
996   // At this point, successfully parsed an integer register.
997   return false;
998 }
999 
1000 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
1001 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
1002                                     bool &HaveReg2, Register &Reg2,
1003                                     const MCExpr *&Disp, const MCExpr *&Length,
1004                                     bool HasLength, bool HasVectorIndex) {
1005   // Parse the displacement, which must always be present.
1006   if (getParser().parseExpression(Disp))
1007     return true;
1008 
1009   // Parse the optional base and index.
1010   HaveReg1 = false;
1011   HaveReg2 = false;
1012   Length = nullptr;
1013 
1014   // If we have a scenario as below:
1015   //   vgef %v0, 0(0), 0
1016   // This is an example of a "BDVMem" instruction type.
1017   //
1018   // So when we parse this as an integer register, the register group
1019   // needs to be tied to "RegV". Usually when the prefix is passed in
1020   // as %<prefix><reg-number> its easy to check which group it should belong to
1021   // However, if we're passing in just the integer there's no real way to
1022   // "check" what register group it should belong to.
1023   //
1024   // When the user passes in the register as an integer, the user assumes that
1025   // the compiler is responsible for substituting it as the right kind of
1026   // register. Whereas, when the user specifies a "prefix", the onus is on
1027   // the user to make sure they pass in the right kind of register.
1028   //
1029   // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1030   // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1031   // (i.e. insn is of type BDVMem) is true.
1032   RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
1033 
1034   if (getLexer().is(AsmToken::LParen)) {
1035     Parser.Lex();
1036 
1037     if (isParsingATT() && getLexer().is(AsmToken::Percent)) {
1038       // Parse the first register.
1039       HaveReg1 = true;
1040       if (parseRegister(Reg1))
1041         return true;
1042     }
1043     // So if we have an integer as the first token in ([tok1], ..), it could:
1044     // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
1045     // instructions)
1046     // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
1047     else if (getLexer().is(AsmToken::Integer)) {
1048       if (HasLength) {
1049         // Instruction has a "Length" field, safe to parse the first token as
1050         // the "Length" field
1051         if (getParser().parseExpression(Length))
1052           return true;
1053       } else {
1054         // Otherwise, if the instruction has no "Length" field, parse the
1055         // token as a "Register". We don't have to worry about whether the
1056         // instruction is invalid here, because the caller will take care of
1057         // error reporting.
1058         HaveReg1 = true;
1059         if (parseIntegerRegister(Reg1, RegGroup))
1060           return true;
1061       }
1062     } else {
1063       // If its not an integer or a percent token, then if the instruction
1064       // is reported to have a "Length" then, parse it as "Length".
1065       if (HasLength) {
1066         if (getParser().parseExpression(Length))
1067           return true;
1068       }
1069     }
1070 
1071     // Check whether there's a second register.
1072     if (getLexer().is(AsmToken::Comma)) {
1073       Parser.Lex();
1074       HaveReg2 = true;
1075 
1076       if (getLexer().is(AsmToken::Integer)) {
1077         if (parseIntegerRegister(Reg2, RegGR))
1078           return true;
1079       } else {
1080         if (isParsingATT() && parseRegister(Reg2))
1081           return true;
1082       }
1083     }
1084 
1085     // Consume the closing bracket.
1086     if (getLexer().isNot(AsmToken::RParen))
1087       return Error(Parser.getTok().getLoc(), "unexpected token in address");
1088     Parser.Lex();
1089   }
1090   return false;
1091 }
1092 
1093 // Verify that Reg is a valid address register (base or index).
1094 bool
1095 SystemZAsmParser::parseAddressRegister(Register &Reg) {
1096   if (Reg.Group == RegV) {
1097     Error(Reg.StartLoc, "invalid use of vector addressing");
1098     return true;
1099   } else if (Reg.Group != RegGR) {
1100     Error(Reg.StartLoc, "invalid address register");
1101     return true;
1102   }
1103   return false;
1104 }
1105 
1106 // Parse a memory operand and add it to Operands.  The other arguments
1107 // are as above.
1108 OperandMatchResultTy
1109 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1110                                RegisterKind RegKind) {
1111   SMLoc StartLoc = Parser.getTok().getLoc();
1112   unsigned Base = 0, Index = 0, LengthReg = 0;
1113   Register Reg1, Reg2;
1114   bool HaveReg1, HaveReg2;
1115   const MCExpr *Disp;
1116   const MCExpr *Length;
1117 
1118   bool HasLength = (MemKind == BDLMem) ? true : false;
1119   bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1120   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1121                    HasVectorIndex))
1122     return MatchOperand_ParseFail;
1123 
1124   const unsigned *Regs;
1125   switch (RegKind) {
1126   case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1127   case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1128   default: llvm_unreachable("invalid RegKind");
1129   }
1130 
1131   switch (MemKind) {
1132   case BDMem:
1133     // If we have Reg1, it must be an address register.
1134     if (HaveReg1) {
1135       if (parseAddressRegister(Reg1))
1136         return MatchOperand_ParseFail;
1137       Base = Regs[Reg1.Num];
1138     }
1139     // There must be no Reg2.
1140     if (HaveReg2) {
1141       Error(StartLoc, "invalid use of indexed addressing");
1142       return MatchOperand_ParseFail;
1143     }
1144     break;
1145   case BDXMem:
1146     // If we have Reg1, it must be an address register.
1147     if (HaveReg1) {
1148       if (parseAddressRegister(Reg1))
1149         return MatchOperand_ParseFail;
1150       // If the are two registers, the first one is the index and the
1151       // second is the base.
1152       if (HaveReg2)
1153         Index = Regs[Reg1.Num];
1154       else
1155         Base = Regs[Reg1.Num];
1156     }
1157     // If we have Reg2, it must be an address register.
1158     if (HaveReg2) {
1159       if (parseAddressRegister(Reg2))
1160         return MatchOperand_ParseFail;
1161       Base = Regs[Reg2.Num];
1162     }
1163     break;
1164   case BDLMem:
1165     // If we have Reg2, it must be an address register.
1166     if (HaveReg2) {
1167       if (parseAddressRegister(Reg2))
1168         return MatchOperand_ParseFail;
1169       Base = Regs[Reg2.Num];
1170     }
1171     // We cannot support base+index addressing.
1172     if (HaveReg1 && HaveReg2) {
1173       Error(StartLoc, "invalid use of indexed addressing");
1174       return MatchOperand_ParseFail;
1175     }
1176     // We must have a length.
1177     if (!Length) {
1178       Error(StartLoc, "missing length in address");
1179       return MatchOperand_ParseFail;
1180     }
1181     break;
1182   case BDRMem:
1183     // We must have Reg1, and it must be a GPR.
1184     if (!HaveReg1 || Reg1.Group != RegGR) {
1185       Error(StartLoc, "invalid operand for instruction");
1186       return MatchOperand_ParseFail;
1187     }
1188     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1189     // If we have Reg2, it must be an address register.
1190     if (HaveReg2) {
1191       if (parseAddressRegister(Reg2))
1192         return MatchOperand_ParseFail;
1193       Base = Regs[Reg2.Num];
1194     }
1195     break;
1196   case BDVMem:
1197     // We must have Reg1, and it must be a vector register.
1198     if (!HaveReg1 || Reg1.Group != RegV) {
1199       Error(StartLoc, "vector index required in address");
1200       return MatchOperand_ParseFail;
1201     }
1202     Index = SystemZMC::VR128Regs[Reg1.Num];
1203     // If we have Reg2, it must be an address register.
1204     if (HaveReg2) {
1205       if (parseAddressRegister(Reg2))
1206         return MatchOperand_ParseFail;
1207       Base = Regs[Reg2.Num];
1208     }
1209     break;
1210   }
1211 
1212   SMLoc EndLoc =
1213       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1214   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1215                                                Index, Length, LengthReg,
1216                                                StartLoc, EndLoc));
1217   return MatchOperand_Success;
1218 }
1219 
1220 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1221   StringRef IDVal = DirectiveID.getIdentifier();
1222 
1223   if (IDVal == ".insn")
1224     return ParseDirectiveInsn(DirectiveID.getLoc());
1225   if (IDVal == ".machine")
1226     return ParseDirectiveMachine(DirectiveID.getLoc());
1227 
1228   return true;
1229 }
1230 
1231 /// ParseDirectiveInsn
1232 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1233 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1234   MCAsmParser &Parser = getParser();
1235 
1236   // Expect instruction format as identifier.
1237   StringRef Format;
1238   SMLoc ErrorLoc = Parser.getTok().getLoc();
1239   if (Parser.parseIdentifier(Format))
1240     return Error(ErrorLoc, "expected instruction format");
1241 
1242   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1243 
1244   // Find entry for this format in InsnMatchTable.
1245   auto EntryRange =
1246     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1247                      Format, CompareInsn());
1248 
1249   // If first == second, couldn't find a match in the table.
1250   if (EntryRange.first == EntryRange.second)
1251     return Error(ErrorLoc, "unrecognized format");
1252 
1253   struct InsnMatchEntry *Entry = EntryRange.first;
1254 
1255   // Format should match from equal_range.
1256   assert(Entry->Format == Format);
1257 
1258   // Parse the following operands using the table's information.
1259   for (int i = 0; i < Entry->NumOperands; i++) {
1260     MatchClassKind Kind = Entry->OperandKinds[i];
1261 
1262     SMLoc StartLoc = Parser.getTok().getLoc();
1263 
1264     // Always expect commas as separators for operands.
1265     if (getLexer().isNot(AsmToken::Comma))
1266       return Error(StartLoc, "unexpected token in directive");
1267     Lex();
1268 
1269     // Parse operands.
1270     OperandMatchResultTy ResTy;
1271     if (Kind == MCK_AnyReg)
1272       ResTy = parseAnyReg(Operands);
1273     else if (Kind == MCK_VR128)
1274       ResTy = parseVR128(Operands);
1275     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1276       ResTy = parseBDXAddr64(Operands);
1277     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1278       ResTy = parseBDAddr64(Operands);
1279     else if (Kind == MCK_BDVAddr64Disp12)
1280       ResTy = parseBDVAddr64(Operands);
1281     else if (Kind == MCK_PCRel32)
1282       ResTy = parsePCRel32(Operands);
1283     else if (Kind == MCK_PCRel16)
1284       ResTy = parsePCRel16(Operands);
1285     else {
1286       // Only remaining operand kind is an immediate.
1287       const MCExpr *Expr;
1288       SMLoc StartLoc = Parser.getTok().getLoc();
1289 
1290       // Expect immediate expression.
1291       if (Parser.parseExpression(Expr))
1292         return Error(StartLoc, "unexpected token in directive");
1293 
1294       SMLoc EndLoc =
1295         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1296 
1297       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1298       ResTy = MatchOperand_Success;
1299     }
1300 
1301     if (ResTy != MatchOperand_Success)
1302       return true;
1303   }
1304 
1305   // Build the instruction with the parsed operands.
1306   MCInst Inst = MCInstBuilder(Entry->Opcode);
1307 
1308   for (size_t i = 0; i < Operands.size(); i++) {
1309     MCParsedAsmOperand &Operand = *Operands[i];
1310     MatchClassKind Kind = Entry->OperandKinds[i];
1311 
1312     // Verify operand.
1313     unsigned Res = validateOperandClass(Operand, Kind);
1314     if (Res != Match_Success)
1315       return Error(Operand.getStartLoc(), "unexpected operand type");
1316 
1317     // Add operands to instruction.
1318     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1319     if (ZOperand.isReg())
1320       ZOperand.addRegOperands(Inst, 1);
1321     else if (ZOperand.isMem(BDMem))
1322       ZOperand.addBDAddrOperands(Inst, 2);
1323     else if (ZOperand.isMem(BDXMem))
1324       ZOperand.addBDXAddrOperands(Inst, 3);
1325     else if (ZOperand.isMem(BDVMem))
1326       ZOperand.addBDVAddrOperands(Inst, 3);
1327     else if (ZOperand.isImm())
1328       ZOperand.addImmOperands(Inst, 1);
1329     else
1330       llvm_unreachable("unexpected operand type");
1331   }
1332 
1333   // Emit as a regular instruction.
1334   Parser.getStreamer().emitInstruction(Inst, getSTI());
1335 
1336   return false;
1337 }
1338 
1339 /// ParseDirectiveMachine
1340 /// ::= .machine [ mcpu ]
1341 bool SystemZAsmParser::ParseDirectiveMachine(SMLoc L) {
1342   MCAsmParser &Parser = getParser();
1343   if (Parser.getTok().isNot(AsmToken::Identifier) &&
1344       Parser.getTok().isNot(AsmToken::String))
1345     return Error(L, "unexpected token in '.machine' directive");
1346 
1347   StringRef CPU = Parser.getTok().getIdentifier();
1348   Parser.Lex();
1349   if (parseToken(AsmToken::EndOfStatement))
1350     return addErrorSuffix(" in '.machine' directive");
1351 
1352   MCSubtargetInfo &STI = copySTI();
1353   STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
1354   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
1355 
1356   getTargetStreamer().emitMachine(CPU);
1357 
1358   return false;
1359 }
1360 
1361 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1362                                      SMLoc &EndLoc, bool RestoreOnFailure) {
1363   Register Reg;
1364   if (parseRegister(Reg, RestoreOnFailure))
1365     return true;
1366   if (Reg.Group == RegGR)
1367     RegNo = SystemZMC::GR64Regs[Reg.Num];
1368   else if (Reg.Group == RegFP)
1369     RegNo = SystemZMC::FP64Regs[Reg.Num];
1370   else if (Reg.Group == RegV)
1371     RegNo = SystemZMC::VR128Regs[Reg.Num];
1372   else if (Reg.Group == RegAR)
1373     RegNo = SystemZMC::AR32Regs[Reg.Num];
1374   else if (Reg.Group == RegCR)
1375     RegNo = SystemZMC::CR64Regs[Reg.Num];
1376   StartLoc = Reg.StartLoc;
1377   EndLoc = Reg.EndLoc;
1378   return false;
1379 }
1380 
1381 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1382                                      SMLoc &EndLoc) {
1383   return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1384 }
1385 
1386 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1387                                                         SMLoc &StartLoc,
1388                                                         SMLoc &EndLoc) {
1389   bool Result =
1390       ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1391   bool PendingErrors = getParser().hasPendingError();
1392   getParser().clearPendingErrors();
1393   if (PendingErrors)
1394     return MatchOperand_ParseFail;
1395   if (Result)
1396     return MatchOperand_NoMatch;
1397   return MatchOperand_Success;
1398 }
1399 
1400 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1401                                         StringRef Name, SMLoc NameLoc,
1402                                         OperandVector &Operands) {
1403 
1404   // Apply mnemonic aliases first, before doing anything else, in
1405   // case the target uses it.
1406   applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
1407 
1408   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1409 
1410   // Read the remaining operands.
1411   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1412     // Read the first operand.
1413     if (parseOperand(Operands, Name)) {
1414       return true;
1415     }
1416 
1417     // Read any subsequent operands.
1418     while (getLexer().is(AsmToken::Comma)) {
1419       Parser.Lex();
1420 
1421       if (isParsingHLASM() && getLexer().is(AsmToken::Space))
1422         return Error(
1423             Parser.getTok().getLoc(),
1424             "No space allowed between comma that separates operand entries");
1425 
1426       if (parseOperand(Operands, Name)) {
1427         return true;
1428       }
1429     }
1430 
1431     // Under the HLASM variant, we could have the remark field
1432     // The remark field occurs after the operation entries
1433     // There is a space that separates the operation entries and the
1434     // remark field.
1435     if (isParsingHLASM() && getTok().is(AsmToken::Space)) {
1436       // We've confirmed that there is a Remark field.
1437       StringRef Remark(getLexer().LexUntilEndOfStatement());
1438       Parser.Lex();
1439 
1440       // If there is nothing after the space, then there is nothing to emit
1441       // We could have a situation as this:
1442       // "  \n"
1443       // After lexing above, we will have
1444       // "\n"
1445       // This isn't an explicit remark field, so we don't have to output
1446       // this as a comment.
1447       if (Remark.size())
1448         // Output the entire Remarks Field as a comment
1449         getStreamer().AddComment(Remark);
1450     }
1451 
1452     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1453       SMLoc Loc = getLexer().getLoc();
1454       return Error(Loc, "unexpected token in argument list");
1455     }
1456   }
1457 
1458   // Consume the EndOfStatement.
1459   Parser.Lex();
1460   return false;
1461 }
1462 
1463 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1464                                     StringRef Mnemonic) {
1465   // Check if the current operand has a custom associated parser, if so, try to
1466   // custom parse the operand, or fallback to the general approach.  Force all
1467   // features to be available during the operand check, or else we will fail to
1468   // find the custom parser, and then we will later get an InvalidOperand error
1469   // instead of a MissingFeature errror.
1470   FeatureBitset AvailableFeatures = getAvailableFeatures();
1471   FeatureBitset All;
1472   All.set();
1473   setAvailableFeatures(All);
1474   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1475   setAvailableFeatures(AvailableFeatures);
1476   if (ResTy == MatchOperand_Success)
1477     return false;
1478 
1479   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1480   // there was a match, but an error occurred, in which case, just return that
1481   // the operand parsing failed.
1482   if (ResTy == MatchOperand_ParseFail)
1483     return true;
1484 
1485   // Check for a register.  All real register operands should have used
1486   // a context-dependent parse routine, which gives the required register
1487   // class.  The code is here to mop up other cases, like those where
1488   // the instruction isn't recognized.
1489   if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
1490     Register Reg;
1491     if (parseRegister(Reg))
1492       return true;
1493     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1494     return false;
1495   }
1496 
1497   // The only other type of operand is an immediate or address.  As above,
1498   // real address operands should have used a context-dependent parse routine,
1499   // so we treat any plain expression as an immediate.
1500   SMLoc StartLoc = Parser.getTok().getLoc();
1501   Register Reg1, Reg2;
1502   bool HaveReg1, HaveReg2;
1503   const MCExpr *Expr;
1504   const MCExpr *Length;
1505   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1506                    /*HasLength*/ true, /*HasVectorIndex*/ true))
1507     return true;
1508   // If the register combination is not valid for any instruction, reject it.
1509   // Otherwise, fall back to reporting an unrecognized instruction.
1510   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1511       && parseAddressRegister(Reg1))
1512     return true;
1513   if (HaveReg2 && parseAddressRegister(Reg2))
1514     return true;
1515 
1516   SMLoc EndLoc =
1517     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1518   if (HaveReg1 || HaveReg2 || Length)
1519     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1520   else
1521     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1522   return false;
1523 }
1524 
1525 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1526                                                OperandVector &Operands,
1527                                                MCStreamer &Out,
1528                                                uint64_t &ErrorInfo,
1529                                                bool MatchingInlineAsm) {
1530   MCInst Inst;
1531   unsigned MatchResult;
1532 
1533   unsigned Dialect = getMAIAssemblerDialect();
1534 
1535   FeatureBitset MissingFeatures;
1536   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
1537                                      MatchingInlineAsm, Dialect);
1538   switch (MatchResult) {
1539   case Match_Success:
1540     Inst.setLoc(IDLoc);
1541     Out.emitInstruction(Inst, getSTI());
1542     return false;
1543 
1544   case Match_MissingFeature: {
1545     assert(MissingFeatures.any() && "Unknown missing feature!");
1546     // Special case the error message for the very common case where only
1547     // a single subtarget feature is missing
1548     std::string Msg = "instruction requires:";
1549     for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1550       if (MissingFeatures[I]) {
1551         Msg += " ";
1552         Msg += getSubtargetFeatureName(I);
1553       }
1554     }
1555     return Error(IDLoc, Msg);
1556   }
1557 
1558   case Match_InvalidOperand: {
1559     SMLoc ErrorLoc = IDLoc;
1560     if (ErrorInfo != ~0ULL) {
1561       if (ErrorInfo >= Operands.size())
1562         return Error(IDLoc, "too few operands for instruction");
1563 
1564       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1565       if (ErrorLoc == SMLoc())
1566         ErrorLoc = IDLoc;
1567     }
1568     return Error(ErrorLoc, "invalid operand for instruction");
1569   }
1570 
1571   case Match_MnemonicFail: {
1572     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1573     std::string Suggestion = SystemZMnemonicSpellCheck(
1574         ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
1575     return Error(IDLoc, "invalid instruction" + Suggestion,
1576                  ((SystemZOperand &)*Operands[0]).getLocRange());
1577   }
1578   }
1579 
1580   llvm_unreachable("Unexpected match type");
1581 }
1582 
1583 OperandMatchResultTy
1584 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1585                              int64_t MaxVal, bool AllowTLS) {
1586   MCContext &Ctx = getContext();
1587   MCStreamer &Out = getStreamer();
1588   const MCExpr *Expr;
1589   SMLoc StartLoc = Parser.getTok().getLoc();
1590   if (getParser().parseExpression(Expr))
1591     return MatchOperand_NoMatch;
1592 
1593   auto isOutOfRangeConstant = [&](const MCExpr *E, bool Negate) -> bool {
1594     if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1595       int64_t Value = CE->getValue();
1596       if (Negate)
1597         Value = -Value;
1598       if ((Value & 1) || Value < MinVal || Value > MaxVal)
1599         return true;
1600     }
1601     return false;
1602   };
1603 
1604   // For consistency with the GNU assembler, treat immediates as offsets
1605   // from ".".
1606   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1607     if (isParsingHLASM()) {
1608       Error(StartLoc, "Expected PC-relative expression");
1609       return MatchOperand_ParseFail;
1610     }
1611     if (isOutOfRangeConstant(CE, false)) {
1612       Error(StartLoc, "offset out of range");
1613       return MatchOperand_ParseFail;
1614     }
1615     int64_t Value = CE->getValue();
1616     MCSymbol *Sym = Ctx.createTempSymbol();
1617     Out.emitLabel(Sym);
1618     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1619                                                  Ctx);
1620     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1621   }
1622 
1623   // For consistency with the GNU assembler, conservatively assume that a
1624   // constant offset must by itself be within the given size range.
1625   if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1626     if (isOutOfRangeConstant(BE->getLHS(), false) ||
1627         isOutOfRangeConstant(BE->getRHS(),
1628                              BE->getOpcode() == MCBinaryExpr::Sub)) {
1629       Error(StartLoc, "offset out of range");
1630       return MatchOperand_ParseFail;
1631     }
1632 
1633   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1634   const MCExpr *Sym = nullptr;
1635   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1636     Parser.Lex();
1637 
1638     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1639       Error(Parser.getTok().getLoc(), "unexpected token");
1640       return MatchOperand_ParseFail;
1641     }
1642 
1643     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1644     StringRef Name = Parser.getTok().getString();
1645     if (Name == "tls_gdcall")
1646       Kind = MCSymbolRefExpr::VK_TLSGD;
1647     else if (Name == "tls_ldcall")
1648       Kind = MCSymbolRefExpr::VK_TLSLDM;
1649     else {
1650       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1651       return MatchOperand_ParseFail;
1652     }
1653     Parser.Lex();
1654 
1655     if (Parser.getTok().isNot(AsmToken::Colon)) {
1656       Error(Parser.getTok().getLoc(), "unexpected token");
1657       return MatchOperand_ParseFail;
1658     }
1659     Parser.Lex();
1660 
1661     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1662       Error(Parser.getTok().getLoc(), "unexpected token");
1663       return MatchOperand_ParseFail;
1664     }
1665 
1666     StringRef Identifier = Parser.getTok().getString();
1667     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1668                                   Kind, Ctx);
1669     Parser.Lex();
1670   }
1671 
1672   SMLoc EndLoc =
1673     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1674 
1675   if (AllowTLS)
1676     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1677                                                     StartLoc, EndLoc));
1678   else
1679     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1680 
1681   return MatchOperand_Success;
1682 }
1683 
1684 bool SystemZAsmParser::isLabel(AsmToken &Token) {
1685   if (isParsingATT())
1686     return true;
1687 
1688   // HLASM labels are ordinary symbols.
1689   // An HLASM label always starts at column 1.
1690   // An ordinary symbol syntax is laid out as follows:
1691   // Rules:
1692   // 1. Has to start with an "alphabetic character". Can be followed by up to
1693   //    62 alphanumeric characters. An "alphabetic character", in this scenario,
1694   //    is a letter from 'A' through 'Z', or from 'a' through 'z',
1695   //    or '$', '_', '#', or '@'
1696   // 2. Labels are case-insensitive. E.g. "lab123", "LAB123", "lAb123", etc.
1697   //    are all treated as the same symbol. However, the processing for the case
1698   //    folding will not be done in this function.
1699   StringRef RawLabel = Token.getString();
1700   SMLoc Loc = Token.getLoc();
1701 
1702   // An HLASM label cannot be empty.
1703   if (!RawLabel.size())
1704     return !Error(Loc, "HLASM Label cannot be empty");
1705 
1706   // An HLASM label cannot exceed greater than 63 characters.
1707   if (RawLabel.size() > 63)
1708     return !Error(Loc, "Maximum length for HLASM Label is 63 characters");
1709 
1710   // A label must start with an "alphabetic character".
1711   if (!isHLASMAlpha(RawLabel[0]))
1712     return !Error(Loc, "HLASM Label has to start with an alphabetic "
1713                        "character or the underscore character");
1714 
1715   // Now, we've established that the length is valid
1716   // and the first character is alphabetic.
1717   // Check whether remaining string is alphanumeric.
1718   for (unsigned I = 1; I < RawLabel.size(); ++I)
1719     if (!isHLASMAlnum(RawLabel[I]))
1720       return !Error(Loc, "HLASM Label has to be alphanumeric");
1721 
1722   return true;
1723 }
1724 
1725 // Force static initialization.
1726 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() {
1727   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1728 }
1729