1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 
16 #include "SystemZ.h"
17 #include "SystemZRegisterInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include <cstdint>
24 
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class SystemZSubtarget;
31 
32 namespace SystemZII {
33 
34 enum {
35   // See comments in SystemZInstrFormats.td.
36   SimpleBDXLoad          = (1 << 0),
37   SimpleBDXStore         = (1 << 1),
38   Has20BitOffset         = (1 << 2),
39   HasIndex               = (1 << 3),
40   Is128Bit               = (1 << 4),
41   AccessSizeMask         = (31 << 5),
42   AccessSizeShift        = 5,
43   CCValuesMask           = (15 << 10),
44   CCValuesShift          = 10,
45   CompareZeroCCMaskMask  = (15 << 14),
46   CompareZeroCCMaskShift = 14,
47   CCMaskFirst            = (1 << 18),
48   CCMaskLast             = (1 << 19),
49   IsLogical              = (1 << 20),
50   CCIfNoSignedWrap       = (1 << 21),
51   MemMemOp               = (1 << 22)
52 };
53 
54 static inline unsigned getAccessSize(unsigned int Flags) {
55   return (Flags & AccessSizeMask) >> AccessSizeShift;
56 }
57 
58 static inline unsigned getCCValues(unsigned int Flags) {
59   return (Flags & CCValuesMask) >> CCValuesShift;
60 }
61 
62 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
63   return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
64 }
65 
66 // SystemZ MachineOperand target flags.
67 enum {
68   // Masks out the bits for the access model.
69   MO_SYMBOL_MODIFIER = (3 << 0),
70 
71   // @GOT (aka @GOTENT)
72   MO_GOT = (1 << 0),
73 
74   // @INDNTPOFF
75   MO_INDNTPOFF = (2 << 0)
76 };
77 
78 // Classifies a branch.
79 enum BranchType {
80   // An instruction that branches on the current value of CC.
81   BranchNormal,
82 
83   // An instruction that peforms a 32-bit signed comparison and branches
84   // on the result.
85   BranchC,
86 
87   // An instruction that peforms a 32-bit unsigned comparison and branches
88   // on the result.
89   BranchCL,
90 
91   // An instruction that peforms a 64-bit signed comparison and branches
92   // on the result.
93   BranchCG,
94 
95   // An instruction that peforms a 64-bit unsigned comparison and branches
96   // on the result.
97   BranchCLG,
98 
99   // An instruction that decrements a 32-bit register and branches if
100   // the result is nonzero.
101   BranchCT,
102 
103   // An instruction that decrements a 64-bit register and branches if
104   // the result is nonzero.
105   BranchCTG,
106 
107   // An instruction representing an asm goto statement.
108   AsmGoto
109 };
110 
111 // Information about a branch instruction.
112 class Branch {
113   // The target of the branch. In case of INLINEASM_BR, this is nullptr.
114   const MachineOperand *Target;
115 
116 public:
117   // The type of the branch.
118   BranchType Type;
119 
120   // CCMASK_<N> is set if CC might be equal to N.
121   unsigned CCValid;
122 
123   // CCMASK_<N> is set if the branch should be taken when CC == N.
124   unsigned CCMask;
125 
126   Branch(BranchType type, unsigned ccValid, unsigned ccMask,
127          const MachineOperand *target)
128     : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {}
129 
130   bool isIndirect() { return Target != nullptr && Target->isReg(); }
131   bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }
132   MachineBasicBlock *getMBBTarget() {
133     return hasMBBTarget() ? Target->getMBB() : nullptr;
134   }
135 };
136 
137 // Kinds of fused compares in compare-and-* instructions.  Together with type
138 // of the converted compare, this identifies the compare-and-*
139 // instruction.
140 enum FusedCompareType {
141   // Relative branch - CRJ etc.
142   CompareAndBranch,
143 
144   // Indirect branch, used for return - CRBReturn etc.
145   CompareAndReturn,
146 
147   // Indirect branch, used for sibcall - CRBCall etc.
148   CompareAndSibcall,
149 
150   // Trap
151   CompareAndTrap
152 };
153 
154 } // end namespace SystemZII
155 
156 namespace SystemZ {
157 int getTwoOperandOpcode(uint16_t Opcode);
158 int getTargetMemOpcode(uint16_t Opcode);
159 
160 // Return a version of comparison CC mask CCMask in which the LT and GT
161 // actions are swapped.
162 unsigned reverseCCMask(unsigned CCMask);
163 
164 // Create a new basic block after MBB.
165 MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB);
166 // Split MBB after MI and return the new block (the one that contains
167 // instructions after MI).
168 MachineBasicBlock *splitBlockAfter(MachineBasicBlock::iterator MI,
169                                    MachineBasicBlock *MBB);
170 // Split MBB before MI and return the new block (the one that contains MI).
171 MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI,
172                                     MachineBasicBlock *MBB);
173 }
174 
175 class SystemZInstrInfo : public SystemZGenInstrInfo {
176   const SystemZRegisterInfo RI;
177   SystemZSubtarget &STI;
178 
179   void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
180   void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
181   void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
182                       bool ConvertHigh) const;
183   void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
184                        unsigned LowOpcodeK, unsigned HighOpcode) const;
185   void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
186                        unsigned HighOpcode) const;
187   void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
188                        unsigned HighOpcode) const;
189   void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
190                         unsigned Size) const;
191   void expandLoadStackGuard(MachineInstr *MI) const;
192 
193   MachineInstrBuilder
194   emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
195                 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
196                 unsigned LowLowOpcode, unsigned Size, bool KillSrc,
197                 bool UndefSrc) const;
198 
199   virtual void anchor();
200 
201 protected:
202   /// Commutes the operands in the given instruction by changing the operands
203   /// order and/or changing the instruction's opcode and/or the immediate value
204   /// operand.
205   ///
206   /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
207   /// to be commuted.
208   ///
209   /// Do not call this method for a non-commutable instruction or
210   /// non-commutable operands.
211   /// Even though the instruction is commutable, the method may still
212   /// fail to commute the operands, null pointer is returned in such cases.
213   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
214                                        unsigned CommuteOpIdx1,
215                                        unsigned CommuteOpIdx2) const override;
216 
217 public:
218   explicit SystemZInstrInfo(SystemZSubtarget &STI);
219 
220   // Override TargetInstrInfo.
221   unsigned isLoadFromStackSlot(const MachineInstr &MI,
222                                int &FrameIndex) const override;
223   unsigned isStoreToStackSlot(const MachineInstr &MI,
224                               int &FrameIndex) const override;
225   bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
226                        int &SrcFrameIndex) const override;
227   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
228                      MachineBasicBlock *&FBB,
229                      SmallVectorImpl<MachineOperand> &Cond,
230                      bool AllowModify) const override;
231   unsigned removeBranch(MachineBasicBlock &MBB,
232                         int *BytesRemoved = nullptr) const override;
233   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
234                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
235                         const DebugLoc &DL,
236                         int *BytesAdded = nullptr) const override;
237   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
238                       Register &SrcReg2, int64_t &Mask,
239                       int64_t &Value) const override;
240   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
241                        Register, Register, Register, int &, int &,
242                        int &) const override;
243   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
244                     const DebugLoc &DL, Register DstReg,
245                     ArrayRef<MachineOperand> Cond, Register TrueReg,
246                     Register FalseReg) const override;
247   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
248                      MachineRegisterInfo *MRI) const override;
249   bool isPredicable(const MachineInstr &MI) const override;
250   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
251                            unsigned ExtraPredCycles,
252                            BranchProbability Probability) const override;
253   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
254                            unsigned NumCyclesT, unsigned ExtraPredCyclesT,
255                            MachineBasicBlock &FMBB,
256                            unsigned NumCyclesF, unsigned ExtraPredCyclesF,
257                            BranchProbability Probability) const override;
258   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
259                             BranchProbability Probability) const override;
260   bool PredicateInstruction(MachineInstr &MI,
261                             ArrayRef<MachineOperand> Pred) const override;
262   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
263                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
264                    bool KillSrc) const override;
265   void storeRegToStackSlot(MachineBasicBlock &MBB,
266                            MachineBasicBlock::iterator MBBI,
267                            Register SrcReg, bool isKill, int FrameIndex,
268                            const TargetRegisterClass *RC,
269                            const TargetRegisterInfo *TRI) const override;
270   void loadRegFromStackSlot(MachineBasicBlock &MBB,
271                             MachineBasicBlock::iterator MBBI,
272                             Register DestReg, int FrameIdx,
273                             const TargetRegisterClass *RC,
274                             const TargetRegisterInfo *TRI) const override;
275   MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
276                                       LiveIntervals *LIS) const override;
277   MachineInstr *
278   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
279                         ArrayRef<unsigned> Ops,
280                         MachineBasicBlock::iterator InsertPt, int FrameIndex,
281                         LiveIntervals *LIS = nullptr,
282                         VirtRegMap *VRM = nullptr) const override;
283   MachineInstr *foldMemoryOperandImpl(
284       MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
285       MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
286       LiveIntervals *LIS = nullptr) const override;
287   bool expandPostRAPseudo(MachineInstr &MBBI) const override;
288   bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
289     override;
290 
291   // Return the SystemZRegisterInfo, which this class owns.
292   const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
293 
294   // Return the size in bytes of MI.
295   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
296 
297   // Return true if MI is a conditional or unconditional branch.
298   // When returning true, set Cond to the mask of condition-code
299   // values on which the instruction will branch, and set Target
300   // to the operand that contains the branch target.  This target
301   // can be a register or a basic block.
302   SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
303 
304   // Get the load and store opcodes for a given register class.
305   void getLoadStoreOpcodes(const TargetRegisterClass *RC,
306                            unsigned &LoadOpcode, unsigned &StoreOpcode) const;
307 
308   // Opcode is the opcode of an instruction that has an address operand,
309   // and the caller wants to perform that instruction's operation on an
310   // address that has displacement Offset.  Return the opcode of a suitable
311   // instruction (which might be Opcode itself) or 0 if no such instruction
312   // exists.
313   unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
314 
315   // Return true if Opcode has a mapping in 12 <-> 20 bit displacements.
316   bool hasDisplacementPairInsn(unsigned Opcode) const;
317 
318   // If Opcode is a load instruction that has a LOAD AND TEST form,
319   // return the opcode for the testing form, otherwise return 0.
320   unsigned getLoadAndTest(unsigned Opcode) const;
321 
322   // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
323   // Mask of the R2 operand, given that only the low BitSize bits of Mask are
324   // significant.  Set Start and End to the I3 and I4 operands if so.
325   bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
326                    unsigned &Start, unsigned &End) const;
327 
328   // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
329   // operation exists, return the opcode for the latter, otherwise return 0.
330   // MI, if nonnull, is the compare instruction.
331   unsigned getFusedCompare(unsigned Opcode,
332                            SystemZII::FusedCompareType Type,
333                            const MachineInstr *MI = nullptr) const;
334 
335   // Try to find all CC users of the compare instruction (MBBI) and update
336   // all of them to maintain equivalent behavior after swapping the compare
337   // operands. Return false if not all users can be conclusively found and
338   // handled. The compare instruction is *not* changed.
339   bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const;
340 
341   // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
342   // operation exists, returh the opcode for the latter, otherwise return 0.
343   unsigned getLoadAndTrap(unsigned Opcode) const;
344 
345   // Emit code before MBBI in MI to move immediate value Value into
346   // physical register Reg.
347   void loadImmediate(MachineBasicBlock &MBB,
348                      MachineBasicBlock::iterator MBBI,
349                      unsigned Reg, uint64_t Value) const;
350 
351   // Perform target specific instruction verification.
352   bool verifyInstruction(const MachineInstr &MI,
353                          StringRef &ErrInfo) const override;
354 
355   // Sometimes, it is possible for the target to tell, even without
356   // aliasing information, that two MIs access different memory
357   // addresses. This function returns true if two MIs access different
358   // memory addresses and false otherwise.
359   bool
360   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
361                                   const MachineInstr &MIb) const override;
362 };
363 
364 } // end namespace llvm
365 
366 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
367