10b57cec5SDimitry Andric//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 9fe6060f1SDimitry Andricdef IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10fe6060f1SDimitry Andricdef IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11fe6060f1SDimitry Andric 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric// Stack allocation 140b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric// The callseq_start node requires the hasSideEffects flag, even though these 170b57cec5SDimitry Andric// instructions are noops on SystemZ. 180b57cec5SDimitry Andriclet hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 190b57cec5SDimitry Andric def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 200b57cec5SDimitry Andric [(callseq_start timm:$amt1, timm:$amt2)]>; 210b57cec5SDimitry Andric def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 220b57cec5SDimitry Andric [(callseq_end timm:$amt1, timm:$amt2)]>; 230b57cec5SDimitry Andric} 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric// Takes as input the value of the stack pointer after a dynamic allocation 260b57cec5SDimitry Andric// has been made. Sets the output to the address of the dynamically- 270b57cec5SDimitry Andric// allocated area itself, skipping the outgoing arguments. 280b57cec5SDimitry Andric// 290b57cec5SDimitry Andric// This expands to an LA or LAY instruction. We restrict the offset 300b57cec5SDimitry Andric// to the range of LA and keep the LAY range in reserve for when 310b57cec5SDimitry Andric// the size of the outgoing arguments is added. 320b57cec5SDimitry Andricdef ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 330b57cec5SDimitry Andric [(set GR64:$dst, dynalloc12only:$src)]>; 340b57cec5SDimitry Andric 355ffd83dbSDimitry Andriclet Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 365ffd83dbSDimitry Andric usesCustomInserter = 1 in 375ffd83dbSDimitry Andric def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 385ffd83dbSDimitry Andric (ins GR64:$oldSP, GR64:$space), 395ffd83dbSDimitry Andric [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 405ffd83dbSDimitry Andric 415ffd83dbSDimitry Andriclet Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 425ffd83dbSDimitry Andric hasSideEffects = 1 in 435ffd83dbSDimitry Andric def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 440b57cec5SDimitry Andric 4581ad6265SDimitry Andriclet Defs = [R3D, CC], Uses = [R3D, R4D], hasNoSchedulingInfo = 1, 4681ad6265SDimitry Andric hasSideEffects = 1 in 4781ad6265SDimitry Andric def XPLINK_STACKALLOC : Pseudo<(outs), (ins), []>; 4881ad6265SDimitry Andric 490b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 500b57cec5SDimitry Andric// Branch instructions 510b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric// Conditional branches. 540b57cec5SDimitry Andriclet isBranch = 1, isTerminator = 1, Uses = [CC] in { 550b57cec5SDimitry Andric // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 560b57cec5SDimitry Andric // with the condition-code mask being the first operand. It seems friendlier 570b57cec5SDimitry Andric // to use mnemonic forms like JE and JLH when writing out the assembly though. 580b57cec5SDimitry Andric let isCodeGenOnly = 1 in { 590b57cec5SDimitry Andric // An assembler extended mnemonic for BRC. 600b57cec5SDimitry Andric def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 610b57cec5SDimitry Andric // An assembler extended mnemonic for BRCL. (The extension is "G" 620b57cec5SDimitry Andric // rather than "L" because "JL" is "Jump if Less".) 630b57cec5SDimitry Andric def BRCL : CondBranchRIL<"jg#", 0xC04>; 640b57cec5SDimitry Andric let isIndirectBranch = 1 in { 650b57cec5SDimitry Andric def BC : CondBranchRX<"b#", 0x47>; 660b57cec5SDimitry Andric def BCR : CondBranchRR<"b#r", 0x07>; 670b57cec5SDimitry Andric def BIC : CondBranchRXY<"bi#", 0xe347>, 680b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 690b57cec5SDimitry Andric } 700b57cec5SDimitry Andric } 710b57cec5SDimitry Andric 720b57cec5SDimitry Andric // Allow using the raw forms directly from the assembler (and occasional 730b57cec5SDimitry Andric // special code generation needs) as well. 740b57cec5SDimitry Andric def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 750b57cec5SDimitry Andric def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 760b57cec5SDimitry Andric let isIndirectBranch = 1 in { 770b57cec5SDimitry Andric def BCAsm : AsmCondBranchRX<"bc", 0x47>; 780b57cec5SDimitry Andric def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 790b57cec5SDimitry Andric def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 800b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 810b57cec5SDimitry Andric } 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric // Define AsmParser extended mnemonics for each general condition-code mask 840b57cec5SDimitry Andric // (integer or floating-point) 850b57cec5SDimitry Andric foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 860b57cec5SDimitry Andric "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 870b57cec5SDimitry Andric def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 88fe6060f1SDimitry Andric def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 890b57cec5SDimitry Andric let isIndirectBranch = 1 in { 900b57cec5SDimitry Andric def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 910b57cec5SDimitry Andric def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 920b57cec5SDimitry Andric def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 930b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 940b57cec5SDimitry Andric } 950b57cec5SDimitry Andric } 960b57cec5SDimitry Andric} 970b57cec5SDimitry Andric 980b57cec5SDimitry Andric// Unconditional branches. These are in fact simply variants of the 990b57cec5SDimitry Andric// conditional branches with the condition mask set to "always". 1000b57cec5SDimitry Andriclet isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1010b57cec5SDimitry Andric def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 102fe6060f1SDimitry Andric def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 1030b57cec5SDimitry Andric let isIndirectBranch = 1 in { 1040b57cec5SDimitry Andric def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 1050b57cec5SDimitry Andric def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 1060b57cec5SDimitry Andric def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 1070b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 1080b57cec5SDimitry Andric } 1090b57cec5SDimitry Andric} 1100b57cec5SDimitry Andric 111e8d8bef9SDimitry Andric// NOPs. These are again variants of the conditional branches, with the 112e8d8bef9SDimitry Andric// condition mask set to "never". NOP_bare can't be an InstAlias since it 113e8d8bef9SDimitry Andric// would need R0D hard coded which is not part of ADDR64BitRegClass. 1140b57cec5SDimitry Andricdef NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 11506c3fb27SDimitry Andriclet isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in 116e8d8bef9SDimitry Andric def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 1170b57cec5SDimitry Andricdef NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 118e8d8bef9SDimitry Andricdef NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 119e8d8bef9SDimitry Andric 120e8d8bef9SDimitry Andric// An alias of BRC 0, label 121e8d8bef9SDimitry Andricdef JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 122e8d8bef9SDimitry Andric 123e8d8bef9SDimitry Andric// An alias of BRCL 0, label 124fe6060f1SDimitry Andric// jgnop on att ; jlnop on hlasm 125fe6060f1SDimitry Andricdef JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andric// Fused compare-and-branch instructions. 1280b57cec5SDimitry Andric// 1290b57cec5SDimitry Andric// These instructions do not use or clobber the condition codes. 1300b57cec5SDimitry Andric// We nevertheless pretend that the relative compare-and-branch 1310b57cec5SDimitry Andric// instructions clobber CC, so that we can lower them to separate 1320b57cec5SDimitry Andric// comparisons and BRCLs if the branch ends up being out of range. 1330b57cec5SDimitry Andriclet isBranch = 1, isTerminator = 1 in { 1340b57cec5SDimitry Andric // As for normal branches, we handle these instructions internally in 1350b57cec5SDimitry Andric // their raw CRJ-like form, but use assembly macros like CRJE when writing 1360b57cec5SDimitry Andric // them out. Using the *Pair multiclasses, we also create the raw forms. 1370b57cec5SDimitry Andric let Defs = [CC] in { 1380b57cec5SDimitry Andric defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 1390b57cec5SDimitry Andric defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 1400b57cec5SDimitry Andric defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 1410b57cec5SDimitry Andric defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 1420b57cec5SDimitry Andric defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 1430b57cec5SDimitry Andric defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 1440b57cec5SDimitry Andric defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 1450b57cec5SDimitry Andric defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 1460b57cec5SDimitry Andric } 1470b57cec5SDimitry Andric let isIndirectBranch = 1 in { 1480b57cec5SDimitry Andric defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 1490b57cec5SDimitry Andric defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 1500b57cec5SDimitry Andric defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 1510b57cec5SDimitry Andric defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 1520b57cec5SDimitry Andric defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 1530b57cec5SDimitry Andric defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 1540b57cec5SDimitry Andric defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 1550b57cec5SDimitry Andric defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 1560b57cec5SDimitry Andric } 1570b57cec5SDimitry Andric 1580b57cec5SDimitry Andric // Define AsmParser mnemonics for each integer condition-code mask. 1590b57cec5SDimitry Andric foreach V = [ "E", "H", "L", "HE", "LE", "LH", 1600b57cec5SDimitry Andric "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 1610b57cec5SDimitry Andric let Defs = [CC] in { 1620b57cec5SDimitry Andric def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 1630b57cec5SDimitry Andric def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 1640b57cec5SDimitry Andric def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 1650b57cec5SDimitry Andric imm32sx8>; 1660b57cec5SDimitry Andric def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 1670b57cec5SDimitry Andric imm64sx8>; 1680b57cec5SDimitry Andric def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 1690b57cec5SDimitry Andric def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 1700b57cec5SDimitry Andric def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 1710b57cec5SDimitry Andric imm32zx8>; 1720b57cec5SDimitry Andric def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 1730b57cec5SDimitry Andric imm64zx8>; 1740b57cec5SDimitry Andric } 1750b57cec5SDimitry Andric let isIndirectBranch = 1 in { 1760b57cec5SDimitry Andric def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 1770b57cec5SDimitry Andric def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 1780b57cec5SDimitry Andric def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 1790b57cec5SDimitry Andric imm32sx8>; 1800b57cec5SDimitry Andric def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 1810b57cec5SDimitry Andric imm64sx8>; 1820b57cec5SDimitry Andric def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 1830b57cec5SDimitry Andric def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 1840b57cec5SDimitry Andric def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 1850b57cec5SDimitry Andric imm32zx8>; 1860b57cec5SDimitry Andric def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 1870b57cec5SDimitry Andric imm64zx8>; 1880b57cec5SDimitry Andric } 1890b57cec5SDimitry Andric } 1900b57cec5SDimitry Andric} 1910b57cec5SDimitry Andric 1920b57cec5SDimitry Andric// Decrement a register and branch if it is nonzero. These don't clobber CC, 1930b57cec5SDimitry Andric// but we might need to split long relative branches into sequences that do. 1940b57cec5SDimitry Andriclet isBranch = 1, isTerminator = 1 in { 1950b57cec5SDimitry Andric let Defs = [CC] in { 1960b57cec5SDimitry Andric def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 1970b57cec5SDimitry Andric def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 1980b57cec5SDimitry Andric } 1990b57cec5SDimitry Andric // This doesn't need to clobber CC since we never need to split it. 2000b57cec5SDimitry Andric def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 2010b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 2020b57cec5SDimitry Andric 2030b57cec5SDimitry Andric def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 2040b57cec5SDimitry Andric def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 2050b57cec5SDimitry Andric def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 2060b57cec5SDimitry Andric def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 2070b57cec5SDimitry Andric} 2080b57cec5SDimitry Andric 2090b57cec5SDimitry Andriclet isBranch = 1, isTerminator = 1 in { 2100b57cec5SDimitry Andric let Defs = [CC] in { 2110b57cec5SDimitry Andric def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 2120b57cec5SDimitry Andric def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 2130b57cec5SDimitry Andric def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 2140b57cec5SDimitry Andric def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 2150b57cec5SDimitry Andric } 2160b57cec5SDimitry Andric def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 2170b57cec5SDimitry Andric def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 2180b57cec5SDimitry Andric def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 2190b57cec5SDimitry Andric def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 2200b57cec5SDimitry Andric} 2210b57cec5SDimitry Andric 2220b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2230b57cec5SDimitry Andric// Trap instructions 2240b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2250b57cec5SDimitry Andric 2260b57cec5SDimitry Andric// Unconditional trap. 2270b57cec5SDimitry Andriclet hasCtrlDep = 1, hasSideEffects = 1 in 2280b57cec5SDimitry Andric def Trap : Alias<4, (outs), (ins), [(trap)]>; 2290b57cec5SDimitry Andric 2300b57cec5SDimitry Andric// Conditional trap. 2310b57cec5SDimitry Andriclet hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 2320b57cec5SDimitry Andric def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 2330b57cec5SDimitry Andric 2340b57cec5SDimitry Andric// Fused compare-and-trap instructions. 2350b57cec5SDimitry Andriclet hasCtrlDep = 1, hasSideEffects = 1 in { 2360b57cec5SDimitry Andric // These patterns work the same way as for compare-and-branch. 2370b57cec5SDimitry Andric defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 2380b57cec5SDimitry Andric defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 2390b57cec5SDimitry Andric defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 2400b57cec5SDimitry Andric defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 2410b57cec5SDimitry Andric defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 2420b57cec5SDimitry Andric defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 2430b57cec5SDimitry Andric defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 2440b57cec5SDimitry Andric defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 2450b57cec5SDimitry Andric let Predicates = [FeatureMiscellaneousExtensions] in { 2460b57cec5SDimitry Andric defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 2470b57cec5SDimitry Andric defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 2480b57cec5SDimitry Andric } 2490b57cec5SDimitry Andric 2500b57cec5SDimitry Andric foreach V = [ "E", "H", "L", "HE", "LE", "LH", 2510b57cec5SDimitry Andric "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 2520b57cec5SDimitry Andric def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 2530b57cec5SDimitry Andric def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 2540b57cec5SDimitry Andric def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 2550b57cec5SDimitry Andric def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 2560b57cec5SDimitry Andric def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 2570b57cec5SDimitry Andric imm32sx16>; 2580b57cec5SDimitry Andric def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 2590b57cec5SDimitry Andric imm64sx16>; 2600b57cec5SDimitry Andric def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 2610b57cec5SDimitry Andric imm32zx16>; 2620b57cec5SDimitry Andric def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 2630b57cec5SDimitry Andric imm64zx16>; 2640b57cec5SDimitry Andric let Predicates = [FeatureMiscellaneousExtensions] in { 2650b57cec5SDimitry Andric def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 2660b57cec5SDimitry Andric def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 2670b57cec5SDimitry Andric } 2680b57cec5SDimitry Andric } 2690b57cec5SDimitry Andric} 2700b57cec5SDimitry Andric 2710b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2720b57cec5SDimitry Andric// Call and return instructions 2730b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2740b57cec5SDimitry Andric 2750b57cec5SDimitry Andric// Define the general form of the call instructions for the asm parser. 2760b57cec5SDimitry Andric// These instructions don't hard-code %r14 as the return address register. 2770b57cec5SDimitry Andriclet isCall = 1, Defs = [CC] in { 2780b57cec5SDimitry Andric def BRAS : CallRI <"bras", 0xA75>; 2790b57cec5SDimitry Andric def BRASL : CallRIL<"brasl", 0xC05>; 2800b57cec5SDimitry Andric def BAS : CallRX <"bas", 0x4D>; 2810b57cec5SDimitry Andric def BASR : CallRR <"basr", 0x0D>; 2820b57cec5SDimitry Andric} 2830b57cec5SDimitry Andric 28406c3fb27SDimitry Andric// A symbol in the ADA (z/OS only). 28506c3fb27SDimitry Andricdef adasym : Operand<i64>; 28606c3fb27SDimitry Andric 287fe6060f1SDimitry Andric// z/OS XPLINK 288fe6060f1SDimitry Andriclet Predicates = [IsTargetXPLINK64] in { 289fe6060f1SDimitry Andric let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 290fe6060f1SDimitry Andric def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 291fe6060f1SDimitry Andric [(z_call pcrel32:$I2)]>; 292fe6060f1SDimitry Andric def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 293fe6060f1SDimitry Andric [(z_call ADDR64:$R2)]>; 294fe6060f1SDimitry Andric } 29581ad6265SDimitry Andric 29681ad6265SDimitry Andric let isCall = 1, Defs = [R3D, CC], Uses = [FPC] in { 29781ad6265SDimitry Andric def CallBASR_STACKEXT : Alias<4, (outs), (ins ADDR64:$R2), []>; 29881ad6265SDimitry Andric } 29906c3fb27SDimitry Andric 30006c3fb27SDimitry Andric let hasNoSchedulingInfo = 1, Defs = [CC] in { 30106c3fb27SDimitry Andric def ADA_ENTRY : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, 30206c3fb27SDimitry Andric ADDR64:$ADA, imm64:$Offset), 30306c3fb27SDimitry Andric [(set i64:$Reg, (z_ada_entry i64:$addr, 30406c3fb27SDimitry Andric i64:$ADA, i64:$Offset))]>; 30506c3fb27SDimitry Andric } 30606c3fb27SDimitry Andric let mayLoad = 1, AddedComplexity = 20, hasNoSchedulingInfo = 1, Defs = [CC] in { 30706c3fb27SDimitry Andric def ADA_ENTRY_VALUE : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, 30806c3fb27SDimitry Andric ADDR64:$ADA, imm64:$Offset), 30906c3fb27SDimitry Andric [(set i64:$Reg, (load (z_ada_entry 31006c3fb27SDimitry Andric iPTR:$addr, iPTR:$ADA, i64:$Offset)))]>; 31106c3fb27SDimitry Andric } 312fe6060f1SDimitry Andric} 313fe6060f1SDimitry Andric 3140b57cec5SDimitry Andric// Regular calls. 315fe6060f1SDimitry Andric// z/Linux ELF 316fe6060f1SDimitry Andriclet Predicates = [IsTargetELF] in { 3170b57cec5SDimitry Andric let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 3180b57cec5SDimitry Andric def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 3190b57cec5SDimitry Andric [(z_call pcrel32:$I2)]>; 3200b57cec5SDimitry Andric def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 3210b57cec5SDimitry Andric [(z_call ADDR64:$R2)]>; 3220b57cec5SDimitry Andric } 3230b57cec5SDimitry Andric 3240b57cec5SDimitry Andric // TLS calls. These will be lowered into a call to __tls_get_offset, 3250b57cec5SDimitry Andric // with an extra relocation specifying the TLS symbol. 3260b57cec5SDimitry Andric let isCall = 1, Defs = [R14D, CC] in { 3270b57cec5SDimitry Andric def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 3280b57cec5SDimitry Andric [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 3290b57cec5SDimitry Andric def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 3300b57cec5SDimitry Andric [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 3310b57cec5SDimitry Andric } 332fe6060f1SDimitry Andric} 3330b57cec5SDimitry Andric 334fe6060f1SDimitry Andric// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 335fe6060f1SDimitry Andric// R1 used for ELF 3360b57cec5SDimitry Andriclet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 3370b57cec5SDimitry Andric def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 3380b57cec5SDimitry Andric [(z_sibcall pcrel32:$I2)]>; 339e8d8bef9SDimitry Andric def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 340e8d8bef9SDimitry Andric [(z_sibcall ADDR64:$R2)]>; 3410b57cec5SDimitry Andric} 3420b57cec5SDimitry Andric 3430b57cec5SDimitry Andric// Conditional sibling calls. 3440b57cec5SDimitry Andriclet CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 3450b57cec5SDimitry Andric def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 3460b57cec5SDimitry Andric pcrel32:$I2), []>; 347e8d8bef9SDimitry Andric def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 348e8d8bef9SDimitry Andric ADDR64:$R2), []>; 3490b57cec5SDimitry Andric} 3500b57cec5SDimitry Andric 3510b57cec5SDimitry Andric// Fused compare and conditional sibling calls. 352e8d8bef9SDimitry Andriclet isCall = 1, isTerminator = 1, isReturn = 1 in { 353e8d8bef9SDimitry Andric def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 354e8d8bef9SDimitry Andric def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 355e8d8bef9SDimitry Andric def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 356e8d8bef9SDimitry Andric def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 357e8d8bef9SDimitry Andric def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 358e8d8bef9SDimitry Andric def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 359e8d8bef9SDimitry Andric def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 360e8d8bef9SDimitry Andric def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 3610b57cec5SDimitry Andric} 3620b57cec5SDimitry Andric 36381ad6265SDimitry Andriclet Predicates = [IsTargetXPLINK64] in { 36481ad6265SDimitry Andric // A return instruction (b 2(%r7)). 36581ad6265SDimitry Andric let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 36606c3fb27SDimitry Andric def Return_XPLINK : Alias<4, (outs), (ins), [(z_retglue)]>; 36781ad6265SDimitry Andric 36881ad6265SDimitry Andric // A conditional return instruction (bc <cond>, 2(%r7)). 36981ad6265SDimitry Andric let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 37081ad6265SDimitry Andric def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 37181ad6265SDimitry Andric} 37281ad6265SDimitry Andric 37381ad6265SDimitry Andriclet Predicates = [IsTargetELF] in { 37481ad6265SDimitry Andric // A return instruction (br %r14). 3750b57cec5SDimitry Andric let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 37606c3fb27SDimitry Andric def Return : Alias<2, (outs), (ins), [(z_retglue)]>; 3770b57cec5SDimitry Andric 3780b57cec5SDimitry Andric // A conditional return instruction (bcr <cond>, %r14). 3790b57cec5SDimitry Andric let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 3800b57cec5SDimitry Andric def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 38181ad6265SDimitry Andric} 3820b57cec5SDimitry Andric 3830b57cec5SDimitry Andric// Fused compare and conditional returns. 3840b57cec5SDimitry Andriclet isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 3850b57cec5SDimitry Andric def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 3860b57cec5SDimitry Andric def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 3870b57cec5SDimitry Andric def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 3880b57cec5SDimitry Andric def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 3890b57cec5SDimitry Andric def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 3900b57cec5SDimitry Andric def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 3910b57cec5SDimitry Andric def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 3920b57cec5SDimitry Andric def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 3930b57cec5SDimitry Andric} 3940b57cec5SDimitry Andric 3950b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 3960b57cec5SDimitry Andric// Select instructions 3970b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 3980b57cec5SDimitry Andric 3990b57cec5SDimitry Andricdef Select32 : SelectWrapper<i32, GR32>, 4000b57cec5SDimitry Andric Requires<[FeatureNoLoadStoreOnCond]>; 4010b57cec5SDimitry Andricdef Select64 : SelectWrapper<i64, GR64>, 4020b57cec5SDimitry Andric Requires<[FeatureNoLoadStoreOnCond]>; 4030b57cec5SDimitry Andric 4040b57cec5SDimitry Andric// We don't define 32-bit Mux stores if we don't have STOCFH, because the 4050b57cec5SDimitry Andric// low-only STOC should then always be used if possible. 4060b57cec5SDimitry Andricdefm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 4070b57cec5SDimitry Andric nonvolatile_anyextloadi8, bdxaddr20only>, 4080b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 4090b57cec5SDimitry Andricdefm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 4100b57cec5SDimitry Andric nonvolatile_anyextloadi16, bdxaddr20only>, 4110b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 4128bcb0991SDimitry Andricdefm CondStore32Mux : CondStores<GRX32, simple_store, 4138bcb0991SDimitry Andric simple_load, bdxaddr20only>, 4140b57cec5SDimitry Andric Requires<[FeatureLoadStoreOnCond2]>; 4150b57cec5SDimitry Andricdefm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 4160b57cec5SDimitry Andric nonvolatile_anyextloadi8, bdxaddr20only>; 4170b57cec5SDimitry Andricdefm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 4180b57cec5SDimitry Andric nonvolatile_anyextloadi16, bdxaddr20only>; 4198bcb0991SDimitry Andricdefm CondStore32 : CondStores<GR32, simple_store, 4208bcb0991SDimitry Andric simple_load, bdxaddr20only>; 4210b57cec5SDimitry Andric 4220b57cec5SDimitry Andricdefm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 4230b57cec5SDimitry Andric nonvolatile_anyextloadi8, bdxaddr20only>; 4240b57cec5SDimitry Andricdefm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 4250b57cec5SDimitry Andric nonvolatile_anyextloadi16, bdxaddr20only>; 4260b57cec5SDimitry Andricdefm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 4270b57cec5SDimitry Andric nonvolatile_anyextloadi32, bdxaddr20only>; 4288bcb0991SDimitry Andricdefm CondStore64 : CondStores<GR64, simple_store, 4298bcb0991SDimitry Andric simple_load, bdxaddr20only>; 4300b57cec5SDimitry Andric 4310b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4320b57cec5SDimitry Andric// Move instructions 4330b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4340b57cec5SDimitry Andric 4350b57cec5SDimitry Andric// Register moves. 4360b57cec5SDimitry Andricdef LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 4370b57cec5SDimitry Andricdef LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 4380b57cec5SDimitry Andric 4390b57cec5SDimitry Andriclet Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 4400b57cec5SDimitry Andric def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 4410b57cec5SDimitry Andric def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 4420b57cec5SDimitry Andric} 4430b57cec5SDimitry Andric 4440b57cec5SDimitry Andriclet usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 4450b57cec5SDimitry Andric def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 4460b57cec5SDimitry Andric 4470b57cec5SDimitry Andric// Immediate moves. 4480b57cec5SDimitry Andriclet isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 4490b57cec5SDimitry Andric // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 4500b57cec5SDimitry Andric // deopending on the choice of register. 4510b57cec5SDimitry Andric def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 4520b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 4530b57cec5SDimitry Andric def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 4540b57cec5SDimitry Andric def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 4550b57cec5SDimitry Andric 4560b57cec5SDimitry Andric // Other 16-bit immediates. 4570b57cec5SDimitry Andric def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 4580b57cec5SDimitry Andric def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 4590b57cec5SDimitry Andric def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 4600b57cec5SDimitry Andric def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 4610b57cec5SDimitry Andric 4620b57cec5SDimitry Andric // 32-bit immediates. 4630b57cec5SDimitry Andric def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 4640b57cec5SDimitry Andric def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 4650b57cec5SDimitry Andric def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 4660b57cec5SDimitry Andric} 4670b57cec5SDimitry Andric 4680b57cec5SDimitry Andric// Register loads. 4690b57cec5SDimitry Andriclet canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 4700b57cec5SDimitry Andric // Expands to L, LY or LFH, depending on the choice of register. 4710b57cec5SDimitry Andric def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 4720b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 4730b57cec5SDimitry Andric defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 4740b57cec5SDimitry Andric def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 4750b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 4760b57cec5SDimitry Andric def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 4770b57cec5SDimitry Andric 4780b57cec5SDimitry Andric // These instructions are split after register allocation, so we don't 4790b57cec5SDimitry Andric // want a custom inserter. 4800b57cec5SDimitry Andric let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 4810b57cec5SDimitry Andric def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 4820b57cec5SDimitry Andric [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 4830b57cec5SDimitry Andric } 4840b57cec5SDimitry Andric} 4850b57cec5SDimitry Andriclet Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 4860b57cec5SDimitry Andric def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 4870b57cec5SDimitry Andric def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 4880b57cec5SDimitry Andric} 4890b57cec5SDimitry Andric 4900b57cec5SDimitry Andriclet canFoldAsLoad = 1 in { 4910b57cec5SDimitry Andric def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 4920b57cec5SDimitry Andric def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 4930b57cec5SDimitry Andric} 4940b57cec5SDimitry Andric 4950b57cec5SDimitry Andric// Load and zero rightmost byte. 4960b57cec5SDimitry Andriclet Predicates = [FeatureLoadAndZeroRightmostByte] in { 4970b57cec5SDimitry Andric def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 4980b57cec5SDimitry Andric def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 4990b57cec5SDimitry Andric def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 5000b57cec5SDimitry Andric (LZRF bdxaddr20only:$src)>; 5010b57cec5SDimitry Andric def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 5020b57cec5SDimitry Andric (LZRG bdxaddr20only:$src)>; 5030b57cec5SDimitry Andric} 5040b57cec5SDimitry Andric 5050b57cec5SDimitry Andric// Load and trap. 5060b57cec5SDimitry Andriclet Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 5070b57cec5SDimitry Andric def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 5080b57cec5SDimitry Andric def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 5090b57cec5SDimitry Andric def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 5100b57cec5SDimitry Andric} 5110b57cec5SDimitry Andric 5120b57cec5SDimitry Andric// Register stores. 5130b57cec5SDimitry Andriclet SimpleBDXStore = 1, mayStore = 1 in { 5140b57cec5SDimitry Andric // Expands to ST, STY or STFH, depending on the choice of register. 5150b57cec5SDimitry Andric def STMux : StoreRXYPseudo<store, GRX32, 4>, 5160b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 5170b57cec5SDimitry Andric defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 5180b57cec5SDimitry Andric def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 5190b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 5200b57cec5SDimitry Andric def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 5210b57cec5SDimitry Andric 5220b57cec5SDimitry Andric // These instructions are split after register allocation, so we don't 5230b57cec5SDimitry Andric // want a custom inserter. 5240b57cec5SDimitry Andric let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 5250b57cec5SDimitry Andric def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 5260b57cec5SDimitry Andric [(store GR128:$src, bdxaddr20only128:$dst)]>; 5270b57cec5SDimitry Andric } 5280b57cec5SDimitry Andric} 5290b57cec5SDimitry Andricdef STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 5300b57cec5SDimitry Andricdef STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 5310b57cec5SDimitry Andric 5320b57cec5SDimitry Andric// 8-bit immediate stores to 8-bit fields. 5330b57cec5SDimitry Andricdefm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 5340b57cec5SDimitry Andric 5350b57cec5SDimitry Andric// 16-bit immediate stores to 16-, 32- or 64-bit fields. 5360b57cec5SDimitry Andricdef MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 5370b57cec5SDimitry Andricdef MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 5380b57cec5SDimitry Andricdef MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 5390b57cec5SDimitry Andric 5400b57cec5SDimitry Andric// Memory-to-memory moves. 5410b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1 in 542349cc55cSDimitry Andric defm MVC : MemorySS<"mvc", 0xD2, z_mvc>; 5430b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Defs = [CC] in { 5440b57cec5SDimitry Andric def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 5450b57cec5SDimitry Andric def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 5460b57cec5SDimitry Andric def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 5470b57cec5SDimitry Andric} 5480b57cec5SDimitry Andric 5490eae32dcSDimitry Andric// Memset[Length][Byte] pseudos. 5500eae32dcSDimitry Andricdef MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>; 5510eae32dcSDimitry Andricdef MemsetImmReg : MemsetPseudo<imm64, GR32>; 5520eae32dcSDimitry Andricdef MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>; 5530eae32dcSDimitry Andricdef MemsetRegReg : MemsetPseudo<ADDR64, GR32>; 5540eae32dcSDimitry Andric 5550b57cec5SDimitry Andric// Move right. 5560b57cec5SDimitry Andriclet Predicates = [FeatureMiscellaneousExtensions3], 5570b57cec5SDimitry Andric mayLoad = 1, mayStore = 1, Uses = [R0L] in 5580b57cec5SDimitry Andric def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 5590b57cec5SDimitry Andric 5600b57cec5SDimitry Andric// String moves. 5610b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Defs = [CC] in 5620b57cec5SDimitry Andric defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 5630b57cec5SDimitry Andric 5640b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 5650b57cec5SDimitry Andric// Conditional move instructions 5660b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 5670b57cec5SDimitry Andric 5680b57cec5SDimitry Andriclet Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 5690b57cec5SDimitry Andric // Select. 5700b57cec5SDimitry Andric let isCommutable = 1 in { 5710b57cec5SDimitry Andric // Expands to SELR or SELFHR or a branch-and-move sequence, 5720b57cec5SDimitry Andric // depending on the choice of registers. 5735ffd83dbSDimitry Andric def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 5740b57cec5SDimitry Andric defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 5750b57cec5SDimitry Andric defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 5760b57cec5SDimitry Andric defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 5770b57cec5SDimitry Andric } 5780b57cec5SDimitry Andric 5790b57cec5SDimitry Andric // Define AsmParser extended mnemonics for each general condition-code mask. 5800b57cec5SDimitry Andric foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 5810b57cec5SDimitry Andric "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 5820b57cec5SDimitry Andric def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 5830b57cec5SDimitry Andric GR32, GR32, GR32>; 5840b57cec5SDimitry Andric def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 5850b57cec5SDimitry Andric GRH32, GRH32, GRH32>; 5860b57cec5SDimitry Andric def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 5870b57cec5SDimitry Andric GR64, GR64, GR64>; 5880b57cec5SDimitry Andric } 5890b57cec5SDimitry Andric} 5900b57cec5SDimitry Andric 5910b57cec5SDimitry Andriclet Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 5920b57cec5SDimitry Andric // Load immediate on condition. Matched via DAG pattern and created 5930b57cec5SDimitry Andric // by the PeepholeOptimizer via FoldImmediate. 5940b57cec5SDimitry Andric 5950b57cec5SDimitry Andric // Expands to LOCHI or LOCHHI, depending on the choice of register. 5960b57cec5SDimitry Andric def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 5970b57cec5SDimitry Andric defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 5980b57cec5SDimitry Andric defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 5990b57cec5SDimitry Andric defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 6000b57cec5SDimitry Andric 6010b57cec5SDimitry Andric // Move register on condition. Matched via DAG pattern and 6020b57cec5SDimitry Andric // created by early if-conversion. 6030b57cec5SDimitry Andric let isCommutable = 1 in { 6040b57cec5SDimitry Andric // Expands to LOCR or LOCFHR or a branch-and-move sequence, 6050b57cec5SDimitry Andric // depending on the choice of registers. 6065ffd83dbSDimitry Andric def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 6070b57cec5SDimitry Andric defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 6080b57cec5SDimitry Andric } 6090b57cec5SDimitry Andric 6100b57cec5SDimitry Andric // Load on condition. Matched via DAG pattern. 6110b57cec5SDimitry Andric // Expands to LOC or LOCFH, depending on the choice of register. 6125ffd83dbSDimitry Andric defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 6138bcb0991SDimitry Andric defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 6140b57cec5SDimitry Andric 6150b57cec5SDimitry Andric // Store on condition. Expanded from CondStore* pseudos. 6160b57cec5SDimitry Andric // Expands to STOC or STOCFH, depending on the choice of register. 6170b57cec5SDimitry Andric def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 6180b57cec5SDimitry Andric defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 6190b57cec5SDimitry Andric 6200b57cec5SDimitry Andric // Define AsmParser extended mnemonics for each general condition-code mask. 6210b57cec5SDimitry Andric foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 6220b57cec5SDimitry Andric "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 6230b57cec5SDimitry Andric def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 6240b57cec5SDimitry Andric imm32sx16>; 6250b57cec5SDimitry Andric def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 6260b57cec5SDimitry Andric imm64sx16>; 6270b57cec5SDimitry Andric def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 6280b57cec5SDimitry Andric imm32sx16>; 6290b57cec5SDimitry Andric def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 6300b57cec5SDimitry Andric def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 6310b57cec5SDimitry Andric def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 6320b57cec5SDimitry Andric } 6330b57cec5SDimitry Andric} 6340b57cec5SDimitry Andric 6350b57cec5SDimitry Andriclet Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 6360b57cec5SDimitry Andric // Move register on condition. Matched via DAG pattern and 6370b57cec5SDimitry Andric // created by early if-conversion. 6380b57cec5SDimitry Andric let isCommutable = 1 in { 6390b57cec5SDimitry Andric defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 6400b57cec5SDimitry Andric defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 6410b57cec5SDimitry Andric } 6420b57cec5SDimitry Andric 6430b57cec5SDimitry Andric // Load on condition. Matched via DAG pattern. 6448bcb0991SDimitry Andric defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 6455ffd83dbSDimitry Andric defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 6460b57cec5SDimitry Andric 6470b57cec5SDimitry Andric // Store on condition. Expanded from CondStore* pseudos. 6480b57cec5SDimitry Andric defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 6490b57cec5SDimitry Andric defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 6500b57cec5SDimitry Andric 6510b57cec5SDimitry Andric // Define AsmParser extended mnemonics for each general condition-code mask. 6520b57cec5SDimitry Andric foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 6530b57cec5SDimitry Andric "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 6540b57cec5SDimitry Andric def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 6550b57cec5SDimitry Andric def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 6560b57cec5SDimitry Andric def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 6570b57cec5SDimitry Andric def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 6580b57cec5SDimitry Andric def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 6590b57cec5SDimitry Andric def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 6600b57cec5SDimitry Andric } 6610b57cec5SDimitry Andric} 6620b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 6630b57cec5SDimitry Andric// Sign extensions 6640b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 6650b57cec5SDimitry Andric// 6660b57cec5SDimitry Andric// Note that putting these before zero extensions mean that we will prefer 6670b57cec5SDimitry Andric// them for anyextload*. There's not really much to choose between the two 6680b57cec5SDimitry Andric// either way, but signed-extending loads have a short LH and a long LHY, 6690b57cec5SDimitry Andric// while zero-extending loads have only the long LLH. 6700b57cec5SDimitry Andric// 6710b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 6720b57cec5SDimitry Andric 6730b57cec5SDimitry Andric// 32-bit extensions from registers. 6740b57cec5SDimitry Andricdef LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 6750b57cec5SDimitry Andricdef LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 6760b57cec5SDimitry Andric 6770b57cec5SDimitry Andric// 64-bit extensions from registers. 6780b57cec5SDimitry Andricdef LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 6790b57cec5SDimitry Andricdef LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 6800b57cec5SDimitry Andricdef LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 6810b57cec5SDimitry Andric 6820b57cec5SDimitry Andriclet Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 6830b57cec5SDimitry Andric def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 6840b57cec5SDimitry Andric 6850b57cec5SDimitry Andric// Match 32-to-64-bit sign extensions in which the source is already 6860b57cec5SDimitry Andric// in a 64-bit register. 6870b57cec5SDimitry Andricdef : Pat<(sext_inreg GR64:$src, i32), 6880b57cec5SDimitry Andric (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 6890b57cec5SDimitry Andric 6900b57cec5SDimitry Andric// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 6910b57cec5SDimitry Andric// depending on the choice of register. 6920b57cec5SDimitry Andricdef LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 6930b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 6940b57cec5SDimitry Andricdef LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 6950b57cec5SDimitry Andricdef LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 6960b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 6970b57cec5SDimitry Andric 6980b57cec5SDimitry Andric// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 6990b57cec5SDimitry Andric// depending on the choice of register. 7000b57cec5SDimitry Andricdef LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 7010b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7020b57cec5SDimitry Andricdefm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 7030b57cec5SDimitry Andricdef LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 7040b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7050b57cec5SDimitry Andricdef LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 7060b57cec5SDimitry Andric 7070b57cec5SDimitry Andric// 64-bit extensions from memory. 7080b57cec5SDimitry Andricdef LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 7090b57cec5SDimitry Andricdef LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 7100b57cec5SDimitry Andricdef LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 7110b57cec5SDimitry Andricdef LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 7120b57cec5SDimitry Andricdef LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 7130b57cec5SDimitry Andriclet Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 7140b57cec5SDimitry Andric def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 7150b57cec5SDimitry Andric 7160b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 7170b57cec5SDimitry Andric// Zero extensions 7180b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 7190b57cec5SDimitry Andric 7200b57cec5SDimitry Andric// 32-bit extensions from registers. 7210b57cec5SDimitry Andric 7220b57cec5SDimitry Andric// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 7230b57cec5SDimitry Andricdef LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 7240b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7250b57cec5SDimitry Andricdef LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 7260b57cec5SDimitry Andric// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 7270b57cec5SDimitry Andricdef LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 7280b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7290b57cec5SDimitry Andricdef LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 7300b57cec5SDimitry Andric 7310b57cec5SDimitry Andric// 64-bit extensions from registers. 7320b57cec5SDimitry Andricdef LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 7330b57cec5SDimitry Andricdef LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 7340b57cec5SDimitry Andricdef LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 7350b57cec5SDimitry Andric 7360b57cec5SDimitry Andric// Match 32-to-64-bit zero extensions in which the source is already 7370b57cec5SDimitry Andric// in a 64-bit register. 7380b57cec5SDimitry Andricdef : Pat<(and GR64:$src, 0xffffffff), 7390b57cec5SDimitry Andric (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 7400b57cec5SDimitry Andric 7410b57cec5SDimitry Andric// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 7420b57cec5SDimitry Andric// depending on the choice of register. 7430b57cec5SDimitry Andricdef LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 7440b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7450b57cec5SDimitry Andricdef LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 7460b57cec5SDimitry Andricdef LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 7470b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andric// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 7500b57cec5SDimitry Andric// depending on the choice of register. 7510b57cec5SDimitry Andricdef LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 7520b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7530b57cec5SDimitry Andricdef LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 7540b57cec5SDimitry Andricdef LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 7550b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 7560b57cec5SDimitry Andricdef LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 7570b57cec5SDimitry Andric 7580b57cec5SDimitry Andric// 64-bit extensions from memory. 7590b57cec5SDimitry Andricdef LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 7600b57cec5SDimitry Andricdef LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 7610b57cec5SDimitry Andricdef LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 7620b57cec5SDimitry Andricdef LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 7630b57cec5SDimitry Andricdef LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 7640b57cec5SDimitry Andric 7650b57cec5SDimitry Andric// 31-to-64-bit zero extensions. 7660b57cec5SDimitry Andricdef LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 7670b57cec5SDimitry Andricdef LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 7680b57cec5SDimitry Andricdef : Pat<(and GR64:$src, 0x7fffffff), 7690b57cec5SDimitry Andric (LLGTR GR64:$src)>; 7700b57cec5SDimitry Andricdef : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 7710b57cec5SDimitry Andric (LLGT bdxaddr20only:$src)>; 7720b57cec5SDimitry Andric 7730b57cec5SDimitry Andric// Load and zero rightmost byte. 7740b57cec5SDimitry Andriclet Predicates = [FeatureLoadAndZeroRightmostByte] in { 7750b57cec5SDimitry Andric def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 7760b57cec5SDimitry Andric def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 7770b57cec5SDimitry Andric (LLZRGF bdxaddr20only:$src)>; 7780b57cec5SDimitry Andric} 7790b57cec5SDimitry Andric 7800b57cec5SDimitry Andric// Load and trap. 7810b57cec5SDimitry Andriclet Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 7820b57cec5SDimitry Andric def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 7830b57cec5SDimitry Andric def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 7840b57cec5SDimitry Andric} 7850b57cec5SDimitry Andric 7860b57cec5SDimitry Andric// Extend GR64s to GR128s. 7870b57cec5SDimitry Andriclet usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 7880b57cec5SDimitry Andric def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 7890b57cec5SDimitry Andric 7900b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 7910b57cec5SDimitry Andric// "Any" extensions 7920b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 7930b57cec5SDimitry Andric 7940b57cec5SDimitry Andric// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 7950b57cec5SDimitry Andricdef : Pat<(i64 (anyext GR32:$src)), 7960b57cec5SDimitry Andric (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 7970b57cec5SDimitry Andric 7980b57cec5SDimitry Andric// Extend GR64s to GR128s. 7990b57cec5SDimitry Andriclet usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 8000b57cec5SDimitry Andric def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 8010b57cec5SDimitry Andric 8020b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8030b57cec5SDimitry Andric// Truncations 8040b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8050b57cec5SDimitry Andric 8060b57cec5SDimitry Andric// Truncations of 64-bit registers to 32-bit registers. 8070b57cec5SDimitry Andricdef : Pat<(i32 (trunc GR64:$src)), 8080b57cec5SDimitry Andric (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 8090b57cec5SDimitry Andric 8100b57cec5SDimitry Andric// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 8110b57cec5SDimitry Andric// STC, STCY or STCH, depending on the choice of register. 8120b57cec5SDimitry Andricdef STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 8130b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 8140b57cec5SDimitry Andricdefm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 8150b57cec5SDimitry Andricdef STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 8160b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 8170b57cec5SDimitry Andric 8180b57cec5SDimitry Andric// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 8190b57cec5SDimitry Andric// STH, STHY or STHH, depending on the choice of register. 8200b57cec5SDimitry Andricdef STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 8210b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 8220b57cec5SDimitry Andricdefm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 8230b57cec5SDimitry Andricdef STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 8240b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 8250b57cec5SDimitry Andricdef STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 8260b57cec5SDimitry Andric 8270b57cec5SDimitry Andric// Truncations of 64-bit registers to memory. 8280b57cec5SDimitry Andricdefm : StoreGR64Pair<STC, STCY, truncstorei8>; 8290b57cec5SDimitry Andricdefm : StoreGR64Pair<STH, STHY, truncstorei16>; 8300b57cec5SDimitry Andricdef : StoreGR64PC<STHRL, aligned_truncstorei16>; 8310b57cec5SDimitry Andricdefm : StoreGR64Pair<ST, STY, truncstorei32>; 8320b57cec5SDimitry Andricdef : StoreGR64PC<STRL, aligned_truncstorei32>; 8330b57cec5SDimitry Andric 8340b57cec5SDimitry Andric// Store characters under mask -- not (yet) used for codegen. 8350b57cec5SDimitry Andricdefm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 8360b57cec5SDimitry Andricdef STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 8370b57cec5SDimitry Andric 8380b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8390b57cec5SDimitry Andric// Multi-register moves 8400b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8410b57cec5SDimitry Andric 8420b57cec5SDimitry Andric// Multi-register loads. 8430b57cec5SDimitry Andricdefm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 8440b57cec5SDimitry Andricdef LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 8450b57cec5SDimitry Andricdef LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 8460b57cec5SDimitry Andricdef LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 8470b57cec5SDimitry Andric 8480b57cec5SDimitry Andric// Multi-register stores. 8490b57cec5SDimitry Andricdefm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 8500b57cec5SDimitry Andricdef STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 8510b57cec5SDimitry Andricdef STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 8520b57cec5SDimitry Andric 8530b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8540b57cec5SDimitry Andric// Byte swaps 8550b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8560b57cec5SDimitry Andric 8570b57cec5SDimitry Andric// Byte-swapping register moves. 8580b57cec5SDimitry Andricdef LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 8590b57cec5SDimitry Andricdef LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 8600b57cec5SDimitry Andric 8610b57cec5SDimitry Andric// Byte-swapping loads. 8620b57cec5SDimitry Andricdef LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 8630b57cec5SDimitry Andricdef LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 8640b57cec5SDimitry Andricdef LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 8650b57cec5SDimitry Andric 8660b57cec5SDimitry Andric// Byte-swapping stores. 8670b57cec5SDimitry Andricdef STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 8680b57cec5SDimitry Andricdef STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 8690b57cec5SDimitry Andricdef STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 8700b57cec5SDimitry Andric 8710b57cec5SDimitry Andric// Byte-swapping memory-to-memory moves. 8720b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1 in 8730b57cec5SDimitry Andric def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 8740b57cec5SDimitry Andric 8750b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8760b57cec5SDimitry Andric// Load address instructions 8770b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8780b57cec5SDimitry Andric 8790b57cec5SDimitry Andric// Load BDX-style addresses. 8800b57cec5SDimitry Andriclet isAsCheapAsAMove = 1, isReMaterializable = 1 in 8810b57cec5SDimitry Andric defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 8820b57cec5SDimitry Andric 8830b57cec5SDimitry Andric// Load a PC-relative address. There's no version of this instruction 8840b57cec5SDimitry Andric// with a 16-bit offset, so there's no relaxation. 8850b57cec5SDimitry Andriclet isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 8860b57cec5SDimitry Andric def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 8870b57cec5SDimitry Andric 8880b57cec5SDimitry Andric// Load the Global Offset Table address. This will be lowered into a 8890b57cec5SDimitry Andric// larl $R1, _GLOBAL_OFFSET_TABLE_ 8900b57cec5SDimitry Andric// instruction. 8910b57cec5SDimitry Andricdef GOT : Alias<6, (outs GR64:$R1), (ins), 8920b57cec5SDimitry Andric [(set GR64:$R1, (global_offset_table))]>; 8930b57cec5SDimitry Andric 8940b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8950b57cec5SDimitry Andric// Absolute and Negation 8960b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8970b57cec5SDimitry Andric 8980b57cec5SDimitry Andriclet Defs = [CC] in { 8990b57cec5SDimitry Andric let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 900e8d8bef9SDimitry Andric def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 901e8d8bef9SDimitry Andric def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 9020b57cec5SDimitry Andric } 9030b57cec5SDimitry Andric let CCValues = 0xE, CompareZeroCCMask = 0xE in 9040b57cec5SDimitry Andric def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 9050b57cec5SDimitry Andric} 906e8d8bef9SDimitry Andricdefm : SXU<abs, LPGFR>; 9070b57cec5SDimitry Andric 9080b57cec5SDimitry Andriclet Defs = [CC] in { 9090b57cec5SDimitry Andric let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 9100b57cec5SDimitry Andric def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 9110b57cec5SDimitry Andric def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 9120b57cec5SDimitry Andric } 9130b57cec5SDimitry Andric let CCValues = 0xE, CompareZeroCCMask = 0xE in 9140b57cec5SDimitry Andric def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 9150b57cec5SDimitry Andric} 9160b57cec5SDimitry Andricdefm : SXU<z_inegabs, LNGFR>; 9170b57cec5SDimitry Andric 9180b57cec5SDimitry Andriclet Defs = [CC] in { 9190b57cec5SDimitry Andric let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 9200b57cec5SDimitry Andric def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 9210b57cec5SDimitry Andric def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 9220b57cec5SDimitry Andric } 9230b57cec5SDimitry Andric let CCValues = 0xE, CompareZeroCCMask = 0xE in 9240b57cec5SDimitry Andric def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 9250b57cec5SDimitry Andric} 9260b57cec5SDimitry Andricdefm : SXU<ineg, LCGFR>; 9270b57cec5SDimitry Andric 9280b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 9290b57cec5SDimitry Andric// Insertion 9300b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 9310b57cec5SDimitry Andric 9320b57cec5SDimitry Andriclet isCodeGenOnly = 1 in 9330b57cec5SDimitry Andric defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 9340b57cec5SDimitry Andricdefm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 9350b57cec5SDimitry Andric 9360b57cec5SDimitry Andricdefm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 9370b57cec5SDimitry Andricdefm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 9380b57cec5SDimitry Andric 9390b57cec5SDimitry Andricdefm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 9400b57cec5SDimitry Andricdefm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 9410b57cec5SDimitry Andric 9420b57cec5SDimitry Andric// Insert characters under mask -- not (yet) used for codegen. 9430b57cec5SDimitry Andriclet Defs = [CC] in { 9440b57cec5SDimitry Andric defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 9450b57cec5SDimitry Andric def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 9460b57cec5SDimitry Andric} 9470b57cec5SDimitry Andric 9480b57cec5SDimitry Andric// Insertions of a 16-bit immediate, leaving other bits unaffected. 9490b57cec5SDimitry Andric// We don't have or_as_insert equivalents of these operations because 9500b57cec5SDimitry Andric// OI is available instead. 9510b57cec5SDimitry Andric// 9520b57cec5SDimitry Andric// IIxMux expands to II[LH]x, depending on the choice of register. 9530b57cec5SDimitry Andricdef IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 9540b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 9550b57cec5SDimitry Andricdef IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 9560b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 9570b57cec5SDimitry Andricdef IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 9580b57cec5SDimitry Andricdef IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 9590b57cec5SDimitry Andricdef IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 9600b57cec5SDimitry Andricdef IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 9610b57cec5SDimitry Andricdef IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 9620b57cec5SDimitry Andricdef IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 9630b57cec5SDimitry Andricdef IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 9640b57cec5SDimitry Andricdef IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 9650b57cec5SDimitry Andric 9660b57cec5SDimitry Andric// ...likewise for 32-bit immediates. For GR32s this is a general 9670b57cec5SDimitry Andric// full-width move. (We use IILF rather than something like LLILF 9680b57cec5SDimitry Andric// for 32-bit moves because IILF leaves the upper 32 bits of the 9690b57cec5SDimitry Andric// GR64 unchanged.) 9700b57cec5SDimitry Andriclet isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 9710b57cec5SDimitry Andric def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 9720b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 9730b57cec5SDimitry Andric def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 9740b57cec5SDimitry Andric def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 9750b57cec5SDimitry Andric} 9760b57cec5SDimitry Andricdef IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 9770b57cec5SDimitry Andricdef IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 9780b57cec5SDimitry Andric 9790b57cec5SDimitry Andric// An alternative model of inserthf, with the first operand being 9800b57cec5SDimitry Andric// a zero-extended value. 9810b57cec5SDimitry Andricdef : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 9820b57cec5SDimitry Andric (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 9830b57cec5SDimitry Andric imm64hf32:$imm)>; 9840b57cec5SDimitry Andric 9850b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 9860b57cec5SDimitry Andric// Addition 9870b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 9880b57cec5SDimitry Andric 9890b57cec5SDimitry Andric// Addition producing a signed overflow flag. 990480093f4SDimitry Andriclet Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 9910b57cec5SDimitry Andric // Addition of a register. 9920b57cec5SDimitry Andric let isCommutable = 1 in { 9930b57cec5SDimitry Andric defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 9940b57cec5SDimitry Andric defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 9950b57cec5SDimitry Andric } 9960b57cec5SDimitry Andric def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 9970b57cec5SDimitry Andric 9980b57cec5SDimitry Andric // Addition to a high register. 9990b57cec5SDimitry Andric def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 10000b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10010b57cec5SDimitry Andric def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 10020b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10030b57cec5SDimitry Andric 10040b57cec5SDimitry Andric // Addition of signed 16-bit immediates. 10050b57cec5SDimitry Andric defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 10060b57cec5SDimitry Andric defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 10070b57cec5SDimitry Andric defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 10080b57cec5SDimitry Andric 10090b57cec5SDimitry Andric // Addition of signed 32-bit immediates. 10100b57cec5SDimitry Andric def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 10110b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10120b57cec5SDimitry Andric def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 10130b57cec5SDimitry Andric def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 10140b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10150b57cec5SDimitry Andric def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 10160b57cec5SDimitry Andric 10170b57cec5SDimitry Andric // Addition of memory. 10180b57cec5SDimitry Andric defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 10190b57cec5SDimitry Andric defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 10200b57cec5SDimitry Andric def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 10210b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 10220b57cec5SDimitry Andric def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 10230b57cec5SDimitry Andric defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 10240b57cec5SDimitry Andric 10250b57cec5SDimitry Andric // Addition to memory. 10260b57cec5SDimitry Andric def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 10270b57cec5SDimitry Andric def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 10280b57cec5SDimitry Andric} 10290b57cec5SDimitry Andricdefm : SXB<z_sadd, GR64, AGFR>; 10300b57cec5SDimitry Andric 10310b57cec5SDimitry Andric// Addition producing a carry. 1032480093f4SDimitry Andriclet Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 10330b57cec5SDimitry Andric // Addition of a register. 10340b57cec5SDimitry Andric let isCommutable = 1 in { 10350b57cec5SDimitry Andric defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 10360b57cec5SDimitry Andric defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 10370b57cec5SDimitry Andric } 10380b57cec5SDimitry Andric def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 10390b57cec5SDimitry Andric 10400b57cec5SDimitry Andric // Addition to a high register. 10410b57cec5SDimitry Andric def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 10420b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10430b57cec5SDimitry Andric def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 10440b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10450b57cec5SDimitry Andric 10460b57cec5SDimitry Andric // Addition of signed 16-bit immediates. 10470b57cec5SDimitry Andric def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 10480b57cec5SDimitry Andric Requires<[FeatureDistinctOps]>; 10490b57cec5SDimitry Andric def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 10500b57cec5SDimitry Andric Requires<[FeatureDistinctOps]>; 10510b57cec5SDimitry Andric 10520b57cec5SDimitry Andric // Addition of unsigned 32-bit immediates. 10530b57cec5SDimitry Andric def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 10540b57cec5SDimitry Andric def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 10550b57cec5SDimitry Andric 10560b57cec5SDimitry Andric // Addition of signed 32-bit immediates. 10570b57cec5SDimitry Andric def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 10580b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10590b57cec5SDimitry Andric 10600b57cec5SDimitry Andric // Addition of memory. 10610b57cec5SDimitry Andric defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 10620b57cec5SDimitry Andric def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 10630b57cec5SDimitry Andric defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 10640b57cec5SDimitry Andric 10650b57cec5SDimitry Andric // Addition to memory. 10660b57cec5SDimitry Andric def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 10670b57cec5SDimitry Andric def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 10680b57cec5SDimitry Andric} 10690b57cec5SDimitry Andricdefm : ZXB<z_uadd, GR64, ALGFR>; 10700b57cec5SDimitry Andric 10710b57cec5SDimitry Andric// Addition producing and using a carry. 1072480093f4SDimitry Andriclet Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 10730b57cec5SDimitry Andric // Addition of a register. 10740b57cec5SDimitry Andric def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 10750b57cec5SDimitry Andric def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 10760b57cec5SDimitry Andric 10770b57cec5SDimitry Andric // Addition of memory. 10780b57cec5SDimitry Andric def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 10790b57cec5SDimitry Andric def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 10800b57cec5SDimitry Andric} 10810b57cec5SDimitry Andric 10820b57cec5SDimitry Andric// Addition that does not modify the condition code. 10830b57cec5SDimitry Andricdef ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 10840b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 10850b57cec5SDimitry Andric 10860b57cec5SDimitry Andric 10870b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 10880b57cec5SDimitry Andric// Subtraction 10890b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 10900b57cec5SDimitry Andric 10910b57cec5SDimitry Andric// Subtraction producing a signed overflow flag. 1092480093f4SDimitry Andriclet Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1093480093f4SDimitry Andric CCIfNoSignedWrap = 1 in { 10940b57cec5SDimitry Andric // Subtraction of a register. 10950b57cec5SDimitry Andric defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 10960b57cec5SDimitry Andric def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 10970b57cec5SDimitry Andric defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 10980b57cec5SDimitry Andric 10990b57cec5SDimitry Andric // Subtraction from a high register. 11000b57cec5SDimitry Andric def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 11010b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 11020b57cec5SDimitry Andric def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 11030b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 11040b57cec5SDimitry Andric 11050b57cec5SDimitry Andric // Subtraction of memory. 11060b57cec5SDimitry Andric defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 11070b57cec5SDimitry Andric defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 11080b57cec5SDimitry Andric def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 11090b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 11100b57cec5SDimitry Andric def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 11110b57cec5SDimitry Andric defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 11120b57cec5SDimitry Andric} 11130b57cec5SDimitry Andricdefm : SXB<z_ssub, GR64, SGFR>; 11140b57cec5SDimitry Andric 11150b57cec5SDimitry Andric// Subtracting an immediate is the same as adding the negated immediate. 11160b57cec5SDimitry Andriclet AddedComplexity = 1 in { 11170b57cec5SDimitry Andric def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 11180b57cec5SDimitry Andric (AHIMux GR32:$src1, imm32sx16n:$src2)>, 11190b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 11200b57cec5SDimitry Andric def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 11210b57cec5SDimitry Andric (AFIMux GR32:$src1, simm32n:$src2)>, 11220b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 11230b57cec5SDimitry Andric def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 11240b57cec5SDimitry Andric (AHI GR32:$src1, imm32sx16n:$src2)>; 11250b57cec5SDimitry Andric def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 11260b57cec5SDimitry Andric (AFI GR32:$src1, simm32n:$src2)>; 11270b57cec5SDimitry Andric def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 11280b57cec5SDimitry Andric (AGHI GR64:$src1, imm64sx16n:$src2)>; 11290b57cec5SDimitry Andric def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 11300b57cec5SDimitry Andric (AGFI GR64:$src1, imm64sx32n:$src2)>; 11310b57cec5SDimitry Andric} 11320b57cec5SDimitry Andric 11330b57cec5SDimitry Andric// And vice versa in one special case, where we need to load a 11340b57cec5SDimitry Andric// constant into a register in any case, but the negated constant 11350b57cec5SDimitry Andric// requires fewer instructions to load. 11360b57cec5SDimitry Andricdef : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 11370b57cec5SDimitry Andric (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 11380b57cec5SDimitry Andricdef : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 11390b57cec5SDimitry Andric (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 11400b57cec5SDimitry Andric 11410b57cec5SDimitry Andric// Subtraction producing a carry. 1142480093f4SDimitry Andriclet Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 11430b57cec5SDimitry Andric // Subtraction of a register. 11440b57cec5SDimitry Andric defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 11450b57cec5SDimitry Andric def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 11460b57cec5SDimitry Andric defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 11470b57cec5SDimitry Andric 11480b57cec5SDimitry Andric // Subtraction from a high register. 11490b57cec5SDimitry Andric def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 11500b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 11510b57cec5SDimitry Andric def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 11520b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 11530b57cec5SDimitry Andric 11540b57cec5SDimitry Andric // Subtraction of unsigned 32-bit immediates. 11550b57cec5SDimitry Andric def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 11560b57cec5SDimitry Andric def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 11570b57cec5SDimitry Andric 11580b57cec5SDimitry Andric // Subtraction of memory. 11590b57cec5SDimitry Andric defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 11600b57cec5SDimitry Andric def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 11610b57cec5SDimitry Andric defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 11620b57cec5SDimitry Andric} 11630b57cec5SDimitry Andricdefm : ZXB<z_usub, GR64, SLGFR>; 11640b57cec5SDimitry Andric 11650b57cec5SDimitry Andric// Subtracting an immediate is the same as adding the negated immediate. 11660b57cec5SDimitry Andriclet AddedComplexity = 1 in { 11670b57cec5SDimitry Andric def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 11680b57cec5SDimitry Andric (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 11690b57cec5SDimitry Andric Requires<[FeatureDistinctOps]>; 11700b57cec5SDimitry Andric def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 11710b57cec5SDimitry Andric (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 11720b57cec5SDimitry Andric Requires<[FeatureDistinctOps]>; 11730b57cec5SDimitry Andric} 11740b57cec5SDimitry Andric 11750b57cec5SDimitry Andric// And vice versa in one special case (but we prefer addition). 11760b57cec5SDimitry Andricdef : Pat<(add GR64:$src1, imm64zx32n:$src2), 11770b57cec5SDimitry Andric (SLGFI GR64:$src1, imm64zx32n:$src2)>; 11780b57cec5SDimitry Andric 11790b57cec5SDimitry Andric// Subtraction producing and using a carry. 1180480093f4SDimitry Andriclet Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 11810b57cec5SDimitry Andric // Subtraction of a register. 11820b57cec5SDimitry Andric def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 11830b57cec5SDimitry Andric def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 11840b57cec5SDimitry Andric 11850b57cec5SDimitry Andric // Subtraction of memory. 11860b57cec5SDimitry Andric def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 11870b57cec5SDimitry Andric def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 11880b57cec5SDimitry Andric} 11890b57cec5SDimitry Andric 11900b57cec5SDimitry Andric 11910b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 11920b57cec5SDimitry Andric// AND 11930b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 11940b57cec5SDimitry Andric 11950b57cec5SDimitry Andriclet Defs = [CC] in { 11960b57cec5SDimitry Andric // ANDs of a register. 11970b57cec5SDimitry Andric let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 11980b57cec5SDimitry Andric defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 11990b57cec5SDimitry Andric defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 12000b57cec5SDimitry Andric } 12010b57cec5SDimitry Andric 12020b57cec5SDimitry Andric let isConvertibleToThreeAddress = 1 in { 12030b57cec5SDimitry Andric // ANDs of a 16-bit immediate, leaving other bits unaffected. 12040b57cec5SDimitry Andric // The CC result only reflects the 16-bit field, not the full register. 12050b57cec5SDimitry Andric // 12060b57cec5SDimitry Andric // NIxMux expands to NI[LH]x, depending on the choice of register. 12070b57cec5SDimitry Andric def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 12080b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 12090b57cec5SDimitry Andric def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 12100b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 12110b57cec5SDimitry Andric def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 12120b57cec5SDimitry Andric def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 12130b57cec5SDimitry Andric def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 12140b57cec5SDimitry Andric def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 12150b57cec5SDimitry Andric def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 12160b57cec5SDimitry Andric def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 12170b57cec5SDimitry Andric def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 12180b57cec5SDimitry Andric def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 12190b57cec5SDimitry Andric 12200b57cec5SDimitry Andric // ANDs of a 32-bit immediate, leaving other bits unaffected. 12210b57cec5SDimitry Andric // The CC result only reflects the 32-bit field, which means we can 12220b57cec5SDimitry Andric // use it as a zero indicator for i32 operations but not otherwise. 12230b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 12240b57cec5SDimitry Andric // Expands to NILF or NIHF, depending on the choice of register. 12250b57cec5SDimitry Andric def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 12260b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 12270b57cec5SDimitry Andric def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 12280b57cec5SDimitry Andric def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 12290b57cec5SDimitry Andric } 12300b57cec5SDimitry Andric def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 12310b57cec5SDimitry Andric def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 12320b57cec5SDimitry Andric } 12330b57cec5SDimitry Andric 12340b57cec5SDimitry Andric // ANDs of memory. 12350b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 12360b57cec5SDimitry Andric defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 12370b57cec5SDimitry Andric defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 12380b57cec5SDimitry Andric } 12390b57cec5SDimitry Andric 12400b57cec5SDimitry Andric // AND to memory 12410b57cec5SDimitry Andric defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 12420b57cec5SDimitry Andric 12430b57cec5SDimitry Andric // Block AND. 12440b57cec5SDimitry Andric let mayLoad = 1, mayStore = 1 in 1245349cc55cSDimitry Andric defm NC : MemorySS<"nc", 0xD4, z_nc>; 12460b57cec5SDimitry Andric} 12470b57cec5SDimitry Andricdefm : RMWIByte<and, bdaddr12pair, NI>; 12480b57cec5SDimitry Andricdefm : RMWIByte<and, bdaddr20pair, NIY>; 12490b57cec5SDimitry Andric 12500b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12510b57cec5SDimitry Andric// OR 12520b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12530b57cec5SDimitry Andric 12540b57cec5SDimitry Andriclet Defs = [CC] in { 12550b57cec5SDimitry Andric // ORs of a register. 12560b57cec5SDimitry Andric let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 12570b57cec5SDimitry Andric defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 12580b57cec5SDimitry Andric defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 12590b57cec5SDimitry Andric } 12600b57cec5SDimitry Andric 12610b57cec5SDimitry Andric // ORs of a 16-bit immediate, leaving other bits unaffected. 12620b57cec5SDimitry Andric // The CC result only reflects the 16-bit field, not the full register. 12630b57cec5SDimitry Andric // 12640b57cec5SDimitry Andric // OIxMux expands to OI[LH]x, depending on the choice of register. 12650b57cec5SDimitry Andric def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 12660b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 12670b57cec5SDimitry Andric def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 12680b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 12690b57cec5SDimitry Andric def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 12700b57cec5SDimitry Andric def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 12710b57cec5SDimitry Andric def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 12720b57cec5SDimitry Andric def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 12730b57cec5SDimitry Andric def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 12740b57cec5SDimitry Andric def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 12750b57cec5SDimitry Andric def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 12760b57cec5SDimitry Andric def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 12770b57cec5SDimitry Andric 12780b57cec5SDimitry Andric // ORs of a 32-bit immediate, leaving other bits unaffected. 12790b57cec5SDimitry Andric // The CC result only reflects the 32-bit field, which means we can 12800b57cec5SDimitry Andric // use it as a zero indicator for i32 operations but not otherwise. 12810b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 12820b57cec5SDimitry Andric // Expands to OILF or OIHF, depending on the choice of register. 12830b57cec5SDimitry Andric def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 12840b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 12850b57cec5SDimitry Andric def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 12860b57cec5SDimitry Andric def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 12870b57cec5SDimitry Andric } 12880b57cec5SDimitry Andric def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 12890b57cec5SDimitry Andric def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 12900b57cec5SDimitry Andric 12910b57cec5SDimitry Andric // ORs of memory. 12920b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 12930b57cec5SDimitry Andric defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 12940b57cec5SDimitry Andric defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 12950b57cec5SDimitry Andric } 12960b57cec5SDimitry Andric 12970b57cec5SDimitry Andric // OR to memory 12980b57cec5SDimitry Andric defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 12990b57cec5SDimitry Andric 13000b57cec5SDimitry Andric // Block OR. 13010b57cec5SDimitry Andric let mayLoad = 1, mayStore = 1 in 1302349cc55cSDimitry Andric defm OC : MemorySS<"oc", 0xD6, z_oc>; 13030b57cec5SDimitry Andric} 13040b57cec5SDimitry Andricdefm : RMWIByte<or, bdaddr12pair, OI>; 13050b57cec5SDimitry Andricdefm : RMWIByte<or, bdaddr20pair, OIY>; 13060b57cec5SDimitry Andric 13070b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13080b57cec5SDimitry Andric// XOR 13090b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13100b57cec5SDimitry Andric 13110b57cec5SDimitry Andriclet Defs = [CC] in { 13120b57cec5SDimitry Andric // XORs of a register. 13130b57cec5SDimitry Andric let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13140b57cec5SDimitry Andric defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 13150b57cec5SDimitry Andric defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 13160b57cec5SDimitry Andric } 13170b57cec5SDimitry Andric 13180b57cec5SDimitry Andric // XORs of a 32-bit immediate, leaving other bits unaffected. 13190b57cec5SDimitry Andric // The CC result only reflects the 32-bit field, which means we can 13200b57cec5SDimitry Andric // use it as a zero indicator for i32 operations but not otherwise. 13210b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13220b57cec5SDimitry Andric // Expands to XILF or XIHF, depending on the choice of register. 13230b57cec5SDimitry Andric def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 13240b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 13250b57cec5SDimitry Andric def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 13260b57cec5SDimitry Andric def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 13270b57cec5SDimitry Andric } 13280b57cec5SDimitry Andric def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 13290b57cec5SDimitry Andric def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 13300b57cec5SDimitry Andric 13310b57cec5SDimitry Andric // XORs of memory. 13320b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13330b57cec5SDimitry Andric defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 13340b57cec5SDimitry Andric defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 13350b57cec5SDimitry Andric } 13360b57cec5SDimitry Andric 13370b57cec5SDimitry Andric // XOR to memory 13380b57cec5SDimitry Andric defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 13390b57cec5SDimitry Andric 13400b57cec5SDimitry Andric // Block XOR. 13410b57cec5SDimitry Andric let mayLoad = 1, mayStore = 1 in 1342349cc55cSDimitry Andric defm XC : MemorySS<"xc", 0xD7, z_xc>; 13430b57cec5SDimitry Andric} 13440b57cec5SDimitry Andricdefm : RMWIByte<xor, bdaddr12pair, XI>; 13450b57cec5SDimitry Andricdefm : RMWIByte<xor, bdaddr20pair, XIY>; 13460b57cec5SDimitry Andric 13470b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13480b57cec5SDimitry Andric// Combined logical operations 13490b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13500b57cec5SDimitry Andric 13510b57cec5SDimitry Andriclet Predicates = [FeatureMiscellaneousExtensions3], 13520b57cec5SDimitry Andric Defs = [CC] in { 13530b57cec5SDimitry Andric // AND with complement. 13540b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13550b57cec5SDimitry Andric def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 13560b57cec5SDimitry Andric def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 13570b57cec5SDimitry Andric } 13580b57cec5SDimitry Andric 13590b57cec5SDimitry Andric // OR with complement. 13600b57cec5SDimitry Andric let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13610b57cec5SDimitry Andric def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 13620b57cec5SDimitry Andric def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 13630b57cec5SDimitry Andric } 13640b57cec5SDimitry Andric 13650b57cec5SDimitry Andric // NAND. 13660b57cec5SDimitry Andric let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13670b57cec5SDimitry Andric def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 13680b57cec5SDimitry Andric def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 13690b57cec5SDimitry Andric } 13700b57cec5SDimitry Andric 13710b57cec5SDimitry Andric // NOR. 13720b57cec5SDimitry Andric let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13730b57cec5SDimitry Andric def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 13740b57cec5SDimitry Andric def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 13750b57cec5SDimitry Andric } 13760b57cec5SDimitry Andric 13770b57cec5SDimitry Andric // NXOR. 13780b57cec5SDimitry Andric let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 13790b57cec5SDimitry Andric def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 13800b57cec5SDimitry Andric def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 13810b57cec5SDimitry Andric } 13820b57cec5SDimitry Andric} 13830b57cec5SDimitry Andric 13840b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13850b57cec5SDimitry Andric// Multiplication 13860b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13870b57cec5SDimitry Andric 13880b57cec5SDimitry Andric// Multiplication of a register, setting the condition code. We prefer these 13890b57cec5SDimitry Andric// over MS(G)R if available, even though we cannot use the condition code, 13900b57cec5SDimitry Andric// since they are three-operand instructions. 13910b57cec5SDimitry Andriclet Predicates = [FeatureMiscellaneousExtensions2], 13920b57cec5SDimitry Andric Defs = [CC], isCommutable = 1 in { 13930b57cec5SDimitry Andric def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 13940b57cec5SDimitry Andric def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 13950b57cec5SDimitry Andric} 13960b57cec5SDimitry Andric 13970b57cec5SDimitry Andric// Multiplication of a register. 13980b57cec5SDimitry Andriclet isCommutable = 1 in { 13990b57cec5SDimitry Andric def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 14000b57cec5SDimitry Andric def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 14010b57cec5SDimitry Andric} 14020b57cec5SDimitry Andricdef MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 14030b57cec5SDimitry Andricdefm : SXB<mul, GR64, MSGFR>; 14040b57cec5SDimitry Andric 14050b57cec5SDimitry Andric// Multiplication of a signed 16-bit immediate. 14060b57cec5SDimitry Andricdef MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 14070b57cec5SDimitry Andricdef MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 14080b57cec5SDimitry Andric 14090b57cec5SDimitry Andric// Multiplication of a signed 32-bit immediate. 14100b57cec5SDimitry Andricdef MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 14110b57cec5SDimitry Andricdef MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 14120b57cec5SDimitry Andric 14130b57cec5SDimitry Andric// Multiplication of memory. 14140b57cec5SDimitry Andricdefm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 14150b57cec5SDimitry Andricdefm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 14160b57cec5SDimitry Andricdef MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 14170b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 14180b57cec5SDimitry Andricdef MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 14190b57cec5SDimitry Andricdef MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 14200b57cec5SDimitry Andric 14210b57cec5SDimitry Andric// Multiplication of memory, setting the condition code. 14220b57cec5SDimitry Andriclet Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 14235ffd83dbSDimitry Andric defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 14245ffd83dbSDimitry Andric defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 14250b57cec5SDimitry Andric} 14260b57cec5SDimitry Andric 14270b57cec5SDimitry Andric// Multiplication of a register, producing two results. 14280b57cec5SDimitry Andricdef MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 14290b57cec5SDimitry Andricdef MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 14300b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 14310b57cec5SDimitry Andricdef MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 14320b57cec5SDimitry Andricdef MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 14330b57cec5SDimitry Andric 14340b57cec5SDimitry Andricdef : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 14350b57cec5SDimitry Andric (MGRK GR64:$src1, GR64:$src2)>; 14360b57cec5SDimitry Andricdef : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 14370b57cec5SDimitry Andric (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 14380b57cec5SDimitry Andric 14390b57cec5SDimitry Andric// Multiplication of memory, producing two results. 14400b57cec5SDimitry Andricdef M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 14410b57cec5SDimitry Andricdef MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 14420b57cec5SDimitry Andricdef MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 14430b57cec5SDimitry Andric Requires<[FeatureMiscellaneousExtensions2]>; 14440b57cec5SDimitry Andricdef ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 14450b57cec5SDimitry Andricdef MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 14460b57cec5SDimitry Andric 14470b57cec5SDimitry Andricdef : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 14480b57cec5SDimitry Andric (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 14490b57cec5SDimitry Andricdef : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 14500b57cec5SDimitry Andric (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 14510b57cec5SDimitry Andric 14520b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14530b57cec5SDimitry Andric// Division and remainder 14540b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14550b57cec5SDimitry Andric 14560b57cec5SDimitry Andriclet hasSideEffects = 1 in { // Do not speculatively execute. 14570b57cec5SDimitry Andric // Division and remainder, from registers. 14580b57cec5SDimitry Andric def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 14590b57cec5SDimitry Andric def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 14600b57cec5SDimitry Andric def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 14610b57cec5SDimitry Andric def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 14620b57cec5SDimitry Andric def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 14630b57cec5SDimitry Andric 14640b57cec5SDimitry Andric // Division and remainder, from memory. 14650b57cec5SDimitry Andric def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 14660b57cec5SDimitry Andric def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 14670b57cec5SDimitry Andric def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 14680b57cec5SDimitry Andric def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 14690b57cec5SDimitry Andric def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 14700b57cec5SDimitry Andric} 14710b57cec5SDimitry Andricdef : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 14720b57cec5SDimitry Andric (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 14730b57cec5SDimitry Andricdef : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 14740b57cec5SDimitry Andric (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 14750b57cec5SDimitry Andricdef : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 14760b57cec5SDimitry Andric (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 14770b57cec5SDimitry Andricdef : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 14780b57cec5SDimitry Andric (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 14790b57cec5SDimitry Andric 14800b57cec5SDimitry Andricdef : Pat<(z_udivrem GR32:$src1, GR32:$src2), 14810b57cec5SDimitry Andric (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 14820b57cec5SDimitry Andric subreg_l32)), GR32:$src2)>; 14830b57cec5SDimitry Andricdef : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 14840b57cec5SDimitry Andric (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 14850b57cec5SDimitry Andric subreg_l32)), bdxaddr20only:$src2)>; 14860b57cec5SDimitry Andricdef : Pat<(z_udivrem GR64:$src1, GR64:$src2), 14870b57cec5SDimitry Andric (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 14880b57cec5SDimitry Andricdef : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 14890b57cec5SDimitry Andric (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 14900b57cec5SDimitry Andric 14910b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14920b57cec5SDimitry Andric// Shifts 14930b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14940b57cec5SDimitry Andric 14950b57cec5SDimitry Andric// Logical shift left. 14960b57cec5SDimitry Andricdefm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 14970b57cec5SDimitry Andricdef SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 14980b57cec5SDimitry Andricdef SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 14990b57cec5SDimitry Andric 15000b57cec5SDimitry Andric// Arithmetic shift left. 15010b57cec5SDimitry Andriclet Defs = [CC] in { 15020b57cec5SDimitry Andric defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 15030b57cec5SDimitry Andric def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 15040b57cec5SDimitry Andric def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 15050b57cec5SDimitry Andric} 15060b57cec5SDimitry Andric 15070b57cec5SDimitry Andric// Logical shift right. 15080b57cec5SDimitry Andricdefm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 15090b57cec5SDimitry Andricdef SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 15100b57cec5SDimitry Andricdef SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 15110b57cec5SDimitry Andric 15120b57cec5SDimitry Andric// Arithmetic shift right. 15130b57cec5SDimitry Andriclet Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 15140b57cec5SDimitry Andric defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 15150b57cec5SDimitry Andric def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 15160b57cec5SDimitry Andric def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 15170b57cec5SDimitry Andric} 15180b57cec5SDimitry Andric 15190b57cec5SDimitry Andric// Rotate left. 15200b57cec5SDimitry Andricdef RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 15210b57cec5SDimitry Andricdef RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 15220b57cec5SDimitry Andric 15230b57cec5SDimitry Andric// Rotate second operand left and inserted selected bits into first operand. 15240b57cec5SDimitry Andric// These can act like 32-bit operands provided that the constant start and 15250b57cec5SDimitry Andric// end bits (operands 2 and 3) are in the range [32, 64). 15260b57cec5SDimitry Andriclet Defs = [CC] in { 15270b57cec5SDimitry Andric let isCodeGenOnly = 1 in 15280b57cec5SDimitry Andric def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 15290b57cec5SDimitry Andric let CCValues = 0xE, CompareZeroCCMask = 0xE in 15300b57cec5SDimitry Andric def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 15310b57cec5SDimitry Andric} 15320b57cec5SDimitry Andric 15330b57cec5SDimitry Andric// On zEC12 we have a variant of RISBG that does not set CC. 15340b57cec5SDimitry Andriclet Predicates = [FeatureMiscellaneousExtensions] in 15350b57cec5SDimitry Andric def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 15360b57cec5SDimitry Andric 15370b57cec5SDimitry Andric// Forms of RISBG that only affect one word of the destination register. 15380b57cec5SDimitry Andric// They do not set CC. 15390b57cec5SDimitry Andriclet Predicates = [FeatureHighWord] in { 15400b57cec5SDimitry Andric def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 15410b57cec5SDimitry Andric def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 15420b57cec5SDimitry Andric def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 15430b57cec5SDimitry Andric def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 15440b57cec5SDimitry Andric def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 15450b57cec5SDimitry Andric def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 15460b57cec5SDimitry Andric def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 15470b57cec5SDimitry Andric} 15480b57cec5SDimitry Andric 15490b57cec5SDimitry Andric// Rotate second operand left and perform a logical operation with selected 15500b57cec5SDimitry Andric// bits of the first operand. The CC result only describes the selected bits, 15510b57cec5SDimitry Andric// so isn't useful for a full comparison against zero. 15520b57cec5SDimitry Andriclet Defs = [CC] in { 15530b57cec5SDimitry Andric def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 15540b57cec5SDimitry Andric def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 15550b57cec5SDimitry Andric def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 15560b57cec5SDimitry Andric} 15570b57cec5SDimitry Andric 15580b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 15590b57cec5SDimitry Andric// Comparison 15600b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 15610b57cec5SDimitry Andric 15620b57cec5SDimitry Andric// Signed comparisons. We put these before the unsigned comparisons because 15630b57cec5SDimitry Andric// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 15640b57cec5SDimitry Andric// of the unsigned forms do. 15650b57cec5SDimitry Andriclet Defs = [CC], CCValues = 0xE in { 15660b57cec5SDimitry Andric // Comparison with a register. 15670b57cec5SDimitry Andric def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 15680b57cec5SDimitry Andric def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 15690b57cec5SDimitry Andric def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 15700b57cec5SDimitry Andric 15710b57cec5SDimitry Andric // Comparison with a high register. 15720b57cec5SDimitry Andric def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 15730b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 15740b57cec5SDimitry Andric def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 15750b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 15760b57cec5SDimitry Andric 15770b57cec5SDimitry Andric // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 15780b57cec5SDimitry Andric // depending on the choice of register. 15790b57cec5SDimitry Andric def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 15800b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 15810b57cec5SDimitry Andric def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 15820b57cec5SDimitry Andric def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 15830b57cec5SDimitry Andric 15840b57cec5SDimitry Andric // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 15850b57cec5SDimitry Andric // depending on the choice of register. 15860b57cec5SDimitry Andric def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 15870b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 15880b57cec5SDimitry Andric def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 15890b57cec5SDimitry Andric def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 15900b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 15910b57cec5SDimitry Andric def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 15920b57cec5SDimitry Andric 15930b57cec5SDimitry Andric // Comparison with memory. 15940b57cec5SDimitry Andric defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 15950b57cec5SDimitry Andric def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 15960b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 15970b57cec5SDimitry Andric defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 15980b57cec5SDimitry Andric def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 15990b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16000b57cec5SDimitry Andric def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 16010b57cec5SDimitry Andric def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 16020b57cec5SDimitry Andric def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 16030b57cec5SDimitry Andric def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 16040b57cec5SDimitry Andric def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 16050b57cec5SDimitry Andric def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 16060b57cec5SDimitry Andric def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 16070b57cec5SDimitry Andric def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 16080b57cec5SDimitry Andric 16090b57cec5SDimitry Andric // Comparison between memory and a signed 16-bit immediate. 16100b57cec5SDimitry Andric def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 16110b57cec5SDimitry Andric def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 16120b57cec5SDimitry Andric def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 16130b57cec5SDimitry Andric} 16140b57cec5SDimitry Andricdefm : SXB<z_scmp, GR64, CGFR>; 16150b57cec5SDimitry Andric 16160b57cec5SDimitry Andric// Unsigned comparisons. 16170b57cec5SDimitry Andriclet Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 16180b57cec5SDimitry Andric // Comparison with a register. 16190b57cec5SDimitry Andric def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 16200b57cec5SDimitry Andric def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 16210b57cec5SDimitry Andric def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 16220b57cec5SDimitry Andric 16230b57cec5SDimitry Andric // Comparison with a high register. 16240b57cec5SDimitry Andric def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 16250b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16260b57cec5SDimitry Andric def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 16270b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16280b57cec5SDimitry Andric 16290b57cec5SDimitry Andric // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 16300b57cec5SDimitry Andric // or CLIH, depending on the choice of register. 16310b57cec5SDimitry Andric def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 16320b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16330b57cec5SDimitry Andric def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 16340b57cec5SDimitry Andric def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 16350b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16360b57cec5SDimitry Andric def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 16370b57cec5SDimitry Andric 16380b57cec5SDimitry Andric // Comparison with memory. 16390b57cec5SDimitry Andric def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 16400b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16410b57cec5SDimitry Andric defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 16420b57cec5SDimitry Andric def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 16430b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16440b57cec5SDimitry Andric def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 16450b57cec5SDimitry Andric def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 16460b57cec5SDimitry Andric def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 16470b57cec5SDimitry Andric aligned_azextloadi16>; 16480b57cec5SDimitry Andric def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 16490b57cec5SDimitry Andric aligned_load>; 16500b57cec5SDimitry Andric def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 16510b57cec5SDimitry Andric aligned_azextloadi16>; 16520b57cec5SDimitry Andric def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 16530b57cec5SDimitry Andric aligned_azextloadi32>; 16540b57cec5SDimitry Andric def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 16550b57cec5SDimitry Andric aligned_load>; 16560b57cec5SDimitry Andric 16570b57cec5SDimitry Andric // Comparison between memory and an unsigned 8-bit immediate. 16580b57cec5SDimitry Andric defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 16590b57cec5SDimitry Andric 16600b57cec5SDimitry Andric // Comparison between memory and an unsigned 16-bit immediate. 16610b57cec5SDimitry Andric def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 16620b57cec5SDimitry Andric def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 16630b57cec5SDimitry Andric def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 16640b57cec5SDimitry Andric} 16650b57cec5SDimitry Andricdefm : ZXB<z_ucmp, GR64, CLGFR>; 16660b57cec5SDimitry Andric 16670b57cec5SDimitry Andric// Memory-to-memory comparison. 16680b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC] in { 1669349cc55cSDimitry Andric defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>; 16700b57cec5SDimitry Andric def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 16710b57cec5SDimitry Andric def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 16720b57cec5SDimitry Andric def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 16730b57cec5SDimitry Andric} 16740b57cec5SDimitry Andric 16750b57cec5SDimitry Andric// String comparison. 16760b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC] in 16770b57cec5SDimitry Andric defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 16780b57cec5SDimitry Andric 16790b57cec5SDimitry Andric// Test under mask. 16800b57cec5SDimitry Andriclet Defs = [CC] in { 16810b57cec5SDimitry Andric // TMxMux expands to TM[LH]x, depending on the choice of register. 16820b57cec5SDimitry Andric def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 16830b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16840b57cec5SDimitry Andric def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 16850b57cec5SDimitry Andric Requires<[FeatureHighWord]>; 16860b57cec5SDimitry Andric def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 16870b57cec5SDimitry Andric def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 16880b57cec5SDimitry Andric def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 16890b57cec5SDimitry Andric def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 16900b57cec5SDimitry Andric 16910b57cec5SDimitry Andric def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 16920b57cec5SDimitry Andric def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 16930b57cec5SDimitry Andric def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 16940b57cec5SDimitry Andric def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 16950b57cec5SDimitry Andric 16960b57cec5SDimitry Andric defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 16970b57cec5SDimitry Andric} 16980b57cec5SDimitry Andric 16990b57cec5SDimitry Andricdef TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 17000b57cec5SDimitry Andricdef TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 17010b57cec5SDimitry Andric 17020b57cec5SDimitry Andric// Compare logical characters under mask -- not (yet) used for codegen. 17030b57cec5SDimitry Andriclet Defs = [CC] in { 17040b57cec5SDimitry Andric defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 17050b57cec5SDimitry Andric def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 17060b57cec5SDimitry Andric} 17070b57cec5SDimitry Andric 17080b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 17090b57cec5SDimitry Andric// Prefetch and execution hint 17100b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 17110b57cec5SDimitry Andric 17120b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1 in { 17130b57cec5SDimitry Andric def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 17140b57cec5SDimitry Andric def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 17150b57cec5SDimitry Andric} 17160b57cec5SDimitry Andric 17170b57cec5SDimitry Andriclet Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 17180b57cec5SDimitry Andric // Branch Prediction Preload 17190b57cec5SDimitry Andric def BPP : BranchPreloadSMI<"bpp", 0xC7>; 17200b57cec5SDimitry Andric def BPRP : BranchPreloadMII<"bprp", 0xC5>; 17210b57cec5SDimitry Andric 17220b57cec5SDimitry Andric // Next Instruction Access Intent 17230b57cec5SDimitry Andric def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 17240b57cec5SDimitry Andric} 17250b57cec5SDimitry Andric 17260b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 17270b57cec5SDimitry Andric// Atomic operations 17280b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 17290b57cec5SDimitry Andric 17300b57cec5SDimitry Andric// A serialization instruction that acts as a barrier for all memory 17310b57cec5SDimitry Andric// accesses, which expands to "bcr 14, 0". 17320b57cec5SDimitry Andriclet hasSideEffects = 1 in 17330b57cec5SDimitry Andricdef Serialize : Alias<2, (outs), (ins), []>; 17340b57cec5SDimitry Andric 17350b57cec5SDimitry Andriclet Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 17360b57cec5SDimitry Andric def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 17370b57cec5SDimitry Andric def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 17380b57cec5SDimitry Andric def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 17390b57cec5SDimitry Andric def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 17400b57cec5SDimitry Andric def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 17410b57cec5SDimitry Andric def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 17420b57cec5SDimitry Andric def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 17430b57cec5SDimitry Andric def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 17440b57cec5SDimitry Andric def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 17450b57cec5SDimitry Andric def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 17460b57cec5SDimitry Andric} 17470b57cec5SDimitry Andric 17480b57cec5SDimitry Andricdef ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 17490b57cec5SDimitry Andric 17500b57cec5SDimitry Andricdef ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 17510b57cec5SDimitry Andricdef ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 17520b57cec5SDimitry Andric 17530b57cec5SDimitry Andricdef ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 17540b57cec5SDimitry Andric 17550b57cec5SDimitry Andricdef ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 17560b57cec5SDimitry Andricdef ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 17570b57cec5SDimitry Andric 17580b57cec5SDimitry Andricdef ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 17590b57cec5SDimitry Andricdef ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 17600b57cec5SDimitry Andric 17610b57cec5SDimitry Andricdef ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 17620b57cec5SDimitry Andricdef ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 17630b57cec5SDimitry Andric 17640b57cec5SDimitry Andricdef ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 17650b57cec5SDimitry Andricdef ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 17660b57cec5SDimitry Andric imm32lh16c>; 17670b57cec5SDimitry Andric 17680b57cec5SDimitry Andricdef ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 17690b57cec5SDimitry Andricdef ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 17700b57cec5SDimitry Andricdef ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 17710b57cec5SDimitry Andricdef ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 17720b57cec5SDimitry Andric 17730b57cec5SDimitry Andricdef ATOMIC_CMP_SWAPW 17740b57cec5SDimitry Andric : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 17750b57cec5SDimitry Andric ADDR32:$bitshift, ADDR32:$negbitshift, 17760b57cec5SDimitry Andric uimm32:$bitsize), 17770b57cec5SDimitry Andric [(set GR32:$dst, 17780b57cec5SDimitry Andric (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 17790b57cec5SDimitry Andric ADDR32:$bitshift, ADDR32:$negbitshift, 17800b57cec5SDimitry Andric uimm32:$bitsize))]> { 17810b57cec5SDimitry Andric let Defs = [CC]; 17820b57cec5SDimitry Andric let mayLoad = 1; 17830b57cec5SDimitry Andric let mayStore = 1; 17840b57cec5SDimitry Andric let usesCustomInserter = 1; 17850b57cec5SDimitry Andric let hasNoSchedulingInfo = 1; 17860b57cec5SDimitry Andric} 17870b57cec5SDimitry Andric 17880b57cec5SDimitry Andric// Test and set. 17890b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC] in 17900b57cec5SDimitry Andric def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 17910b57cec5SDimitry Andric 17920b57cec5SDimitry Andric// Compare and swap. 17930b57cec5SDimitry Andriclet Defs = [CC] in { 17940b57cec5SDimitry Andric defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 17950b57cec5SDimitry Andric def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 17960b57cec5SDimitry Andric} 17970b57cec5SDimitry Andric 17980b57cec5SDimitry Andric// Compare double and swap. 17990b57cec5SDimitry Andriclet Defs = [CC] in { 18000b57cec5SDimitry Andric defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 18010b57cec5SDimitry Andric def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 18020b57cec5SDimitry Andric} 18030b57cec5SDimitry Andric 18040b57cec5SDimitry Andric// Compare and swap and store. 18050b57cec5SDimitry Andriclet Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 18060b57cec5SDimitry Andric def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 18070b57cec5SDimitry Andric 18080b57cec5SDimitry Andric// Perform locked operation. 18090b57cec5SDimitry Andriclet Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 18100b57cec5SDimitry Andric def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 18110b57cec5SDimitry Andric 18120b57cec5SDimitry Andric// Load/store pair from/to quadword. 18130b57cec5SDimitry Andricdef LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 18140b57cec5SDimitry Andricdef STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 18150b57cec5SDimitry Andric 18160b57cec5SDimitry Andric// Load pair disjoint. 18170b57cec5SDimitry Andriclet Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 18180b57cec5SDimitry Andric def LPD : BinarySSF<"lpd", 0xC84, GR128>; 18190b57cec5SDimitry Andric def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 18200b57cec5SDimitry Andric} 18210b57cec5SDimitry Andric 18220b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18230b57cec5SDimitry Andric// Translate and convert 18240b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18250b57cec5SDimitry Andric 18260b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1 in 18270b57cec5SDimitry Andric def TR : SideEffectBinarySSa<"tr", 0xDC>; 18280b57cec5SDimitry Andric 18290b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC, R0L, R1D] in { 18300b57cec5SDimitry Andric def TRT : SideEffectBinarySSa<"trt", 0xDD>; 18310b57cec5SDimitry Andric def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 18320b57cec5SDimitry Andric} 18330b57cec5SDimitry Andric 18340b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Uses = [R0L] in 18350b57cec5SDimitry Andric def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 18360b57cec5SDimitry Andric 18370b57cec5SDimitry Andriclet mayLoad = 1, Uses = [R1D], Defs = [CC] in { 18380b57cec5SDimitry Andric defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 18390b57cec5SDimitry Andric defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 18400b57cec5SDimitry Andric} 18410b57cec5SDimitry Andric 18420b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 18430b57cec5SDimitry Andric defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 18440b57cec5SDimitry Andric defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 18450b57cec5SDimitry Andric defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 18460b57cec5SDimitry Andric defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 18470b57cec5SDimitry Andric} 18480b57cec5SDimitry Andric 18490b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Defs = [CC] in { 18500b57cec5SDimitry Andric defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 18510b57cec5SDimitry Andric defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 18520b57cec5SDimitry Andric defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 18530b57cec5SDimitry Andric defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 18540b57cec5SDimitry Andric def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 18550b57cec5SDimitry Andric def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 18560b57cec5SDimitry Andric 18570b57cec5SDimitry Andric let isAsmParserOnly = 1 in { 18580b57cec5SDimitry Andric defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 18590b57cec5SDimitry Andric defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 18600b57cec5SDimitry Andric } 18610b57cec5SDimitry Andric} 18620b57cec5SDimitry Andric 18630b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18640b57cec5SDimitry Andric// Message-security assist 18650b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18660b57cec5SDimitry Andric 18670b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 18680b57cec5SDimitry Andric def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 18690b57cec5SDimitry Andric def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 18700b57cec5SDimitry Andric 18710b57cec5SDimitry Andric def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 18720b57cec5SDimitry Andric def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 18730b57cec5SDimitry Andric def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 18740b57cec5SDimitry Andric 18750b57cec5SDimitry Andric let Predicates = [FeatureMessageSecurityAssist4] in { 18760b57cec5SDimitry Andric def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 18770b57cec5SDimitry Andric def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 18780b57cec5SDimitry Andric def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 18790b57cec5SDimitry Andric GR128, GR128, GR128>; 18800b57cec5SDimitry Andric def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 18810b57cec5SDimitry Andric } 18820b57cec5SDimitry Andric 18830b57cec5SDimitry Andric let Predicates = [FeatureMessageSecurityAssist5] in 18840b57cec5SDimitry Andric def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 18850b57cec5SDimitry Andric let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 18860b57cec5SDimitry Andric def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 18870b57cec5SDimitry Andric 18880b57cec5SDimitry Andric let Predicates = [FeatureMessageSecurityAssist8] in 18890b57cec5SDimitry Andric def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 18900b57cec5SDimitry Andric GR128, GR128, GR128>; 18910b57cec5SDimitry Andric 18920b57cec5SDimitry Andric let Predicates = [FeatureMessageSecurityAssist9] in 18930b57cec5SDimitry Andric def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 18940b57cec5SDimitry Andric} 18950b57cec5SDimitry Andric 18960b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18970b57cec5SDimitry Andric// Guarded storage 18980b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18990b57cec5SDimitry Andric 19000b57cec5SDimitry Andric// These instructions use and/or modify the guarded storage control 19010b57cec5SDimitry Andric// registers, which we do not otherwise model, so they should have 19020b57cec5SDimitry Andric// hasSideEffects. 19030b57cec5SDimitry Andriclet Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 19040b57cec5SDimitry Andric def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 19050b57cec5SDimitry Andric def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 19060b57cec5SDimitry Andric 19070b57cec5SDimitry Andric let mayLoad = 1 in 19080b57cec5SDimitry Andric def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 19090b57cec5SDimitry Andric let mayStore = 1 in 19100b57cec5SDimitry Andric def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 19110b57cec5SDimitry Andric} 19120b57cec5SDimitry Andric 19130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19140b57cec5SDimitry Andric// Decimal arithmetic 19150b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19160b57cec5SDimitry Andric 19170b57cec5SDimitry Andricdefm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 19180b57cec5SDimitry Andricdef CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 19190b57cec5SDimitry Andric 19200b57cec5SDimitry Andricdefm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 19210b57cec5SDimitry Andricdef CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 19220b57cec5SDimitry Andric 19230b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1 in { 19240b57cec5SDimitry Andric def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 19250b57cec5SDimitry Andric def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 19260b57cec5SDimitry Andric def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 19270b57cec5SDimitry Andric 19280b57cec5SDimitry Andric def PACK : SideEffectBinarySSb<"pack", 0xF2>; 19290b57cec5SDimitry Andric def PKA : SideEffectBinarySSf<"pka", 0xE9>; 19300b57cec5SDimitry Andric def PKU : SideEffectBinarySSf<"pku", 0xE1>; 19310b57cec5SDimitry Andric def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 19320b57cec5SDimitry Andric let Defs = [CC] in { 19330b57cec5SDimitry Andric def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 19340b57cec5SDimitry Andric def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 19350b57cec5SDimitry Andric } 19360b57cec5SDimitry Andric} 19370b57cec5SDimitry Andric 19380b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1 in { 19390b57cec5SDimitry Andric let Defs = [CC] in { 19400b57cec5SDimitry Andric def AP : SideEffectBinarySSb<"ap", 0xFA>; 19410b57cec5SDimitry Andric def SP : SideEffectBinarySSb<"sp", 0xFB>; 19420b57cec5SDimitry Andric def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 19430b57cec5SDimitry Andric def SRP : SideEffectTernarySSc<"srp", 0xF0>; 19440b57cec5SDimitry Andric } 19450b57cec5SDimitry Andric def MP : SideEffectBinarySSb<"mp", 0xFC>; 19460b57cec5SDimitry Andric def DP : SideEffectBinarySSb<"dp", 0xFD>; 19470b57cec5SDimitry Andric let Defs = [CC] in { 19480b57cec5SDimitry Andric def ED : SideEffectBinarySSa<"ed", 0xDE>; 19490b57cec5SDimitry Andric def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 19500b57cec5SDimitry Andric } 19510b57cec5SDimitry Andric} 19520b57cec5SDimitry Andric 19530b57cec5SDimitry Andriclet Defs = [CC] in { 19540b57cec5SDimitry Andric def CP : CompareSSb<"cp", 0xF9>; 19550b57cec5SDimitry Andric def TP : TestRSL<"tp", 0xEBC0>; 19560b57cec5SDimitry Andric} 19570b57cec5SDimitry Andric 19580b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19590b57cec5SDimitry Andric// Access registers 19600b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19610b57cec5SDimitry Andric 19620b57cec5SDimitry Andric// Read a 32-bit access register into a GR32. As with all GR32 operations, 19630b57cec5SDimitry Andric// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 19640b57cec5SDimitry Andric// when a 64-bit address is stored in a pair of access registers. 19650b57cec5SDimitry Andricdef EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 19660b57cec5SDimitry Andric 19670b57cec5SDimitry Andric// Set access register. 19680b57cec5SDimitry Andricdef SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 19690b57cec5SDimitry Andric 19700b57cec5SDimitry Andric// Copy access register. 19710b57cec5SDimitry Andricdef CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 19720b57cec5SDimitry Andric 19730b57cec5SDimitry Andric// Load address extended. 19740b57cec5SDimitry Andricdefm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 19750b57cec5SDimitry Andric 19760b57cec5SDimitry Andric// Load access multiple. 19770b57cec5SDimitry Andricdefm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 19780b57cec5SDimitry Andric 19790b57cec5SDimitry Andric// Store access multiple. 19800b57cec5SDimitry Andricdefm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 19810b57cec5SDimitry Andric 19820b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19830b57cec5SDimitry Andric// Program mask and addressing mode 19840b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19850b57cec5SDimitry Andric 19860b57cec5SDimitry Andric// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 19870b57cec5SDimitry Andriclet Uses = [CC] in 19880b57cec5SDimitry Andric def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 19890b57cec5SDimitry Andric 19900b57cec5SDimitry Andric// Set CC and program mask from a register. 19910b57cec5SDimitry Andriclet hasSideEffects = 1, Defs = [CC] in 19920b57cec5SDimitry Andric def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 19930b57cec5SDimitry Andric 19940b57cec5SDimitry Andric// Branch and link - like BAS, but also extracts CC and program mask. 19950b57cec5SDimitry Andriclet isCall = 1, Uses = [CC], Defs = [CC] in { 19960b57cec5SDimitry Andric def BAL : CallRX<"bal", 0x45>; 19970b57cec5SDimitry Andric def BALR : CallRR<"balr", 0x05>; 19980b57cec5SDimitry Andric} 19990b57cec5SDimitry Andric 20000b57cec5SDimitry Andric// Test addressing mode. 20010b57cec5SDimitry Andriclet Defs = [CC] in 20020b57cec5SDimitry Andric def TAM : SideEffectInherentE<"tam", 0x010B>; 20030b57cec5SDimitry Andric 20040b57cec5SDimitry Andric// Set addressing mode. 20050b57cec5SDimitry Andriclet hasSideEffects = 1 in { 20060b57cec5SDimitry Andric def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 20070b57cec5SDimitry Andric def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 20080b57cec5SDimitry Andric def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 20090b57cec5SDimitry Andric} 20100b57cec5SDimitry Andric 20110b57cec5SDimitry Andric// Branch and set mode. Not really a call, but also sets an output register. 20120b57cec5SDimitry Andriclet isBranch = 1, isTerminator = 1, isBarrier = 1 in 20130b57cec5SDimitry Andric def BSM : CallRR<"bsm", 0x0B>; 20140b57cec5SDimitry Andric 20150b57cec5SDimitry Andric// Branch and save and set mode. 20160b57cec5SDimitry Andriclet isCall = 1, Defs = [CC] in 20170b57cec5SDimitry Andric def BASSM : CallRR<"bassm", 0x0C>; 20180b57cec5SDimitry Andric 20190b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20200b57cec5SDimitry Andric// Transactional execution 20210b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20220b57cec5SDimitry Andric 20230b57cec5SDimitry Andriclet hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 20240b57cec5SDimitry Andric // Transaction Begin 20250b57cec5SDimitry Andric let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 20260b57cec5SDimitry Andric def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 20270b57cec5SDimitry Andric let hasNoSchedulingInfo = 1 in 20280b57cec5SDimitry Andric def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 20290b57cec5SDimitry Andric def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 20300b57cec5SDimitry Andric int_s390_tbeginc, imm32zx16>; 20310b57cec5SDimitry Andric } 20320b57cec5SDimitry Andric 20330b57cec5SDimitry Andric // Transaction End 20340b57cec5SDimitry Andric let Defs = [CC] in 20350b57cec5SDimitry Andric def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 20360b57cec5SDimitry Andric 20370b57cec5SDimitry Andric // Transaction Abort 20380b57cec5SDimitry Andric let isTerminator = 1, isBarrier = 1, mayStore = 1, 20390b57cec5SDimitry Andric hasSideEffects = 1 in 20400b57cec5SDimitry Andric def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 20410b57cec5SDimitry Andric 20420b57cec5SDimitry Andric // Nontransactional Store 20430b57cec5SDimitry Andric def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 20440b57cec5SDimitry Andric 20450b57cec5SDimitry Andric // Extract Transaction Nesting Depth 20460b57cec5SDimitry Andric def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 20470b57cec5SDimitry Andric} 20480b57cec5SDimitry Andric 20490b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20500b57cec5SDimitry Andric// Processor assist 20510b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20520b57cec5SDimitry Andric 20530b57cec5SDimitry Andriclet Predicates = [FeatureProcessorAssist] in { 20540b57cec5SDimitry Andric let hasSideEffects = 1 in 20550b57cec5SDimitry Andric def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 20560b57cec5SDimitry Andric def : Pat<(int_s390_ppa_txassist GR32:$src), 20570b57cec5SDimitry Andric (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2058480093f4SDimitry Andric zero_reg, 1)>; 20590b57cec5SDimitry Andric} 20600b57cec5SDimitry Andric 20610b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20620b57cec5SDimitry Andric// Miscellaneous Instructions. 20630b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20640b57cec5SDimitry Andric 20650b57cec5SDimitry Andric// Find leftmost one, AKA count leading zeros. The instruction actually 20660b57cec5SDimitry Andric// returns a pair of GR64s, the first giving the number of leading zeros 20670b57cec5SDimitry Andric// and the second giving a copy of the source with the leftmost one bit 20680b57cec5SDimitry Andric// cleared. We only use the first result here. 20690b57cec5SDimitry Andriclet Defs = [CC] in 20700b57cec5SDimitry Andric def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 20718bcb0991SDimitry Andricdef : Pat<(i64 (ctlz GR64:$src)), 20720b57cec5SDimitry Andric (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 20730b57cec5SDimitry Andric 20740b57cec5SDimitry Andric// Population count. Counts bits set per byte or doubleword. 20750b57cec5SDimitry Andriclet Predicates = [FeatureMiscellaneousExtensions3] in { 20760b57cec5SDimitry Andric let Defs = [CC] in 20770b57cec5SDimitry Andric def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 20780b57cec5SDimitry Andric def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 20790b57cec5SDimitry Andric} 20800b57cec5SDimitry Andriclet Predicates = [FeaturePopulationCount], Defs = [CC] in 20810b57cec5SDimitry Andric def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 20820b57cec5SDimitry Andric 20830b57cec5SDimitry Andric// Search a block of memory for a character. 20840b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC] in 20850b57cec5SDimitry Andric defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 20860b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC], Uses = [R0L] in 20870b57cec5SDimitry Andric def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 20880b57cec5SDimitry Andric 20890b57cec5SDimitry Andric// Compare until substring equal. 20900b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 20910b57cec5SDimitry Andric def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 20920b57cec5SDimitry Andric 20930b57cec5SDimitry Andric// Compare and form codeword. 20940b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 20950b57cec5SDimitry Andric def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 20960b57cec5SDimitry Andric 20970b57cec5SDimitry Andric// Update tree. 20980b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 20990b57cec5SDimitry Andric Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 21000b57cec5SDimitry Andric def UPT : SideEffectInherentE<"upt", 0x0102>; 21010b57cec5SDimitry Andric 21020b57cec5SDimitry Andric// Checksum. 21030b57cec5SDimitry Andriclet mayLoad = 1, Defs = [CC] in 21040b57cec5SDimitry Andric def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 21050b57cec5SDimitry Andric 21060b57cec5SDimitry Andric// Compression call. 21070b57cec5SDimitry Andriclet mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 21080b57cec5SDimitry Andric def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 21090b57cec5SDimitry Andric 21100b57cec5SDimitry Andric// Sort lists. 21110b57cec5SDimitry Andriclet Predicates = [FeatureEnhancedSort], 21120b57cec5SDimitry Andric mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 21130b57cec5SDimitry Andric def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 21140b57cec5SDimitry Andric 21150b57cec5SDimitry Andric// Deflate conversion call. 21160b57cec5SDimitry Andriclet Predicates = [FeatureDeflateConversion], 21170b57cec5SDimitry Andric mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 21180b57cec5SDimitry Andric def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 21190b57cec5SDimitry Andric GR128, GR128, GR64>; 21200b57cec5SDimitry Andric 2121fe6060f1SDimitry Andric// NNPA. 2122fe6060f1SDimitry Andriclet Predicates = [FeatureNNPAssist], 2123fe6060f1SDimitry Andric mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2124fe6060f1SDimitry Andric def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2125fe6060f1SDimitry Andric 21260b57cec5SDimitry Andric// Execute. 21270b57cec5SDimitry Andriclet hasSideEffects = 1 in { 2128fe6060f1SDimitry Andric def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2129fe6060f1SDimitry Andric def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2130fe6060f1SDimitry Andric let hasNoSchedulingInfo = 1 in 2131349cc55cSDimitry Andric def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2132fe6060f1SDimitry Andric bdaddr12only:$bdl1, bdaddr12only:$bd2), 2133fe6060f1SDimitry Andric []>; 21340b57cec5SDimitry Andric} 21350b57cec5SDimitry Andric 21360b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 21370b57cec5SDimitry Andric// .insn directive instructions 21380b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 21390b57cec5SDimitry Andric 21400b57cec5SDimitry Andriclet isCodeGenOnly = 1, hasSideEffects = 1 in { 21410b57cec5SDimitry Andric def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 21420b57cec5SDimitry Andric def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 21430b57cec5SDimitry Andric imm32sx16:$I2), 21440b57cec5SDimitry Andric ".insn ri,$enc,$R1,$I2", []>; 21450b57cec5SDimitry Andric def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 21460b57cec5SDimitry Andric AnyReg:$R3, brtarget16:$I2), 21470b57cec5SDimitry Andric ".insn rie,$enc,$R1,$R3,$I2", []>; 21480b57cec5SDimitry Andric def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 21490b57cec5SDimitry Andric brtarget32:$I2), 21500b57cec5SDimitry Andric ".insn ril,$enc,$R1,$I2", []>; 21510b57cec5SDimitry Andric def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 21520b57cec5SDimitry Andric uimm32:$I2), 21530b57cec5SDimitry Andric ".insn rilu,$enc,$R1,$I2", []>; 21540b57cec5SDimitry Andric def InsnRIS : DirectiveInsnRIS<(outs), 21550b57cec5SDimitry Andric (ins imm64zx48:$enc, AnyReg:$R1, 21560b57cec5SDimitry Andric imm32sx8:$I2, imm32zx4:$M3, 215706c3fb27SDimitry Andric (bdaddr12only $B4, $D4):$BD4), 21580b57cec5SDimitry Andric ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 21590b57cec5SDimitry Andric def InsnRR : DirectiveInsnRR<(outs), 21600b57cec5SDimitry Andric (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 21610b57cec5SDimitry Andric ".insn rr,$enc,$R1,$R2", []>; 21620b57cec5SDimitry Andric def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 21630b57cec5SDimitry Andric AnyReg:$R1, AnyReg:$R2), 21640b57cec5SDimitry Andric ".insn rre,$enc,$R1,$R2", []>; 21650b57cec5SDimitry Andric def InsnRRF : DirectiveInsnRRF<(outs), 21660b57cec5SDimitry Andric (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 21670b57cec5SDimitry Andric AnyReg:$R3, imm32zx4:$M4), 21680b57cec5SDimitry Andric ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 21690b57cec5SDimitry Andric def InsnRRS : DirectiveInsnRRS<(outs), 21700b57cec5SDimitry Andric (ins imm64zx48:$enc, AnyReg:$R1, 21710b57cec5SDimitry Andric AnyReg:$R2, imm32zx4:$M3, 217206c3fb27SDimitry Andric (bdaddr12only $B4, $D4):$BD4), 21730b57cec5SDimitry Andric ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 21740b57cec5SDimitry Andric def InsnRS : DirectiveInsnRS<(outs), 21750b57cec5SDimitry Andric (ins imm64zx32:$enc, AnyReg:$R1, 217606c3fb27SDimitry Andric AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 21770b57cec5SDimitry Andric ".insn rs,$enc,$R1,$R3,$BD2", []>; 21780b57cec5SDimitry Andric def InsnRSE : DirectiveInsnRSE<(outs), 21790b57cec5SDimitry Andric (ins imm64zx48:$enc, AnyReg:$R1, 218006c3fb27SDimitry Andric AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 21810b57cec5SDimitry Andric ".insn rse,$enc,$R1,$R3,$BD2", []>; 21820b57cec5SDimitry Andric def InsnRSI : DirectiveInsnRSI<(outs), 21830b57cec5SDimitry Andric (ins imm64zx48:$enc, AnyReg:$R1, 21840b57cec5SDimitry Andric AnyReg:$R3, brtarget16:$RI2), 21850b57cec5SDimitry Andric ".insn rsi,$enc,$R1,$R3,$RI2", []>; 21860b57cec5SDimitry Andric def InsnRSY : DirectiveInsnRSY<(outs), 21870b57cec5SDimitry Andric (ins imm64zx48:$enc, AnyReg:$R1, 218806c3fb27SDimitry Andric AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2), 21890b57cec5SDimitry Andric ".insn rsy,$enc,$R1,$R3,$BD2", []>; 21900b57cec5SDimitry Andric def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 219106c3fb27SDimitry Andric (bdxaddr12only $B2, $D2, $X2):$XBD2), 21920b57cec5SDimitry Andric ".insn rx,$enc,$R1,$XBD2", []>; 21930b57cec5SDimitry Andric def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 219406c3fb27SDimitry Andric (bdxaddr12only $B2, $D2, $X2):$XBD2), 21950b57cec5SDimitry Andric ".insn rxe,$enc,$R1,$XBD2", []>; 21960b57cec5SDimitry Andric def InsnRXF : DirectiveInsnRXF<(outs), 21970b57cec5SDimitry Andric (ins imm64zx48:$enc, AnyReg:$R1, 219806c3fb27SDimitry Andric AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 21990b57cec5SDimitry Andric ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 22000b57cec5SDimitry Andric def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 220106c3fb27SDimitry Andric (bdxaddr20only $B2, $D2, $X2):$XBD2), 22020b57cec5SDimitry Andric ".insn rxy,$enc,$R1,$XBD2", []>; 22030b57cec5SDimitry Andric def InsnS : DirectiveInsnS<(outs), 220406c3fb27SDimitry Andric (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2), 22050b57cec5SDimitry Andric ".insn s,$enc,$BD2", []>; 22060b57cec5SDimitry Andric def InsnSI : DirectiveInsnSI<(outs), 220706c3fb27SDimitry Andric (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, 22080b57cec5SDimitry Andric imm32sx8:$I2), 22090b57cec5SDimitry Andric ".insn si,$enc,$BD1,$I2", []>; 22100b57cec5SDimitry Andric def InsnSIY : DirectiveInsnSIY<(outs), 22110b57cec5SDimitry Andric (ins imm64zx48:$enc, 221206c3fb27SDimitry Andric (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2), 22130b57cec5SDimitry Andric ".insn siy,$enc,$BD1,$I2", []>; 22140b57cec5SDimitry Andric def InsnSIL : DirectiveInsnSIL<(outs), 221506c3fb27SDimitry Andric (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 22160b57cec5SDimitry Andric imm32zx16:$I2), 22170b57cec5SDimitry Andric ".insn sil,$enc,$BD1,$I2", []>; 22180b57cec5SDimitry Andric def InsnSS : DirectiveInsnSS<(outs), 221906c3fb27SDimitry Andric (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1, 222006c3fb27SDimitry Andric (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 22210b57cec5SDimitry Andric ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 22220b57cec5SDimitry Andric def InsnSSE : DirectiveInsnSSE<(outs), 22230b57cec5SDimitry Andric (ins imm64zx48:$enc, 222406c3fb27SDimitry Andric (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2), 22250b57cec5SDimitry Andric ".insn sse,$enc,$BD1,$BD2", []>; 22260b57cec5SDimitry Andric def InsnSSF : DirectiveInsnSSF<(outs), 222706c3fb27SDimitry Andric (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 222806c3fb27SDimitry Andric (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 22290b57cec5SDimitry Andric ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2230e8d8bef9SDimitry Andric def InsnVRI : DirectiveInsnVRI<(outs), 2231e8d8bef9SDimitry Andric (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2232e8d8bef9SDimitry Andric imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2233e8d8bef9SDimitry Andric ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2234e8d8bef9SDimitry Andric def InsnVRR : DirectiveInsnVRR<(outs), 2235e8d8bef9SDimitry Andric (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2236e8d8bef9SDimitry Andric VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2237e8d8bef9SDimitry Andric imm32zx4:$M6), 2238e8d8bef9SDimitry Andric ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2239e8d8bef9SDimitry Andric def InsnVRS : DirectiveInsnVRS<(outs), 2240e8d8bef9SDimitry Andric (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 224106c3fb27SDimitry Andric (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4), 2242e8d8bef9SDimitry Andric ".insn vrs,$enc,$BD2,$M4", []>; 2243e8d8bef9SDimitry Andric def InsnVRV : DirectiveInsnVRV<(outs), 2244e8d8bef9SDimitry Andric (ins imm64zx48:$enc, VR128:$V1, 224506c3fb27SDimitry Andric (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3), 2246e8d8bef9SDimitry Andric ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2247e8d8bef9SDimitry Andric def InsnVRX : DirectiveInsnVRX<(outs), 2248e8d8bef9SDimitry Andric (ins imm64zx48:$enc, VR128:$V1, 224906c3fb27SDimitry Andric (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 2250e8d8bef9SDimitry Andric ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2251e8d8bef9SDimitry Andric def InsnVSI : DirectiveInsnVSI<(outs), 2252e8d8bef9SDimitry Andric (ins imm64zx48:$enc, VR128:$V1, 225306c3fb27SDimitry Andric (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 2254e8d8bef9SDimitry Andric ".insn vsi,$enc,$V1,$BD2,$I3", []>; 22550b57cec5SDimitry Andric} 22560b57cec5SDimitry Andric 22570b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 22580b57cec5SDimitry Andric// Peepholes. 22590b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 22600b57cec5SDimitry Andric 22610b57cec5SDimitry Andric// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 22620b57cec5SDimitry Andric// equivalent to (and (xor x, -1), y) 22630b57cec5SDimitry Andricdef : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 22640b57cec5SDimitry Andric (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 22650b57cec5SDimitry Andric 22665f757f3fSDimitry Andric// Use LCGR/AGHI for i64 xor with -1. 22675f757f3fSDimitry Andricdef : Pat<(xor GR64:$x, (i64 -1)), 22685f757f3fSDimitry Andric (AGHI (LCGR GR64:$x), (i64 -1))>; 22695f757f3fSDimitry Andric 22700b57cec5SDimitry Andric// Shift/rotate instructions only use the last 6 bits of the second operand 22710b57cec5SDimitry Andric// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 22720b57cec5SDimitry Andric// last 16 bits. 22730b57cec5SDimitry Andric// Complexity is added so that we match this before we match NILF on the AND 22740b57cec5SDimitry Andric// operation alone. 22750b57cec5SDimitry Andriclet AddedComplexity = 4 in { 22760b57cec5SDimitry Andric def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22770b57cec5SDimitry Andric (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22780b57cec5SDimitry Andric 22790b57cec5SDimitry Andric def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22800b57cec5SDimitry Andric (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22810b57cec5SDimitry Andric 22820b57cec5SDimitry Andric def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22830b57cec5SDimitry Andric (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22840b57cec5SDimitry Andric 22850b57cec5SDimitry Andric def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22860b57cec5SDimitry Andric (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22870b57cec5SDimitry Andric 22880b57cec5SDimitry Andric def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22890b57cec5SDimitry Andric (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22900b57cec5SDimitry Andric 22910b57cec5SDimitry Andric def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22920b57cec5SDimitry Andric (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22930b57cec5SDimitry Andric 22940b57cec5SDimitry Andric def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22950b57cec5SDimitry Andric (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22960b57cec5SDimitry Andric 22970b57cec5SDimitry Andric def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 22980b57cec5SDimitry Andric (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 22990b57cec5SDimitry Andric} 23000b57cec5SDimitry Andric 23010b57cec5SDimitry Andric// Substitute (x*64-s) with (-s), since shift/rotate instructions only 23020b57cec5SDimitry Andric// use the last 6 bits of the second operand register (making it modulo 64). 23030b57cec5SDimitry Andriclet AddedComplexity = 4 in { 23040b57cec5SDimitry Andric def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 23050b57cec5SDimitry Andric (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 23060b57cec5SDimitry Andric 23070b57cec5SDimitry Andric def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 23080b57cec5SDimitry Andric (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 23090b57cec5SDimitry Andric 23100b57cec5SDimitry Andric def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 23110b57cec5SDimitry Andric (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 23120b57cec5SDimitry Andric 23130b57cec5SDimitry Andric def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 23140b57cec5SDimitry Andric (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 23150b57cec5SDimitry Andric} 23160b57cec5SDimitry Andric 2317349cc55cSDimitry Andric// Peepholes for turning scalar operations into block operations. The length 2318349cc55cSDimitry Andric// is given as one less for these pseudos. 2319349cc55cSDimitry Andricdefm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>; 2320349cc55cSDimitry Andricdefm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>; 2321349cc55cSDimitry Andricdefm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>; 2322349cc55cSDimitry Andricdefm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>; 2323349cc55cSDimitry Andricdefm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>; 2324349cc55cSDimitry Andricdefm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>; 2325349cc55cSDimitry Andricdefm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>; 2326e8d8bef9SDimitry Andric 2327e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 2328e8d8bef9SDimitry Andric// Mnemonic Aliases 2329e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 2330e8d8bef9SDimitry Andric 2331e8d8bef9SDimitry Andricdef JCT : MnemonicAlias<"jct", "brct">; 2332e8d8bef9SDimitry Andricdef JCTG : MnemonicAlias<"jctg", "brctg">; 2333e8d8bef9SDimitry Andricdef JAS : MnemonicAlias<"jas", "bras">; 2334e8d8bef9SDimitry Andricdef JASL : MnemonicAlias<"jasl", "brasl">; 2335e8d8bef9SDimitry Andricdef JXH : MnemonicAlias<"jxh", "brxh">; 2336e8d8bef9SDimitry Andricdef JXLE : MnemonicAlias<"jxle", "brxle">; 2337e8d8bef9SDimitry Andricdef JXHG : MnemonicAlias<"jxhg", "brxhg">; 2338e8d8bef9SDimitry Andricdef JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2339e8d8bef9SDimitry Andric 2340e8d8bef9SDimitry Andricdef BRU : MnemonicAlias<"bru", "j">; 2341fe6060f1SDimitry Andricdef BRUL : MnemonicAlias<"brul", "jg", "att">; 2342fe6060f1SDimitry Andricdef BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2343e8d8bef9SDimitry Andric 2344e8d8bef9SDimitry Andricforeach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2345e8d8bef9SDimitry Andric "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2346fe6060f1SDimitry Andric defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2347fe6060f1SDimitry Andric defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; 2348fe6060f1SDimitry Andric defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2349e8d8bef9SDimitry Andric} 2350