1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// The callseq_start node requires the hasSideEffects flag, even though these 17// instructions are noops on SystemZ. 18let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45let Defs = [R3D, CC], Uses = [R3D, R4D], hasNoSchedulingInfo = 1, 46 hasSideEffects = 1 in 47 def XPLINK_STACKALLOC : Pseudo<(outs), (ins), []>; 48 49//===----------------------------------------------------------------------===// 50// Branch instructions 51//===----------------------------------------------------------------------===// 52 53// Conditional branches. 54let isBranch = 1, isTerminator = 1, Uses = [CC] in { 55 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 56 // with the condition-code mask being the first operand. It seems friendlier 57 // to use mnemonic forms like JE and JLH when writing out the assembly though. 58 let isCodeGenOnly = 1 in { 59 // An assembler extended mnemonic for BRC. 60 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 61 // An assembler extended mnemonic for BRCL. (The extension is "G" 62 // rather than "L" because "JL" is "Jump if Less".) 63 def BRCL : CondBranchRIL<"jg#", 0xC04>; 64 let isIndirectBranch = 1 in { 65 def BC : CondBranchRX<"b#", 0x47>; 66 def BCR : CondBranchRR<"b#r", 0x07>; 67 def BIC : CondBranchRXY<"bi#", 0xe347>, 68 Requires<[FeatureMiscellaneousExtensions2]>; 69 } 70 } 71 72 // Allow using the raw forms directly from the assembler (and occasional 73 // special code generation needs) as well. 74 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 75 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 76 let isIndirectBranch = 1 in { 77 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 78 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 79 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 80 Requires<[FeatureMiscellaneousExtensions2]>; 81 } 82 83 // Define AsmParser extended mnemonics for each general condition-code mask 84 // (integer or floating-point) 85 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 86 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 87 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 88 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 89 let isIndirectBranch = 1 in { 90 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 91 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 92 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 93 Requires<[FeatureMiscellaneousExtensions2]>; 94 } 95 } 96} 97 98// Unconditional branches. These are in fact simply variants of the 99// conditional branches with the condition mask set to "always". 100let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 101 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 102 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 103 let isIndirectBranch = 1 in { 104 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 105 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 106 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 107 Requires<[FeatureMiscellaneousExtensions2]>; 108 } 109} 110 111// NOPs. These are again variants of the conditional branches, with the 112// condition mask set to "never". NOP_bare can't be an InstAlias since it 113// would need R0D hard coded which is not part of ADDR64BitRegClass. 114def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 115let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in 116 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 117def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 118def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 119 120// An alias of BRC 0, label 121def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 122 123// An alias of BRCL 0, label 124// jgnop on att ; jlnop on hlasm 125def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 126 127// Fused compare-and-branch instructions. 128// 129// These instructions do not use or clobber the condition codes. 130// We nevertheless pretend that the relative compare-and-branch 131// instructions clobber CC, so that we can lower them to separate 132// comparisons and BRCLs if the branch ends up being out of range. 133let isBranch = 1, isTerminator = 1 in { 134 // As for normal branches, we handle these instructions internally in 135 // their raw CRJ-like form, but use assembly macros like CRJE when writing 136 // them out. Using the *Pair multiclasses, we also create the raw forms. 137 let Defs = [CC] in { 138 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 139 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 140 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 141 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 142 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 143 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 144 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 145 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 146 } 147 let isIndirectBranch = 1 in { 148 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 149 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 150 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 151 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 152 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 153 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 154 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 155 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 156 } 157 158 // Define AsmParser mnemonics for each integer condition-code mask. 159 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 160 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 161 let Defs = [CC] in { 162 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 163 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 164 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 165 imm32sx8>; 166 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 167 imm64sx8>; 168 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 169 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 170 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 171 imm32zx8>; 172 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 173 imm64zx8>; 174 } 175 let isIndirectBranch = 1 in { 176 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 177 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 178 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 179 imm32sx8>; 180 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 181 imm64sx8>; 182 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 183 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 184 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 185 imm32zx8>; 186 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 187 imm64zx8>; 188 } 189 } 190} 191 192// Decrement a register and branch if it is nonzero. These don't clobber CC, 193// but we might need to split long relative branches into sequences that do. 194let isBranch = 1, isTerminator = 1 in { 195 let Defs = [CC] in { 196 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 197 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 198 } 199 // This doesn't need to clobber CC since we never need to split it. 200 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 201 Requires<[FeatureHighWord]>; 202 203 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 204 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 205 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 206 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 207} 208 209let isBranch = 1, isTerminator = 1 in { 210 let Defs = [CC] in { 211 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 212 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 213 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 214 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 215 } 216 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 217 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 218 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 219 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 220} 221 222//===----------------------------------------------------------------------===// 223// Trap instructions 224//===----------------------------------------------------------------------===// 225 226// Unconditional trap. 227let hasCtrlDep = 1, hasSideEffects = 1 in 228 def Trap : Alias<4, (outs), (ins), [(trap)]>; 229 230// Conditional trap. 231let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 232 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 233 234// Fused compare-and-trap instructions. 235let hasCtrlDep = 1, hasSideEffects = 1 in { 236 // These patterns work the same way as for compare-and-branch. 237 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 238 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 239 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 240 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 241 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 242 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 243 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 244 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 245 let Predicates = [FeatureMiscellaneousExtensions] in { 246 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 247 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 248 } 249 250 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 251 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 252 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 253 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 254 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 255 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 256 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 257 imm32sx16>; 258 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 259 imm64sx16>; 260 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 261 imm32zx16>; 262 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 263 imm64zx16>; 264 let Predicates = [FeatureMiscellaneousExtensions] in { 265 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 266 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 267 } 268 } 269} 270 271//===----------------------------------------------------------------------===// 272// Call and return instructions 273//===----------------------------------------------------------------------===// 274 275// Define the general form of the call instructions for the asm parser. 276// These instructions don't hard-code %r14 as the return address register. 277let isCall = 1, Defs = [CC] in { 278 def BRAS : CallRI <"bras", 0xA75>; 279 def BRASL : CallRIL<"brasl", 0xC05>; 280 def BAS : CallRX <"bas", 0x4D>; 281 def BASR : CallRR <"basr", 0x0D>; 282} 283 284// A symbol in the ADA (z/OS only). 285def adasym : Operand<i64>; 286 287// z/OS XPLINK 288let Predicates = [IsTargetXPLINK64] in { 289 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 290 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 291 [(z_call pcrel32:$I2)]>; 292 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 293 [(z_call ADDR64:$R2)]>; 294 } 295 296 let isCall = 1, Defs = [R3D, CC], Uses = [FPC] in { 297 def CallBASR_STACKEXT : Alias<4, (outs), (ins ADDR64:$R2), []>; 298 } 299 300 let hasNoSchedulingInfo = 1, Defs = [CC] in { 301 def ADA_ENTRY : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, 302 ADDR64:$ADA, imm64:$Offset), 303 [(set i64:$Reg, (z_ada_entry i64:$addr, 304 i64:$ADA, i64:$Offset))]>; 305 } 306 let mayLoad = 1, AddedComplexity = 20, hasNoSchedulingInfo = 1, Defs = [CC] in { 307 def ADA_ENTRY_VALUE : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, 308 ADDR64:$ADA, imm64:$Offset), 309 [(set i64:$Reg, (load (z_ada_entry 310 iPTR:$addr, iPTR:$ADA, i64:$Offset)))]>; 311 } 312} 313 314// Regular calls. 315// z/Linux ELF 316let Predicates = [IsTargetELF] in { 317 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 318 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 319 [(z_call pcrel32:$I2)]>; 320 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 321 [(z_call ADDR64:$R2)]>; 322 } 323 324 // TLS calls. These will be lowered into a call to __tls_get_offset, 325 // with an extra relocation specifying the TLS symbol. 326 let isCall = 1, Defs = [R14D, CC] in { 327 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 328 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 329 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 330 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 331 } 332} 333 334// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 335// R1 used for ELF 336let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 337 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 338 [(z_sibcall pcrel32:$I2)]>; 339 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 340 [(z_sibcall ADDR64:$R2)]>; 341} 342 343// Conditional sibling calls. 344let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 345 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 346 pcrel32:$I2), []>; 347 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 348 ADDR64:$R2), []>; 349} 350 351// Fused compare and conditional sibling calls. 352let isCall = 1, isTerminator = 1, isReturn = 1 in { 353 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 354 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 355 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 356 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 357 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 358 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 359 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 360 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 361} 362 363let Predicates = [IsTargetXPLINK64] in { 364 // A return instruction (b 2(%r7)). 365 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 366 def Return_XPLINK : Alias<4, (outs), (ins), [(z_retglue)]>; 367 368 // A conditional return instruction (bc <cond>, 2(%r7)). 369 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 370 def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 371} 372 373let Predicates = [IsTargetELF] in { 374 // A return instruction (br %r14). 375 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 376 def Return : Alias<2, (outs), (ins), [(z_retglue)]>; 377 378 // A conditional return instruction (bcr <cond>, %r14). 379 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 380 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 381} 382 383// Fused compare and conditional returns. 384let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 385 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 386 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 387 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 388 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 389 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 390 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 391 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 392 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 393} 394 395//===----------------------------------------------------------------------===// 396// Select instructions 397//===----------------------------------------------------------------------===// 398 399def Select32 : SelectWrapper<i32, GR32>, 400 Requires<[FeatureNoLoadStoreOnCond]>; 401def Select64 : SelectWrapper<i64, GR64>, 402 Requires<[FeatureNoLoadStoreOnCond]>; 403 404// We don't define 32-bit Mux stores if we don't have STOCFH, because the 405// low-only STOC should then always be used if possible. 406defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 407 nonvolatile_anyextloadi8, bdxaddr20only>, 408 Requires<[FeatureHighWord]>; 409defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 410 nonvolatile_anyextloadi16, bdxaddr20only>, 411 Requires<[FeatureHighWord]>; 412defm CondStore32Mux : CondStores<GRX32, simple_store, 413 simple_load, bdxaddr20only>, 414 Requires<[FeatureLoadStoreOnCond2]>; 415defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 416 nonvolatile_anyextloadi8, bdxaddr20only>; 417defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 418 nonvolatile_anyextloadi16, bdxaddr20only>; 419defm CondStore32 : CondStores<GR32, simple_store, 420 simple_load, bdxaddr20only>; 421 422defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 423 nonvolatile_anyextloadi8, bdxaddr20only>; 424defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 425 nonvolatile_anyextloadi16, bdxaddr20only>; 426defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 427 nonvolatile_anyextloadi32, bdxaddr20only>; 428defm CondStore64 : CondStores<GR64, simple_store, 429 simple_load, bdxaddr20only>; 430 431//===----------------------------------------------------------------------===// 432// Move instructions 433//===----------------------------------------------------------------------===// 434 435// Register moves. 436def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 437def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 438 439let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 440 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 441 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 442} 443 444let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 445 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 446 447// Immediate moves. 448let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 449 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 450 // deopending on the choice of register. 451 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 452 Requires<[FeatureHighWord]>; 453 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 454 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 455 456 // Other 16-bit immediates. 457 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 458 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 459 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 460 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 461 462 // 32-bit immediates. 463 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 464 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 465 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 466} 467 468// Register loads. 469let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 470 // Expands to L, LY or LFH, depending on the choice of register. 471 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 472 Requires<[FeatureHighWord]>; 473 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 474 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 475 Requires<[FeatureHighWord]>; 476 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 477 478 // These instructions are split after register allocation, so we don't 479 // want a custom inserter. 480 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 481 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 482 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 483 } 484} 485let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 486 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 487 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 488} 489 490let canFoldAsLoad = 1 in { 491 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 492 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 493} 494 495// Load and zero rightmost byte. 496let Predicates = [FeatureLoadAndZeroRightmostByte] in { 497 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 498 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 499 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 500 (LZRF bdxaddr20only:$src)>; 501 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 502 (LZRG bdxaddr20only:$src)>; 503} 504 505// Load and trap. 506let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 507 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 508 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 509 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 510} 511 512// Register stores. 513let SimpleBDXStore = 1, mayStore = 1 in { 514 // Expands to ST, STY or STFH, depending on the choice of register. 515 def STMux : StoreRXYPseudo<store, GRX32, 4>, 516 Requires<[FeatureHighWord]>; 517 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 518 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 519 Requires<[FeatureHighWord]>; 520 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 521 522 // These instructions are split after register allocation, so we don't 523 // want a custom inserter. 524 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 525 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 526 [(store GR128:$src, bdxaddr20only128:$dst)]>; 527 } 528} 529def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 530def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 531 532// 8-bit immediate stores to 8-bit fields. 533defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 534 535// 16-bit immediate stores to 16-, 32- or 64-bit fields. 536def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 537def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 538def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 539 540// Memory-to-memory moves. 541let mayLoad = 1, mayStore = 1 in 542 defm MVC : MemorySS<"mvc", 0xD2, z_mvc>; 543let mayLoad = 1, mayStore = 1, Defs = [CC] in { 544 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 545 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 546 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 547} 548 549// Memset[Length][Byte] pseudos. 550def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>; 551def MemsetImmReg : MemsetPseudo<imm64, GR32>; 552def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>; 553def MemsetRegReg : MemsetPseudo<ADDR64, GR32>; 554 555// Move right. 556let Predicates = [FeatureMiscellaneousExtensions3], 557 mayLoad = 1, mayStore = 1, Uses = [R0L] in 558 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 559 560// String moves. 561let mayLoad = 1, mayStore = 1, Defs = [CC] in 562 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 563 564//===----------------------------------------------------------------------===// 565// Conditional move instructions 566//===----------------------------------------------------------------------===// 567 568let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 569 // Select. 570 let isCommutable = 1 in { 571 // Expands to SELR or SELFHR or a branch-and-move sequence, 572 // depending on the choice of registers. 573 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 574 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 575 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 576 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 577 } 578 579 // Define AsmParser extended mnemonics for each general condition-code mask. 580 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 581 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 582 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 583 GR32, GR32, GR32>; 584 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 585 GRH32, GRH32, GRH32>; 586 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 587 GR64, GR64, GR64>; 588 } 589} 590 591let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 592 // Load immediate on condition. Matched via DAG pattern and created 593 // by the PeepholeOptimizer via FoldImmediate. 594 595 // Expands to LOCHI or LOCHHI, depending on the choice of register. 596 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 597 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 598 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 599 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 600 601 // Move register on condition. Matched via DAG pattern and 602 // created by early if-conversion. 603 let isCommutable = 1 in { 604 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 605 // depending on the choice of registers. 606 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 607 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 608 } 609 610 // Load on condition. Matched via DAG pattern. 611 // Expands to LOC or LOCFH, depending on the choice of register. 612 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 613 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 614 615 // Store on condition. Expanded from CondStore* pseudos. 616 // Expands to STOC or STOCFH, depending on the choice of register. 617 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 618 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 619 620 // Define AsmParser extended mnemonics for each general condition-code mask. 621 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 622 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 623 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 624 imm32sx16>; 625 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 626 imm64sx16>; 627 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 628 imm32sx16>; 629 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 630 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 631 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 632 } 633} 634 635let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 636 // Move register on condition. Matched via DAG pattern and 637 // created by early if-conversion. 638 let isCommutable = 1 in { 639 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 640 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 641 } 642 643 // Load on condition. Matched via DAG pattern. 644 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 645 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 646 647 // Store on condition. Expanded from CondStore* pseudos. 648 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 649 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 650 651 // Define AsmParser extended mnemonics for each general condition-code mask. 652 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 653 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 654 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 655 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 656 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 657 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 658 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 659 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 660 } 661} 662//===----------------------------------------------------------------------===// 663// Sign extensions 664//===----------------------------------------------------------------------===// 665// 666// Note that putting these before zero extensions mean that we will prefer 667// them for anyextload*. There's not really much to choose between the two 668// either way, but signed-extending loads have a short LH and a long LHY, 669// while zero-extending loads have only the long LLH. 670// 671//===----------------------------------------------------------------------===// 672 673// 32-bit extensions from registers. 674def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 675def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 676 677// 64-bit extensions from registers. 678def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 679def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 680def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 681 682let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 683 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 684 685// Match 32-to-64-bit sign extensions in which the source is already 686// in a 64-bit register. 687def : Pat<(sext_inreg GR64:$src, i32), 688 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 689 690// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 691// depending on the choice of register. 692def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 693 Requires<[FeatureHighWord]>; 694def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 695def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 696 Requires<[FeatureHighWord]>; 697 698// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 699// depending on the choice of register. 700def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 701 Requires<[FeatureHighWord]>; 702defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 703def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 704 Requires<[FeatureHighWord]>; 705def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 706 707// 64-bit extensions from memory. 708def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 709def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 710def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 711def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 712def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 713let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 714 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 715 716//===----------------------------------------------------------------------===// 717// Zero extensions 718//===----------------------------------------------------------------------===// 719 720// 32-bit extensions from registers. 721 722// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 723def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 724 Requires<[FeatureHighWord]>; 725def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 726// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 727def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 728 Requires<[FeatureHighWord]>; 729def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 730 731// 64-bit extensions from registers. 732def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 733def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 734def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 735 736// Match 32-to-64-bit zero extensions in which the source is already 737// in a 64-bit register. 738def : Pat<(and GR64:$src, 0xffffffff), 739 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 740 741// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 742// depending on the choice of register. 743def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 744 Requires<[FeatureHighWord]>; 745def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 746def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 747 Requires<[FeatureHighWord]>; 748 749// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 750// depending on the choice of register. 751def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 752 Requires<[FeatureHighWord]>; 753def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 754def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 755 Requires<[FeatureHighWord]>; 756def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 757 758// 64-bit extensions from memory. 759def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 760def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 761def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 762def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 763def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 764 765// 31-to-64-bit zero extensions. 766def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 767def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 768def : Pat<(and GR64:$src, 0x7fffffff), 769 (LLGTR GR64:$src)>; 770def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 771 (LLGT bdxaddr20only:$src)>; 772 773// Load and zero rightmost byte. 774let Predicates = [FeatureLoadAndZeroRightmostByte] in { 775 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 776 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 777 (LLZRGF bdxaddr20only:$src)>; 778} 779 780// Load and trap. 781let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 782 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 783 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 784} 785 786// Extend GR64s to GR128s. 787let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 788 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 789 790//===----------------------------------------------------------------------===// 791// "Any" extensions 792//===----------------------------------------------------------------------===// 793 794// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 795def : Pat<(i64 (anyext GR32:$src)), 796 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 797 798// Extend GR64s to GR128s. 799let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 800 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 801 802//===----------------------------------------------------------------------===// 803// Truncations 804//===----------------------------------------------------------------------===// 805 806// Truncations of 64-bit registers to 32-bit registers. 807def : Pat<(i32 (trunc GR64:$src)), 808 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 809 810// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 811// STC, STCY or STCH, depending on the choice of register. 812def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 813 Requires<[FeatureHighWord]>; 814defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 815def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 816 Requires<[FeatureHighWord]>; 817 818// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 819// STH, STHY or STHH, depending on the choice of register. 820def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 821 Requires<[FeatureHighWord]>; 822defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 823def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 824 Requires<[FeatureHighWord]>; 825def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 826 827// Truncations of 64-bit registers to memory. 828defm : StoreGR64Pair<STC, STCY, truncstorei8>; 829defm : StoreGR64Pair<STH, STHY, truncstorei16>; 830def : StoreGR64PC<STHRL, aligned_truncstorei16>; 831defm : StoreGR64Pair<ST, STY, truncstorei32>; 832def : StoreGR64PC<STRL, aligned_truncstorei32>; 833 834// Store characters under mask -- not (yet) used for codegen. 835defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 836def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 837 838//===----------------------------------------------------------------------===// 839// Multi-register moves 840//===----------------------------------------------------------------------===// 841 842// Multi-register loads. 843defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 844def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 845def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 846def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 847 848// Multi-register stores. 849defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 850def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 851def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 852 853//===----------------------------------------------------------------------===// 854// Byte swaps 855//===----------------------------------------------------------------------===// 856 857// Byte-swapping register moves. 858def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 859def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 860 861// Byte-swapping loads. 862def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 863def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 864def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 865 866// Byte-swapping stores. 867def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 868def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 869def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 870 871// Byte-swapping memory-to-memory moves. 872let mayLoad = 1, mayStore = 1 in 873 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 874 875//===----------------------------------------------------------------------===// 876// Load address instructions 877//===----------------------------------------------------------------------===// 878 879// Load BDX-style addresses. 880let isAsCheapAsAMove = 1, isReMaterializable = 1 in 881 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 882 883// Load a PC-relative address. There's no version of this instruction 884// with a 16-bit offset, so there's no relaxation. 885let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 886 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 887 888// Load the Global Offset Table address. This will be lowered into a 889// larl $R1, _GLOBAL_OFFSET_TABLE_ 890// instruction. 891def GOT : Alias<6, (outs GR64:$R1), (ins), 892 [(set GR64:$R1, (global_offset_table))]>; 893 894//===----------------------------------------------------------------------===// 895// Absolute and Negation 896//===----------------------------------------------------------------------===// 897 898let Defs = [CC] in { 899 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 900 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 901 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 902 } 903 let CCValues = 0xE, CompareZeroCCMask = 0xE in 904 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 905} 906defm : SXU<abs, LPGFR>; 907 908let Defs = [CC] in { 909 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 910 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 911 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 912 } 913 let CCValues = 0xE, CompareZeroCCMask = 0xE in 914 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 915} 916defm : SXU<z_inegabs, LNGFR>; 917 918let Defs = [CC] in { 919 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 920 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 921 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 922 } 923 let CCValues = 0xE, CompareZeroCCMask = 0xE in 924 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 925} 926defm : SXU<ineg, LCGFR>; 927 928//===----------------------------------------------------------------------===// 929// Insertion 930//===----------------------------------------------------------------------===// 931 932let isCodeGenOnly = 1 in 933 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 934defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 935 936defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 937defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 938 939defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 940defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 941 942// Insert characters under mask -- not (yet) used for codegen. 943let Defs = [CC] in { 944 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 945 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 946} 947 948// Insertions of a 16-bit immediate, leaving other bits unaffected. 949// We don't have or_as_insert equivalents of these operations because 950// OI is available instead. 951// 952// IIxMux expands to II[LH]x, depending on the choice of register. 953def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 954 Requires<[FeatureHighWord]>; 955def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 956 Requires<[FeatureHighWord]>; 957def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 958def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 959def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 960def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 961def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 962def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 963def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 964def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 965 966// ...likewise for 32-bit immediates. For GR32s this is a general 967// full-width move. (We use IILF rather than something like LLILF 968// for 32-bit moves because IILF leaves the upper 32 bits of the 969// GR64 unchanged.) 970let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 971 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 972 Requires<[FeatureHighWord]>; 973 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 974 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 975} 976def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 977def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 978 979// An alternative model of inserthf, with the first operand being 980// a zero-extended value. 981def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 982 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 983 imm64hf32:$imm)>; 984 985//===----------------------------------------------------------------------===// 986// Addition 987//===----------------------------------------------------------------------===// 988 989// Addition producing a signed overflow flag. 990let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 991 // Addition of a register. 992 let isCommutable = 1 in { 993 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 994 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 995 } 996 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 997 998 // Addition to a high register. 999 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 1000 Requires<[FeatureHighWord]>; 1001 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 1002 Requires<[FeatureHighWord]>; 1003 1004 // Addition of signed 16-bit immediates. 1005 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 1006 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 1007 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 1008 1009 // Addition of signed 32-bit immediates. 1010 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 1011 Requires<[FeatureHighWord]>; 1012 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 1013 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 1014 Requires<[FeatureHighWord]>; 1015 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 1016 1017 // Addition of memory. 1018 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 1019 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 1020 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 1021 Requires<[FeatureMiscellaneousExtensions2]>; 1022 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 1023 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 1024 1025 // Addition to memory. 1026 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 1027 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 1028} 1029defm : SXB<z_sadd, GR64, AGFR>; 1030 1031// Addition producing a carry. 1032let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 1033 // Addition of a register. 1034 let isCommutable = 1 in { 1035 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 1036 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 1037 } 1038 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 1039 1040 // Addition to a high register. 1041 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 1042 Requires<[FeatureHighWord]>; 1043 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1044 Requires<[FeatureHighWord]>; 1045 1046 // Addition of signed 16-bit immediates. 1047 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1048 Requires<[FeatureDistinctOps]>; 1049 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1050 Requires<[FeatureDistinctOps]>; 1051 1052 // Addition of unsigned 32-bit immediates. 1053 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1054 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1055 1056 // Addition of signed 32-bit immediates. 1057 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1058 Requires<[FeatureHighWord]>; 1059 1060 // Addition of memory. 1061 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1062 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1063 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1064 1065 // Addition to memory. 1066 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1067 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1068} 1069defm : ZXB<z_uadd, GR64, ALGFR>; 1070 1071// Addition producing and using a carry. 1072let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1073 // Addition of a register. 1074 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1075 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1076 1077 // Addition of memory. 1078 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1079 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1080} 1081 1082// Addition that does not modify the condition code. 1083def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1084 Requires<[FeatureHighWord]>; 1085 1086 1087//===----------------------------------------------------------------------===// 1088// Subtraction 1089//===----------------------------------------------------------------------===// 1090 1091// Subtraction producing a signed overflow flag. 1092let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1093 CCIfNoSignedWrap = 1 in { 1094 // Subtraction of a register. 1095 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1096 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1097 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1098 1099 // Subtraction from a high register. 1100 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1101 Requires<[FeatureHighWord]>; 1102 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1103 Requires<[FeatureHighWord]>; 1104 1105 // Subtraction of memory. 1106 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1107 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1108 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1109 Requires<[FeatureMiscellaneousExtensions2]>; 1110 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1111 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1112} 1113defm : SXB<z_ssub, GR64, SGFR>; 1114 1115// Subtracting an immediate is the same as adding the negated immediate. 1116let AddedComplexity = 1 in { 1117 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1118 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1119 Requires<[FeatureHighWord]>; 1120 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1121 (AFIMux GR32:$src1, simm32n:$src2)>, 1122 Requires<[FeatureHighWord]>; 1123 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1124 (AHI GR32:$src1, imm32sx16n:$src2)>; 1125 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1126 (AFI GR32:$src1, simm32n:$src2)>; 1127 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1128 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1129 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1130 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1131} 1132 1133// And vice versa in one special case, where we need to load a 1134// constant into a register in any case, but the negated constant 1135// requires fewer instructions to load. 1136def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1137 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1138def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1139 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1140 1141// Subtraction producing a carry. 1142let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1143 // Subtraction of a register. 1144 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1145 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1146 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1147 1148 // Subtraction from a high register. 1149 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1150 Requires<[FeatureHighWord]>; 1151 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1152 Requires<[FeatureHighWord]>; 1153 1154 // Subtraction of unsigned 32-bit immediates. 1155 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1156 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1157 1158 // Subtraction of memory. 1159 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1160 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1161 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1162} 1163defm : ZXB<z_usub, GR64, SLGFR>; 1164 1165// Subtracting an immediate is the same as adding the negated immediate. 1166let AddedComplexity = 1 in { 1167 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1168 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1169 Requires<[FeatureDistinctOps]>; 1170 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1171 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1172 Requires<[FeatureDistinctOps]>; 1173} 1174 1175// And vice versa in one special case (but we prefer addition). 1176def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1177 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1178 1179// Subtraction producing and using a carry. 1180let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1181 // Subtraction of a register. 1182 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1183 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1184 1185 // Subtraction of memory. 1186 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1187 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1188} 1189 1190 1191//===----------------------------------------------------------------------===// 1192// AND 1193//===----------------------------------------------------------------------===// 1194 1195let Defs = [CC] in { 1196 // ANDs of a register. 1197 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1198 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1199 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1200 } 1201 1202 let isConvertibleToThreeAddress = 1 in { 1203 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1204 // The CC result only reflects the 16-bit field, not the full register. 1205 // 1206 // NIxMux expands to NI[LH]x, depending on the choice of register. 1207 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1208 Requires<[FeatureHighWord]>; 1209 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1210 Requires<[FeatureHighWord]>; 1211 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1212 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1213 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1214 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1215 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1216 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1217 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1218 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1219 1220 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1221 // The CC result only reflects the 32-bit field, which means we can 1222 // use it as a zero indicator for i32 operations but not otherwise. 1223 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1224 // Expands to NILF or NIHF, depending on the choice of register. 1225 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1226 Requires<[FeatureHighWord]>; 1227 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1228 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1229 } 1230 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1231 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1232 } 1233 1234 // ANDs of memory. 1235 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1236 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1237 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1238 } 1239 1240 // AND to memory 1241 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1242 1243 // Block AND. 1244 let mayLoad = 1, mayStore = 1 in 1245 defm NC : MemorySS<"nc", 0xD4, z_nc>; 1246} 1247defm : RMWIByte<and, bdaddr12pair, NI>; 1248defm : RMWIByte<and, bdaddr20pair, NIY>; 1249 1250//===----------------------------------------------------------------------===// 1251// OR 1252//===----------------------------------------------------------------------===// 1253 1254let Defs = [CC] in { 1255 // ORs of a register. 1256 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1257 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1258 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1259 } 1260 1261 // ORs of a 16-bit immediate, leaving other bits unaffected. 1262 // The CC result only reflects the 16-bit field, not the full register. 1263 // 1264 // OIxMux expands to OI[LH]x, depending on the choice of register. 1265 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1266 Requires<[FeatureHighWord]>; 1267 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1268 Requires<[FeatureHighWord]>; 1269 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1270 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1271 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1272 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1273 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1274 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1275 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1276 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1277 1278 // ORs of a 32-bit immediate, leaving other bits unaffected. 1279 // The CC result only reflects the 32-bit field, which means we can 1280 // use it as a zero indicator for i32 operations but not otherwise. 1281 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1282 // Expands to OILF or OIHF, depending on the choice of register. 1283 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1284 Requires<[FeatureHighWord]>; 1285 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1286 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1287 } 1288 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1289 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1290 1291 // ORs of memory. 1292 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1293 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1294 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1295 } 1296 1297 // OR to memory 1298 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1299 1300 // Block OR. 1301 let mayLoad = 1, mayStore = 1 in 1302 defm OC : MemorySS<"oc", 0xD6, z_oc>; 1303} 1304defm : RMWIByte<or, bdaddr12pair, OI>; 1305defm : RMWIByte<or, bdaddr20pair, OIY>; 1306 1307//===----------------------------------------------------------------------===// 1308// XOR 1309//===----------------------------------------------------------------------===// 1310 1311let Defs = [CC] in { 1312 // XORs of a register. 1313 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1314 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1315 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1316 } 1317 1318 // XORs of a 32-bit immediate, leaving other bits unaffected. 1319 // The CC result only reflects the 32-bit field, which means we can 1320 // use it as a zero indicator for i32 operations but not otherwise. 1321 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1322 // Expands to XILF or XIHF, depending on the choice of register. 1323 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1324 Requires<[FeatureHighWord]>; 1325 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1326 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1327 } 1328 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1329 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1330 1331 // XORs of memory. 1332 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1333 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1334 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1335 } 1336 1337 // XOR to memory 1338 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1339 1340 // Block XOR. 1341 let mayLoad = 1, mayStore = 1 in 1342 defm XC : MemorySS<"xc", 0xD7, z_xc>; 1343} 1344defm : RMWIByte<xor, bdaddr12pair, XI>; 1345defm : RMWIByte<xor, bdaddr20pair, XIY>; 1346 1347//===----------------------------------------------------------------------===// 1348// Combined logical operations 1349//===----------------------------------------------------------------------===// 1350 1351let Predicates = [FeatureMiscellaneousExtensions3], 1352 Defs = [CC] in { 1353 // AND with complement. 1354 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1355 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1356 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1357 } 1358 1359 // OR with complement. 1360 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1361 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1362 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1363 } 1364 1365 // NAND. 1366 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1367 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1368 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1369 } 1370 1371 // NOR. 1372 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1373 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1374 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1375 } 1376 1377 // NXOR. 1378 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1379 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1380 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1381 } 1382} 1383 1384//===----------------------------------------------------------------------===// 1385// Multiplication 1386//===----------------------------------------------------------------------===// 1387 1388// Multiplication of a register, setting the condition code. We prefer these 1389// over MS(G)R if available, even though we cannot use the condition code, 1390// since they are three-operand instructions. 1391let Predicates = [FeatureMiscellaneousExtensions2], 1392 Defs = [CC], isCommutable = 1 in { 1393 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1394 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1395} 1396 1397// Multiplication of a register. 1398let isCommutable = 1 in { 1399 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1400 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1401} 1402def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1403defm : SXB<mul, GR64, MSGFR>; 1404 1405// Multiplication of a signed 16-bit immediate. 1406def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1407def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1408 1409// Multiplication of a signed 32-bit immediate. 1410def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1411def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1412 1413// Multiplication of memory. 1414defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1415defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1416def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1417 Requires<[FeatureMiscellaneousExtensions2]>; 1418def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1419def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1420 1421// Multiplication of memory, setting the condition code. 1422let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1423 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1424 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1425} 1426 1427// Multiplication of a register, producing two results. 1428def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1429def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1430 Requires<[FeatureMiscellaneousExtensions2]>; 1431def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1432def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1433 1434def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1435 (MGRK GR64:$src1, GR64:$src2)>; 1436def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1437 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1438 1439// Multiplication of memory, producing two results. 1440def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1441def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1442def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1443 Requires<[FeatureMiscellaneousExtensions2]>; 1444def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1445def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1446 1447def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1448 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1449def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1450 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1451 1452//===----------------------------------------------------------------------===// 1453// Division and remainder 1454//===----------------------------------------------------------------------===// 1455 1456let hasSideEffects = 1 in { // Do not speculatively execute. 1457 // Division and remainder, from registers. 1458 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1459 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1460 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1461 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1462 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1463 1464 // Division and remainder, from memory. 1465 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1466 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1467 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1468 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1469 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1470} 1471def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1472 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1473def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1474 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1475def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1476 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1477def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1478 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1479 1480def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1481 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1482 subreg_l32)), GR32:$src2)>; 1483def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1484 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1485 subreg_l32)), bdxaddr20only:$src2)>; 1486def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1487 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1488def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1489 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1490 1491//===----------------------------------------------------------------------===// 1492// Shifts 1493//===----------------------------------------------------------------------===// 1494 1495// Logical shift left. 1496defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1497def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1498def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1499 1500// Arithmetic shift left. 1501let Defs = [CC] in { 1502 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1503 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1504 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1505} 1506 1507// Logical shift right. 1508defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1509def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1510def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1511 1512// Arithmetic shift right. 1513let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1514 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1515 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1516 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1517} 1518 1519// Rotate left. 1520def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1521def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1522 1523// Rotate second operand left and inserted selected bits into first operand. 1524// These can act like 32-bit operands provided that the constant start and 1525// end bits (operands 2 and 3) are in the range [32, 64). 1526let Defs = [CC] in { 1527 let isCodeGenOnly = 1 in 1528 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1529 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1530 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1531} 1532 1533// On zEC12 we have a variant of RISBG that does not set CC. 1534let Predicates = [FeatureMiscellaneousExtensions] in 1535 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1536 1537// Forms of RISBG that only affect one word of the destination register. 1538// They do not set CC. 1539let Predicates = [FeatureHighWord] in { 1540 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1541 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1542 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1543 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1544 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1545 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1546 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1547} 1548 1549// Rotate second operand left and perform a logical operation with selected 1550// bits of the first operand. The CC result only describes the selected bits, 1551// so isn't useful for a full comparison against zero. 1552let Defs = [CC] in { 1553 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1554 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1555 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1556} 1557 1558//===----------------------------------------------------------------------===// 1559// Comparison 1560//===----------------------------------------------------------------------===// 1561 1562// Signed comparisons. We put these before the unsigned comparisons because 1563// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1564// of the unsigned forms do. 1565let Defs = [CC], CCValues = 0xE in { 1566 // Comparison with a register. 1567 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1568 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1569 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1570 1571 // Comparison with a high register. 1572 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1573 Requires<[FeatureHighWord]>; 1574 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1575 Requires<[FeatureHighWord]>; 1576 1577 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1578 // depending on the choice of register. 1579 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1580 Requires<[FeatureHighWord]>; 1581 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1582 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1583 1584 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1585 // depending on the choice of register. 1586 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1587 Requires<[FeatureHighWord]>; 1588 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1589 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1590 Requires<[FeatureHighWord]>; 1591 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1592 1593 // Comparison with memory. 1594 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1595 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1596 Requires<[FeatureHighWord]>; 1597 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1598 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1599 Requires<[FeatureHighWord]>; 1600 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1601 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1602 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1603 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1604 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1605 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1606 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1607 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1608 1609 // Comparison between memory and a signed 16-bit immediate. 1610 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1611 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1612 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1613} 1614defm : SXB<z_scmp, GR64, CGFR>; 1615 1616// Unsigned comparisons. 1617let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1618 // Comparison with a register. 1619 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1620 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1621 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1622 1623 // Comparison with a high register. 1624 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1625 Requires<[FeatureHighWord]>; 1626 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1627 Requires<[FeatureHighWord]>; 1628 1629 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1630 // or CLIH, depending on the choice of register. 1631 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1632 Requires<[FeatureHighWord]>; 1633 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1634 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1635 Requires<[FeatureHighWord]>; 1636 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1637 1638 // Comparison with memory. 1639 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1640 Requires<[FeatureHighWord]>; 1641 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1642 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1643 Requires<[FeatureHighWord]>; 1644 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1645 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1646 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1647 aligned_azextloadi16>; 1648 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1649 aligned_load>; 1650 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1651 aligned_azextloadi16>; 1652 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1653 aligned_azextloadi32>; 1654 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1655 aligned_load>; 1656 1657 // Comparison between memory and an unsigned 8-bit immediate. 1658 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1659 1660 // Comparison between memory and an unsigned 16-bit immediate. 1661 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1662 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1663 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1664} 1665defm : ZXB<z_ucmp, GR64, CLGFR>; 1666 1667// Memory-to-memory comparison. 1668let mayLoad = 1, Defs = [CC] in { 1669 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>; 1670 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1671 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1672 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1673} 1674 1675// String comparison. 1676let mayLoad = 1, Defs = [CC] in 1677 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1678 1679// Test under mask. 1680let Defs = [CC] in { 1681 // TMxMux expands to TM[LH]x, depending on the choice of register. 1682 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1683 Requires<[FeatureHighWord]>; 1684 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1685 Requires<[FeatureHighWord]>; 1686 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1687 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1688 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1689 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1690 1691 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1692 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1693 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1694 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1695 1696 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1697} 1698 1699def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1700def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1701 1702// Compare logical characters under mask -- not (yet) used for codegen. 1703let Defs = [CC] in { 1704 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1705 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1706} 1707 1708//===----------------------------------------------------------------------===// 1709// Prefetch and execution hint 1710//===----------------------------------------------------------------------===// 1711 1712let mayLoad = 1, mayStore = 1 in { 1713 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1714 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1715} 1716 1717let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1718 // Branch Prediction Preload 1719 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1720 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1721 1722 // Next Instruction Access Intent 1723 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1724} 1725 1726//===----------------------------------------------------------------------===// 1727// Atomic operations 1728//===----------------------------------------------------------------------===// 1729 1730// A serialization instruction that acts as a barrier for all memory 1731// accesses, which expands to "bcr 14, 0". 1732let hasSideEffects = 1 in 1733def Serialize : Alias<2, (outs), (ins), []>; 1734 1735let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1736 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1737 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1738 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1739 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1740 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1741 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1742 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1743 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1744 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1745 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1746} 1747 1748def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1749 1750def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1751def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1752 1753def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1754 1755def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1756def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1757 1758def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1759def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1760 1761def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1762def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1763 1764def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1765def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1766 imm32lh16c>; 1767 1768def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1769def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1770def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1771def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1772 1773def ATOMIC_CMP_SWAPW 1774 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1775 ADDR32:$bitshift, ADDR32:$negbitshift, 1776 uimm32:$bitsize), 1777 [(set GR32:$dst, 1778 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1779 ADDR32:$bitshift, ADDR32:$negbitshift, 1780 uimm32:$bitsize))]> { 1781 let Defs = [CC]; 1782 let mayLoad = 1; 1783 let mayStore = 1; 1784 let usesCustomInserter = 1; 1785 let hasNoSchedulingInfo = 1; 1786} 1787 1788// Test and set. 1789let mayLoad = 1, Defs = [CC] in 1790 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1791 1792// Compare and swap. 1793let Defs = [CC] in { 1794 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1795 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1796} 1797 1798// Compare double and swap. 1799let Defs = [CC] in { 1800 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1801 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1802} 1803 1804// Compare and swap and store. 1805let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1806 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1807 1808// Perform locked operation. 1809let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1810 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1811 1812// Load/store pair from/to quadword. 1813def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1814def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1815 1816// Load pair disjoint. 1817let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1818 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1819 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1820} 1821 1822//===----------------------------------------------------------------------===// 1823// Translate and convert 1824//===----------------------------------------------------------------------===// 1825 1826let mayLoad = 1, mayStore = 1 in 1827 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1828 1829let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1830 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1831 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1832} 1833 1834let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1835 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1836 1837let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1838 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1839 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1840} 1841 1842let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1843 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1844 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1845 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1846 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1847} 1848 1849let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1850 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1851 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1852 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1853 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1854 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1855 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1856 1857 let isAsmParserOnly = 1 in { 1858 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1859 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1860 } 1861} 1862 1863//===----------------------------------------------------------------------===// 1864// Message-security assist 1865//===----------------------------------------------------------------------===// 1866 1867let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1868 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1869 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1870 1871 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1872 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1873 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1874 1875 let Predicates = [FeatureMessageSecurityAssist4] in { 1876 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1877 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1878 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1879 GR128, GR128, GR128>; 1880 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1881 } 1882 1883 let Predicates = [FeatureMessageSecurityAssist5] in 1884 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1885 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1886 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1887 1888 let Predicates = [FeatureMessageSecurityAssist8] in 1889 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1890 GR128, GR128, GR128>; 1891 1892 let Predicates = [FeatureMessageSecurityAssist9] in 1893 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1894} 1895 1896//===----------------------------------------------------------------------===// 1897// Guarded storage 1898//===----------------------------------------------------------------------===// 1899 1900// These instructions use and/or modify the guarded storage control 1901// registers, which we do not otherwise model, so they should have 1902// hasSideEffects. 1903let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1904 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1905 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1906 1907 let mayLoad = 1 in 1908 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1909 let mayStore = 1 in 1910 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1911} 1912 1913//===----------------------------------------------------------------------===// 1914// Decimal arithmetic 1915//===----------------------------------------------------------------------===// 1916 1917defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1918def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1919 1920defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1921def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1922 1923let mayLoad = 1, mayStore = 1 in { 1924 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1925 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1926 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1927 1928 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1929 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1930 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1931 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1932 let Defs = [CC] in { 1933 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1934 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1935 } 1936} 1937 1938let mayLoad = 1, mayStore = 1 in { 1939 let Defs = [CC] in { 1940 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1941 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1942 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1943 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1944 } 1945 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1946 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1947 let Defs = [CC] in { 1948 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1949 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1950 } 1951} 1952 1953let Defs = [CC] in { 1954 def CP : CompareSSb<"cp", 0xF9>; 1955 def TP : TestRSL<"tp", 0xEBC0>; 1956} 1957 1958//===----------------------------------------------------------------------===// 1959// Access registers 1960//===----------------------------------------------------------------------===// 1961 1962// Read a 32-bit access register into a GR32. As with all GR32 operations, 1963// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1964// when a 64-bit address is stored in a pair of access registers. 1965def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1966 1967// Set access register. 1968def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1969 1970// Copy access register. 1971def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1972 1973// Load address extended. 1974defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1975 1976// Load access multiple. 1977defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1978 1979// Store access multiple. 1980defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1981 1982//===----------------------------------------------------------------------===// 1983// Program mask and addressing mode 1984//===----------------------------------------------------------------------===// 1985 1986// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1987let Uses = [CC] in 1988 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1989 1990// Set CC and program mask from a register. 1991let hasSideEffects = 1, Defs = [CC] in 1992 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1993 1994// Branch and link - like BAS, but also extracts CC and program mask. 1995let isCall = 1, Uses = [CC], Defs = [CC] in { 1996 def BAL : CallRX<"bal", 0x45>; 1997 def BALR : CallRR<"balr", 0x05>; 1998} 1999 2000// Test addressing mode. 2001let Defs = [CC] in 2002 def TAM : SideEffectInherentE<"tam", 0x010B>; 2003 2004// Set addressing mode. 2005let hasSideEffects = 1 in { 2006 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2007 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2008 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2009} 2010 2011// Branch and set mode. Not really a call, but also sets an output register. 2012let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2013 def BSM : CallRR<"bsm", 0x0B>; 2014 2015// Branch and save and set mode. 2016let isCall = 1, Defs = [CC] in 2017 def BASSM : CallRR<"bassm", 0x0C>; 2018 2019//===----------------------------------------------------------------------===// 2020// Transactional execution 2021//===----------------------------------------------------------------------===// 2022 2023let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2024 // Transaction Begin 2025 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2026 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2027 let hasNoSchedulingInfo = 1 in 2028 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2029 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2030 int_s390_tbeginc, imm32zx16>; 2031 } 2032 2033 // Transaction End 2034 let Defs = [CC] in 2035 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2036 2037 // Transaction Abort 2038 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2039 hasSideEffects = 1 in 2040 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2041 2042 // Nontransactional Store 2043 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2044 2045 // Extract Transaction Nesting Depth 2046 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2047} 2048 2049//===----------------------------------------------------------------------===// 2050// Processor assist 2051//===----------------------------------------------------------------------===// 2052 2053let Predicates = [FeatureProcessorAssist] in { 2054 let hasSideEffects = 1 in 2055 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2056 def : Pat<(int_s390_ppa_txassist GR32:$src), 2057 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2058 zero_reg, 1)>; 2059} 2060 2061//===----------------------------------------------------------------------===// 2062// Miscellaneous Instructions. 2063//===----------------------------------------------------------------------===// 2064 2065// Find leftmost one, AKA count leading zeros. The instruction actually 2066// returns a pair of GR64s, the first giving the number of leading zeros 2067// and the second giving a copy of the source with the leftmost one bit 2068// cleared. We only use the first result here. 2069let Defs = [CC] in 2070 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2071def : Pat<(i64 (ctlz GR64:$src)), 2072 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2073 2074// Population count. Counts bits set per byte or doubleword. 2075let Predicates = [FeatureMiscellaneousExtensions3] in { 2076 let Defs = [CC] in 2077 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2078 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2079} 2080let Predicates = [FeaturePopulationCount], Defs = [CC] in 2081 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2082 2083// Search a block of memory for a character. 2084let mayLoad = 1, Defs = [CC] in 2085 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2086let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2087 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2088 2089// Compare until substring equal. 2090let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2091 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2092 2093// Compare and form codeword. 2094let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2095 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2096 2097// Update tree. 2098let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2099 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2100 def UPT : SideEffectInherentE<"upt", 0x0102>; 2101 2102// Checksum. 2103let mayLoad = 1, Defs = [CC] in 2104 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2105 2106// Compression call. 2107let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2108 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2109 2110// Sort lists. 2111let Predicates = [FeatureEnhancedSort], 2112 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2113 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2114 2115// Deflate conversion call. 2116let Predicates = [FeatureDeflateConversion], 2117 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2118 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2119 GR128, GR128, GR64>; 2120 2121// NNPA. 2122let Predicates = [FeatureNNPAssist], 2123 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2124 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2125 2126// Execute. 2127let hasSideEffects = 1 in { 2128 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2129 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2130 let hasNoSchedulingInfo = 1 in 2131 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2132 bdaddr12only:$bdl1, bdaddr12only:$bd2), 2133 []>; 2134} 2135 2136//===----------------------------------------------------------------------===// 2137// .insn directive instructions 2138//===----------------------------------------------------------------------===// 2139 2140let isCodeGenOnly = 1, hasSideEffects = 1 in { 2141 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2142 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2143 imm32sx16:$I2), 2144 ".insn ri,$enc,$R1,$I2", []>; 2145 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2146 AnyReg:$R3, brtarget16:$I2), 2147 ".insn rie,$enc,$R1,$R3,$I2", []>; 2148 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2149 brtarget32:$I2), 2150 ".insn ril,$enc,$R1,$I2", []>; 2151 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2152 uimm32:$I2), 2153 ".insn rilu,$enc,$R1,$I2", []>; 2154 def InsnRIS : DirectiveInsnRIS<(outs), 2155 (ins imm64zx48:$enc, AnyReg:$R1, 2156 imm32sx8:$I2, imm32zx4:$M3, 2157 (bdaddr12only $B4, $D4):$BD4), 2158 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2159 def InsnRR : DirectiveInsnRR<(outs), 2160 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2161 ".insn rr,$enc,$R1,$R2", []>; 2162 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2163 AnyReg:$R1, AnyReg:$R2), 2164 ".insn rre,$enc,$R1,$R2", []>; 2165 def InsnRRF : DirectiveInsnRRF<(outs), 2166 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2167 AnyReg:$R3, imm32zx4:$M4), 2168 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2169 def InsnRRS : DirectiveInsnRRS<(outs), 2170 (ins imm64zx48:$enc, AnyReg:$R1, 2171 AnyReg:$R2, imm32zx4:$M3, 2172 (bdaddr12only $B4, $D4):$BD4), 2173 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2174 def InsnRS : DirectiveInsnRS<(outs), 2175 (ins imm64zx32:$enc, AnyReg:$R1, 2176 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 2177 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2178 def InsnRSE : DirectiveInsnRSE<(outs), 2179 (ins imm64zx48:$enc, AnyReg:$R1, 2180 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 2181 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2182 def InsnRSI : DirectiveInsnRSI<(outs), 2183 (ins imm64zx48:$enc, AnyReg:$R1, 2184 AnyReg:$R3, brtarget16:$RI2), 2185 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2186 def InsnRSY : DirectiveInsnRSY<(outs), 2187 (ins imm64zx48:$enc, AnyReg:$R1, 2188 AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2), 2189 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2190 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2191 (bdxaddr12only $B2, $D2, $X2):$XBD2), 2192 ".insn rx,$enc,$R1,$XBD2", []>; 2193 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2194 (bdxaddr12only $B2, $D2, $X2):$XBD2), 2195 ".insn rxe,$enc,$R1,$XBD2", []>; 2196 def InsnRXF : DirectiveInsnRXF<(outs), 2197 (ins imm64zx48:$enc, AnyReg:$R1, 2198 AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2199 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2200 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2201 (bdxaddr20only $B2, $D2, $X2):$XBD2), 2202 ".insn rxy,$enc,$R1,$XBD2", []>; 2203 def InsnS : DirectiveInsnS<(outs), 2204 (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2), 2205 ".insn s,$enc,$BD2", []>; 2206 def InsnSI : DirectiveInsnSI<(outs), 2207 (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, 2208 imm32sx8:$I2), 2209 ".insn si,$enc,$BD1,$I2", []>; 2210 def InsnSIY : DirectiveInsnSIY<(outs), 2211 (ins imm64zx48:$enc, 2212 (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2), 2213 ".insn siy,$enc,$BD1,$I2", []>; 2214 def InsnSIL : DirectiveInsnSIL<(outs), 2215 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 2216 imm32zx16:$I2), 2217 ".insn sil,$enc,$BD1,$I2", []>; 2218 def InsnSS : DirectiveInsnSS<(outs), 2219 (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1, 2220 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 2221 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2222 def InsnSSE : DirectiveInsnSSE<(outs), 2223 (ins imm64zx48:$enc, 2224 (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2), 2225 ".insn sse,$enc,$BD1,$BD2", []>; 2226 def InsnSSF : DirectiveInsnSSF<(outs), 2227 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 2228 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 2229 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2230 def InsnVRI : DirectiveInsnVRI<(outs), 2231 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2232 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2233 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2234 def InsnVRR : DirectiveInsnVRR<(outs), 2235 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2236 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2237 imm32zx4:$M6), 2238 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2239 def InsnVRS : DirectiveInsnVRS<(outs), 2240 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2241 (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4), 2242 ".insn vrs,$enc,$BD2,$M4", []>; 2243 def InsnVRV : DirectiveInsnVRV<(outs), 2244 (ins imm64zx48:$enc, VR128:$V1, 2245 (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3), 2246 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2247 def InsnVRX : DirectiveInsnVRX<(outs), 2248 (ins imm64zx48:$enc, VR128:$V1, 2249 (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 2250 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2251 def InsnVSI : DirectiveInsnVSI<(outs), 2252 (ins imm64zx48:$enc, VR128:$V1, 2253 (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 2254 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2255} 2256 2257//===----------------------------------------------------------------------===// 2258// Peepholes. 2259//===----------------------------------------------------------------------===// 2260 2261// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2262// equivalent to (and (xor x, -1), y) 2263def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2264 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2265 2266// Use LCGR/AGHI for i64 xor with -1. 2267def : Pat<(xor GR64:$x, (i64 -1)), 2268 (AGHI (LCGR GR64:$x), (i64 -1))>; 2269 2270// Shift/rotate instructions only use the last 6 bits of the second operand 2271// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2272// last 16 bits. 2273// Complexity is added so that we match this before we match NILF on the AND 2274// operation alone. 2275let AddedComplexity = 4 in { 2276 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2277 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2278 2279 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2280 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2281 2282 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2283 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2284 2285 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2286 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2287 2288 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2289 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2290 2291 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2292 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2293 2294 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2295 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2296 2297 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2298 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2299} 2300 2301// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2302// use the last 6 bits of the second operand register (making it modulo 64). 2303let AddedComplexity = 4 in { 2304 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2305 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2306 2307 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2308 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2309 2310 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2311 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2312 2313 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2314 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2315} 2316 2317// Peepholes for turning scalar operations into block operations. The length 2318// is given as one less for these pseudos. 2319defm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>; 2320defm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>; 2321defm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>; 2322defm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>; 2323defm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>; 2324defm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>; 2325defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>; 2326 2327//===----------------------------------------------------------------------===// 2328// Mnemonic Aliases 2329//===----------------------------------------------------------------------===// 2330 2331def JCT : MnemonicAlias<"jct", "brct">; 2332def JCTG : MnemonicAlias<"jctg", "brctg">; 2333def JAS : MnemonicAlias<"jas", "bras">; 2334def JASL : MnemonicAlias<"jasl", "brasl">; 2335def JXH : MnemonicAlias<"jxh", "brxh">; 2336def JXLE : MnemonicAlias<"jxle", "brxle">; 2337def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2338def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2339 2340def BRU : MnemonicAlias<"bru", "j">; 2341def BRUL : MnemonicAlias<"brul", "jg", "att">; 2342def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2343 2344foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2345 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2346 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2347 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; 2348 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2349} 2350