1//===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// Class definitions
11//===----------------------------------------------------------------------===//
12
13class ImmediateAsmOperand<string name>
14  : AsmOperandClass {
15  let Name = name;
16  let RenderMethod = "addImmOperands";
17}
18class ImmediateTLSAsmOperand<string name>
19  : AsmOperandClass {
20  let Name = name;
21  let RenderMethod = "addImmTLSOperands";
22}
23
24class ImmediateOp<ValueType vt, string asmop> : Operand<vt> {
25  let PrintMethod = "print"#asmop#"Operand";
26  let DecoderMethod = "decode"#asmop#"Operand";
27  let ParserMatchClass = !cast<AsmOperandClass>(asmop);
28  let OperandType = "OPERAND_IMMEDIATE";
29}
30
31class ImmOpWithPattern<ValueType vt, string asmop, code pred, SDNodeXForm xform,
32      SDNode ImmNode = imm> :
33  ImmediateOp<vt, asmop>, PatLeaf<(vt ImmNode), pred, xform>;
34
35// class ImmediatePatLeaf<ValueType vt, code pred,
36//       SDNodeXForm xform, SDNode ImmNode>
37//   : PatLeaf<(vt ImmNode), pred, xform>;
38
39
40// Constructs both a DAG pattern and instruction operand for an immediate
41// of type VT.  PRED returns true if a node is acceptable and XFORM returns
42// the operand value associated with the node.  ASMOP is the name of the
43// associated asm operand, and also forms the basis of the asm print method.
44multiclass Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop> {
45  // def "" : ImmediateOp<vt, asmop>,
46  //          PatLeaf<(vt imm), pred, xform>;
47  def "" : ImmOpWithPattern<vt, asmop, pred, xform>;
48
49//  def _timm : PatLeaf<(vt timm), pred, xform>;
50  def _timm : ImmOpWithPattern<vt, asmop, pred, xform, timm>;
51}
52
53// Constructs an asm operand for a PC-relative address.  SIZE says how
54// many bits there are.
55class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"#size> {
56  let PredicateMethod = "isImm";
57  let ParserMethod = "parsePCRel"#size;
58}
59class PCRelTLSAsmOperand<string size>
60  : ImmediateTLSAsmOperand<"PCRelTLS"#size> {
61  let PredicateMethod = "isImmTLS";
62  let ParserMethod = "parsePCRelTLS"#size;
63}
64
65// Constructs an operand for a PC-relative address with address type VT.
66// ASMOP is the associated asm operand.
67let OperandType = "OPERAND_PCREL" in {
68  class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
69    let PrintMethod = "printPCRelOperand";
70    let ParserMatchClass = asmop;
71  }
72  class PCRelTLSOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
73    let PrintMethod = "printPCRelTLSOperand";
74    let ParserMatchClass = asmop;
75  }
76}
77
78// Constructs both a DAG pattern and instruction operand for a PC-relative
79// address with address size VT.  SELF is the name of the operand and
80// ASMOP is the associated asm operand.
81class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
82  : ComplexPattern<vt, 1, "selectPCRelAddress",
83                   [z_pcrel_wrapper, z_pcrel_offset]>,
84    PCRelOperand<vt, asmop> {
85  let MIOperandInfo = (ops !cast<Operand>(self));
86}
87
88// Constructs an AsmOperandClass for addressing mode FORMAT, treating the
89// registers as having BITSIZE bits and displacements as having DISPSIZE bits.
90// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it
91// is "".
92class AddressAsmOperand<string format, string bitsize, string dispsize,
93                        string length = "">
94  : AsmOperandClass {
95  let Name = format#bitsize#"Disp"#dispsize#length;
96  let ParserMethod = "parse"#format#bitsize;
97  let RenderMethod = "add"#format#"Operands";
98}
99
100// Constructs an instruction operand for an addressing mode.  FORMAT,
101// BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
102// AddressAsmOperand.  OPERANDS is a list of individual operands
103// (base register, displacement, etc.).
104class AddressOperand<string bitsize, string dispsize, string length,
105                     string format, dag operands>
106  : Operand<!cast<ValueType>("i"#bitsize)> {
107  let PrintMethod = "print"#format#"Operand";
108  let EncoderMethod = "get"#format#dispsize#length#"Encoding";
109  let DecoderMethod =
110    "decode"#format#bitsize#"Disp"#dispsize#length#"Operand";
111  let OperandType = "OPERAND_MEMORY";
112  let MIOperandInfo = operands;
113  let ParserMatchClass =
114    !cast<AddressAsmOperand>(format#bitsize#"Disp"#dispsize#length);
115}
116
117// Constructs both a DAG pattern and instruction operand for an addressing mode.
118// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
119// AddressAsmOperand.  OPERANDS is a list of NUMOPS individual operands
120// (base register, displacement, etc.).  SELTYPE is the type of the memory
121// operand for selection purposes; sometimes we want different selection
122// choices for the same underlying addressing mode.  SUFFIX is similarly
123// a suffix appended to the displacement for selection purposes;
124// e.g. we want to reject small 20-bit displacements if a 12-bit form
125// also exists, but we want to accept them otherwise.
126class AddressingMode<string seltype, string bitsize, string dispsize,
127                     string suffix, string length, int numops, string format,
128                     dag operands>
129  : ComplexPattern<!cast<ValueType>("i"#bitsize), numops,
130                   "select"#seltype#dispsize#suffix#length,
131                   [add, sub, or, frameindex, z_adjdynalloc]>,
132    AddressOperand<bitsize, dispsize, length, format, operands>;
133
134// An addressing mode with a base and displacement but no index.
135class BDMode<string type, string bitsize, string dispsize, string suffix>
136  : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
137                   (ops !cast<RegisterOperand>("ADDR"#bitsize),
138                        !cast<Operand>("disp"#dispsize#"imm"#bitsize))>;
139
140// An addressing mode with a base, displacement and index.
141class BDXMode<string type, string bitsize, string dispsize, string suffix>
142  : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
143                   (ops !cast<RegisterOperand>("ADDR"#bitsize),
144                        !cast<Operand>("disp"#dispsize#"imm"#bitsize),
145                        !cast<RegisterOperand>("ADDR"#bitsize))>;
146
147// A BDMode paired with an immediate length operand of LENSIZE bits.
148class BDLMode<string type, string bitsize, string dispsize, string suffix,
149              string lensize>
150  : AddressingMode<type, bitsize, dispsize, suffix, "Len"#lensize, 3,
151                   "BDLAddr",
152                   (ops !cast<RegisterOperand>("ADDR"#bitsize),
153                        !cast<Operand>("disp"#dispsize#"imm"#bitsize),
154                        !cast<Operand>("imm"#bitsize))>;
155
156// A BDMode paired with a register length operand.
157class BDRMode<string type, string bitsize, string dispsize, string suffix>
158  : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDRAddr",
159                   (ops !cast<RegisterOperand>("ADDR"#bitsize),
160                        !cast<Operand>("disp"#dispsize#"imm"#bitsize),
161                        !cast<RegisterOperand>("GR"#bitsize))>;
162
163// An addressing mode with a base, displacement and a vector index.
164class BDVMode<string bitsize, string dispsize>
165  : AddressOperand<bitsize, dispsize, "", "BDVAddr",
166                   (ops !cast<RegisterOperand>("ADDR"#bitsize),
167                        !cast<Operand>("disp"#dispsize#"imm"#bitsize),
168                        !cast<RegisterOperand>("VR128"))>;
169
170//===----------------------------------------------------------------------===//
171// Extracting immediate operands from nodes
172// These all create MVT::i64 nodes to ensure the value is not sign-extended
173// when converted from an SDNode to a MachineOperand later on.
174//===----------------------------------------------------------------------===//
175
176// Bits 0-15 (counting from the lsb).
177def LL16 : SDNodeXForm<imm, [{
178  uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
179  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
180}]>;
181
182// Bits 16-31 (counting from the lsb).
183def LH16 : SDNodeXForm<imm, [{
184  uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
185  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
186}]>;
187
188// Bits 32-47 (counting from the lsb).
189def HL16 : SDNodeXForm<imm, [{
190  uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
191  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
192}]>;
193
194// Bits 48-63 (counting from the lsb).
195def HH16 : SDNodeXForm<imm, [{
196  uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
197  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
198}]>;
199
200// Low 32 bits.
201def LF32 : SDNodeXForm<imm, [{
202  uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
203  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
204}]>;
205
206// High 32 bits.
207def HF32 : SDNodeXForm<imm, [{
208  uint64_t Value = N->getZExtValue() >> 32;
209  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
210}]>;
211
212// Negated variants.
213def NEGLH16 : SDNodeXForm<imm, [{
214  uint64_t Value = (-N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
215  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
216}]>;
217
218def NEGLF32 : SDNodeXForm<imm, [{
219  uint64_t Value = -N->getZExtValue() & 0x00000000FFFFFFFFULL;
220  return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
221}]>;
222
223// Truncate an immediate to a 8-bit signed quantity.
224def SIMM8 : SDNodeXForm<imm, [{
225  return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
226                                   MVT::i64);
227}]>;
228
229// Truncate an immediate to a 8-bit unsigned quantity.
230def UIMM8 : SDNodeXForm<imm, [{
231  return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N),
232                                   MVT::i64);
233}]>;
234
235// Truncate an immediate to a 8-bit unsigned quantity and mask off low bit.
236def UIMM8EVEN : SDNodeXForm<imm, [{
237  return CurDAG->getTargetConstant(N->getZExtValue() & 0xfe, SDLoc(N),
238                                   MVT::i64);
239}]>;
240
241// Truncate an immediate to a 12-bit unsigned quantity.
242def UIMM12 : SDNodeXForm<imm, [{
243  return CurDAG->getTargetConstant(N->getZExtValue() & 0xfff, SDLoc(N),
244                                   MVT::i64);
245}]>;
246
247// Truncate an immediate to a 16-bit signed quantity.
248def SIMM16 : SDNodeXForm<imm, [{
249  return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
250                                   MVT::i64);
251}]>;
252
253// Negate and then truncate an immediate to a 16-bit signed quantity.
254def NEGSIMM16 : SDNodeXForm<imm, [{
255  return CurDAG->getTargetConstant(int16_t(-N->getZExtValue()), SDLoc(N),
256                                   MVT::i64);
257}]>;
258
259// Truncate an immediate to a 16-bit unsigned quantity.
260def UIMM16 : SDNodeXForm<imm, [{
261  return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N),
262                                   MVT::i64);
263}]>;
264
265// Truncate an immediate to a 32-bit signed quantity.
266def SIMM32 : SDNodeXForm<imm, [{
267  return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N),
268                                   MVT::i64);
269}]>;
270
271// Negate and then truncate an immediate to a 32-bit unsigned quantity.
272def NEGSIMM32 : SDNodeXForm<imm, [{
273  return CurDAG->getTargetConstant(int32_t(-N->getZExtValue()), SDLoc(N),
274                                   MVT::i64);
275}]>;
276
277// Truncate an immediate to a 32-bit unsigned quantity.
278def UIMM32 : SDNodeXForm<imm, [{
279  return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),
280                                   MVT::i64);
281}]>;
282
283// Negate and then truncate an immediate to a 32-bit unsigned quantity.
284def NEGUIMM32 : SDNodeXForm<imm, [{
285  return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),
286                                   MVT::i64);
287}]>;
288
289// Truncate an immediate to a 48-bit unsigned quantity.
290def UIMM48 : SDNodeXForm<imm, [{
291  return CurDAG->getTargetConstant(uint64_t(N->getZExtValue()) & 0xffffffffffff,
292                                   SDLoc(N), MVT::i64);
293}]>;
294
295//===----------------------------------------------------------------------===//
296// Immediate asm operands.
297//===----------------------------------------------------------------------===//
298
299def U1Imm  : ImmediateAsmOperand<"U1Imm">;
300def U2Imm  : ImmediateAsmOperand<"U2Imm">;
301def U3Imm  : ImmediateAsmOperand<"U3Imm">;
302def U4Imm  : ImmediateAsmOperand<"U4Imm">;
303def U6Imm  : ImmediateAsmOperand<"U6Imm">;
304def S8Imm  : ImmediateAsmOperand<"S8Imm">;
305def U8Imm  : ImmediateAsmOperand<"U8Imm">;
306def U12Imm : ImmediateAsmOperand<"U12Imm">;
307def S16Imm : ImmediateAsmOperand<"S16Imm">;
308def U16Imm : ImmediateAsmOperand<"U16Imm">;
309def S32Imm : ImmediateAsmOperand<"S32Imm">;
310def U32Imm : ImmediateAsmOperand<"U32Imm">;
311def U48Imm : ImmediateAsmOperand<"U48Imm">;
312
313//===----------------------------------------------------------------------===//
314// i32 immediates
315//===----------------------------------------------------------------------===//
316
317// Immediates for the lower and upper 16 bits of an i32, with the other
318// bits of the i32 being zero.
319defm imm32ll16 : Immediate<i32, [{
320  return SystemZ::isImmLL(N->getZExtValue());
321}], LL16, "U16Imm">;
322
323defm imm32lh16 : Immediate<i32, [{
324  return SystemZ::isImmLH(N->getZExtValue());
325}], LH16, "U16Imm">;
326
327// Immediates for the lower and upper 16 bits of an i32, with the other
328// bits of the i32 being one.
329defm imm32ll16c : Immediate<i32, [{
330  return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
331}], LL16, "U16Imm">;
332
333defm imm32lh16c : Immediate<i32, [{
334  return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
335}], LH16, "U16Imm">;
336
337// Short immediates
338defm imm32zx1 : Immediate<i32, [{
339  return isUInt<1>(N->getZExtValue());
340}], NOOP_SDNodeXForm, "U1Imm">;
341
342defm imm32zx2 : Immediate<i32, [{
343  return isUInt<2>(N->getZExtValue());
344}], NOOP_SDNodeXForm, "U2Imm">;
345
346defm imm32zx3 : Immediate<i32, [{
347  return isUInt<3>(N->getZExtValue());
348}], NOOP_SDNodeXForm, "U3Imm">;
349
350defm imm32zx4 : Immediate<i32, [{
351  return isUInt<4>(N->getZExtValue());
352}], NOOP_SDNodeXForm, "U4Imm">;
353
354// Note: this enforces an even value during code generation only.
355// When used from the assembler, any 4-bit value is allowed.
356defm imm32zx4even : Immediate<i32, [{
357  return isUInt<4>(N->getZExtValue());
358}], UIMM8EVEN, "U4Imm">;
359
360defm imm32zx6 : Immediate<i32, [{
361  return isUInt<6>(N->getZExtValue());
362}], NOOP_SDNodeXForm, "U6Imm">;
363
364defm imm32sx8 : Immediate<i32, [{
365  return isInt<8>(N->getSExtValue());
366}], SIMM8, "S8Imm">;
367
368defm imm32zx8 : Immediate<i32, [{
369  return isUInt<8>(N->getZExtValue());
370}], UIMM8, "U8Imm">;
371
372defm imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
373
374defm imm32zx12 : Immediate<i32, [{
375  return isUInt<12>(N->getZExtValue());
376}], UIMM12, "U12Imm">;
377
378defm imm32sx16 : Immediate<i32, [{
379  return isInt<16>(N->getSExtValue());
380}], SIMM16, "S16Imm">;
381
382defm imm32sx16n : Immediate<i32, [{
383  return isInt<16>(-N->getSExtValue());
384}], NEGSIMM16, "S16Imm">;
385
386defm imm32zx16 : Immediate<i32, [{
387  return isUInt<16>(N->getZExtValue());
388}], UIMM16, "U16Imm">;
389
390defm imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
391defm imm32zx16trunc : Immediate<i32, [{}], UIMM16, "U16Imm">;
392
393// Full 32-bit immediates.  we need both signed and unsigned versions
394// because the assembler is picky.  E.g. AFI requires signed operands
395// while NILF requires unsigned ones.
396defm simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
397defm uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
398
399defm simm32n : Immediate<i32, [{
400  return isInt<32>(-N->getSExtValue());
401}], NEGSIMM32, "S32Imm">;
402
403def imm32 : ImmLeaf<i32, [{}]>;
404
405//===----------------------------------------------------------------------===//
406// 64-bit immediates
407//===----------------------------------------------------------------------===//
408
409// Immediates for 16-bit chunks of an i64, with the other bits of the
410// i32 being zero.
411defm imm64ll16 : Immediate<i64, [{
412  return SystemZ::isImmLL(N->getZExtValue());
413}], LL16, "U16Imm">;
414
415defm imm64lh16 : Immediate<i64, [{
416  return SystemZ::isImmLH(N->getZExtValue());
417}], LH16, "U16Imm">;
418
419defm imm64hl16 : Immediate<i64, [{
420  return SystemZ::isImmHL(N->getZExtValue());
421}], HL16, "U16Imm">;
422
423defm imm64hh16 : Immediate<i64, [{
424  return SystemZ::isImmHH(N->getZExtValue());
425}], HH16, "U16Imm">;
426
427// Immediates for 16-bit chunks of an i64, with the other bits of the
428// i32 being one.
429defm imm64ll16c : Immediate<i64, [{
430  return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
431}], LL16, "U16Imm">;
432
433defm imm64lh16c : Immediate<i64, [{
434  return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
435}], LH16, "U16Imm">;
436
437defm imm64hl16c : Immediate<i64, [{
438  return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
439}], HL16, "U16Imm">;
440
441defm imm64hh16c : Immediate<i64, [{
442  return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
443}], HH16, "U16Imm">;
444
445// Immediates for the lower and upper 32 bits of an i64, with the other
446// bits of the i32 being zero.
447defm imm64lf32 : Immediate<i64, [{
448  return SystemZ::isImmLF(N->getZExtValue());
449}], LF32, "U32Imm">;
450
451defm imm64hf32 : Immediate<i64, [{
452  return SystemZ::isImmHF(N->getZExtValue());
453}], HF32, "U32Imm">;
454
455// Immediates for the lower and upper 32 bits of an i64, with the other
456// bits of the i32 being one.
457defm imm64lf32c : Immediate<i64, [{
458  return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
459}], LF32, "U32Imm">;
460
461defm imm64hf32c : Immediate<i64, [{
462  return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
463}], HF32, "U32Imm">;
464
465// Negated immediates that fit LF32 or LH16.
466defm imm64lh16n : Immediate<i64, [{
467  return SystemZ::isImmLH(uint64_t(-N->getZExtValue()));
468}], NEGLH16, "U16Imm">;
469
470defm imm64lf32n : Immediate<i64, [{
471  return SystemZ::isImmLF(uint64_t(-N->getZExtValue()));
472}], NEGLF32, "U32Imm">;
473
474// Short immediates.
475defm imm64sx8 : Immediate<i64, [{
476  return isInt<8>(N->getSExtValue());
477}], SIMM8, "S8Imm">;
478
479defm imm64zx8 : Immediate<i64, [{
480  return isUInt<8>(N->getSExtValue());
481}], UIMM8, "U8Imm">;
482
483defm imm64sx16 : Immediate<i64, [{
484  return isInt<16>(N->getSExtValue());
485}], SIMM16, "S16Imm">;
486
487defm imm64sx16n : Immediate<i64, [{
488  return isInt<16>(-N->getSExtValue());
489}], NEGSIMM16, "S16Imm">;
490
491defm imm64zx16 : Immediate<i64, [{
492  return isUInt<16>(N->getZExtValue());
493}], UIMM16, "U16Imm">;
494
495defm imm64sx32 : Immediate<i64, [{
496  return isInt<32>(N->getSExtValue());
497}], SIMM32, "S32Imm">;
498
499defm imm64sx32n : Immediate<i64, [{
500  return isInt<32>(-N->getSExtValue());
501}], NEGSIMM32, "S32Imm">;
502
503defm imm64zx32 : Immediate<i64, [{
504  return isUInt<32>(N->getZExtValue());
505}], UIMM32, "U32Imm">;
506
507defm imm64zx32n : Immediate<i64, [{
508  return isUInt<32>(-N->getSExtValue());
509}], NEGUIMM32, "U32Imm">;
510
511defm imm64zx48 : Immediate<i64, [{
512  return isUInt<64>(N->getZExtValue());
513}], UIMM48, "U48Imm">;
514
515let OperandType = "OPERAND_IMMEDIATE" in
516  def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
517
518//===----------------------------------------------------------------------===//
519// Floating-point immediates
520//===----------------------------------------------------------------------===//
521
522// Floating-point zero.
523def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
524
525// Floating point negative zero.
526def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
527
528//===----------------------------------------------------------------------===//
529// Symbolic address operands
530//===----------------------------------------------------------------------===//
531
532// PC-relative asm operands.
533def PCRel12 : PCRelAsmOperand<"12">;
534def PCRel16 : PCRelAsmOperand<"16">;
535def PCRel24 : PCRelAsmOperand<"24">;
536def PCRel32 : PCRelAsmOperand<"32">;
537def PCRelTLS16 : PCRelTLSAsmOperand<"16">;
538def PCRelTLS32 : PCRelTLSAsmOperand<"32">;
539
540// PC-relative offsets of a basic block.  The offset is sign-extended
541// and multiplied by 2.
542def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
543  let EncoderMethod = "getPC16DBLEncoding";
544  let DecoderMethod = "decodePC16DBLBranchOperand";
545}
546def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
547  let EncoderMethod = "getPC32DBLEncoding";
548  let DecoderMethod = "decodePC32DBLBranchOperand";
549}
550
551// Variants of brtarget for use with branch prediction preload.
552def brtarget12bpp : PCRelOperand<OtherVT, PCRel12> {
553  let EncoderMethod = "getPC12DBLBPPEncoding";
554  let DecoderMethod = "decodePC12DBLBranchOperand";
555}
556def brtarget16bpp : PCRelOperand<OtherVT, PCRel16> {
557  let EncoderMethod = "getPC16DBLBPPEncoding";
558  let DecoderMethod = "decodePC16DBLBranchOperand";
559}
560def brtarget24bpp : PCRelOperand<OtherVT, PCRel24> {
561  let EncoderMethod = "getPC24DBLBPPEncoding";
562  let DecoderMethod = "decodePC24DBLBranchOperand";
563}
564
565// Variants of brtarget16/32 with an optional additional TLS symbol.
566// These are used to annotate calls to __tls_get_offset.
567def tlssym : Operand<i64> { }
568def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> {
569  let MIOperandInfo = (ops brtarget16:$func, tlssym:$sym);
570  let EncoderMethod = "getPC16DBLTLSEncoding";
571  let DecoderMethod = "decodePC16DBLBranchOperand";
572}
573def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> {
574  let MIOperandInfo = (ops brtarget32:$func, tlssym:$sym);
575  let EncoderMethod = "getPC32DBLTLSEncoding";
576  let DecoderMethod = "decodePC32DBLBranchOperand";
577}
578
579// A PC-relative offset of a global value.  The offset is sign-extended
580// and multiplied by 2.
581def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
582  let EncoderMethod = "getPC32DBLEncoding";
583  let DecoderMethod = "decodePC32DBLOperand";
584}
585
586//===----------------------------------------------------------------------===//
587// Addressing modes
588//===----------------------------------------------------------------------===//
589
590// 12-bit displacement operands.
591def disp12imm32 : Operand<i32>;
592def disp12imm64 : Operand<i64>;
593
594// 20-bit displacement operands.
595def disp20imm32 : Operand<i32>;
596def disp20imm64 : Operand<i64>;
597
598def BDAddr32Disp12      : AddressAsmOperand<"BDAddr",   "32", "12">;
599def BDAddr32Disp20      : AddressAsmOperand<"BDAddr",   "32", "20">;
600def BDAddr64Disp12      : AddressAsmOperand<"BDAddr",   "64", "12">;
601def BDAddr64Disp20      : AddressAsmOperand<"BDAddr",   "64", "20">;
602def BDXAddr64Disp12     : AddressAsmOperand<"BDXAddr",  "64", "12">;
603def BDXAddr64Disp20     : AddressAsmOperand<"BDXAddr",  "64", "20">;
604def BDLAddr64Disp12Len4 : AddressAsmOperand<"BDLAddr",  "64", "12", "Len4">;
605def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr",  "64", "12", "Len8">;
606def BDRAddr64Disp12     : AddressAsmOperand<"BDRAddr",  "64", "12">;
607def BDVAddr64Disp12     : AddressAsmOperand<"BDVAddr",  "64", "12">;
608
609// DAG patterns and operands for addressing modes.  Each mode has
610// the form <type><range><group>[<len>] where:
611//
612// <type> is one of:
613//   shift    : base + displacement (32-bit)
614//   bdaddr   : base + displacement
615//   mviaddr  : like bdaddr, but reject cases with a natural index
616//   bdxaddr  : base + displacement + index
617//   laaddr   : like bdxaddr, but used for Load Address operations
618//   dynalloc : base + displacement + index + ADJDYNALLOC
619//   bdladdr  : base + displacement with a length field
620//   bdvaddr  : base + displacement with a vector index
621//
622// <range> is one of:
623//   12       : the displacement is an unsigned 12-bit value
624//   20       : the displacement is a signed 20-bit value
625//
626// <group> is one of:
627//   pair     : used when there is an equivalent instruction with the opposite
628//              range value (12 or 20)
629//   only     : used when there is no equivalent instruction with the opposite
630//              range value
631//
632// <len> is one of:
633//
634//   <empty>  : there is no length field
635//   len8     : the length field is 8 bits, with a range of [1, 0x100].
636def shift12only       : BDMode <"BDAddr",   "32", "12", "Only">;
637def shift20only       : BDMode <"BDAddr",   "32", "20", "Only">;
638def bdaddr12only      : BDMode <"BDAddr",   "64", "12", "Only">;
639def bdaddr12pair      : BDMode <"BDAddr",   "64", "12", "Pair">;
640def bdaddr20only      : BDMode <"BDAddr",   "64", "20", "Only">;
641def bdaddr20pair      : BDMode <"BDAddr",   "64", "20", "Pair">;
642def mviaddr12pair     : BDMode <"MVIAddr",  "64", "12", "Pair">;
643def mviaddr20pair     : BDMode <"MVIAddr",  "64", "20", "Pair">;
644def bdxaddr12only     : BDXMode<"BDXAddr",  "64", "12", "Only">;
645def bdxaddr12pair     : BDXMode<"BDXAddr",  "64", "12", "Pair">;
646def bdxaddr20only     : BDXMode<"BDXAddr",  "64", "20", "Only">;
647def bdxaddr20only128  : BDXMode<"BDXAddr",  "64", "20", "Only128">;
648def bdxaddr20pair     : BDXMode<"BDXAddr",  "64", "20", "Pair">;
649def dynalloc12only    : BDXMode<"DynAlloc", "64", "12", "Only">;
650def laaddr12pair      : BDXMode<"LAAddr",   "64", "12", "Pair">;
651def laaddr20pair      : BDXMode<"LAAddr",   "64", "20", "Pair">;
652def bdladdr12onlylen4 : BDLMode<"BDLAddr",  "64", "12", "Only", "4">;
653def bdladdr12onlylen8 : BDLMode<"BDLAddr",  "64", "12", "Only", "8">;
654def bdraddr12only     : BDRMode<"BDRAddr",  "64", "12", "Only">;
655def bdvaddr12only     : BDVMode<            "64", "12">;
656
657//===----------------------------------------------------------------------===//
658// Miscellaneous
659//===----------------------------------------------------------------------===//
660
661// A 4-bit condition-code mask.
662def cond4 : PatLeaf<(i32 timm), [{ return (N->getZExtValue() < 16); }]>,
663            Operand<i32> {
664  let PrintMethod = "printCond4Operand";
665  let OperandType = "OPERAND_IMMEDIATE";
666}
667