1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the VE Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/VEMCTargetDesc.h" 14 #include "TargetInfo/VETargetInfo.h" 15 #include "VE.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDecoderOps.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/TargetRegistry.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "ve-disassembler" 26 27 typedef MCDisassembler::DecodeStatus DecodeStatus; 28 29 namespace { 30 31 /// A disassembler class for VE. 32 class VEDisassembler : public MCDisassembler { 33 public: 34 VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 35 : MCDisassembler(STI, Ctx) {} 36 virtual ~VEDisassembler() = default; 37 38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 39 ArrayRef<uint8_t> Bytes, uint64_t Address, 40 raw_ostream &CStream) const override; 41 }; 42 } // namespace 43 44 static MCDisassembler *createVEDisassembler(const Target &T, 45 const MCSubtargetInfo &STI, 46 MCContext &Ctx) { 47 return new VEDisassembler(STI, Ctx); 48 } 49 50 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEDisassembler() { 51 // Register the disassembler. 52 TargetRegistry::RegisterMCDisassembler(getTheVETarget(), 53 createVEDisassembler); 54 } 55 56 static const unsigned I32RegDecoderTable[] = { 57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, 58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, 59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, 60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, 61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34, 62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, 63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, 64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, 65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, 66 VE::SW63}; 67 68 static const unsigned I64RegDecoderTable[] = { 69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, 70 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, 71 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, 72 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, 73 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, 74 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, 75 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, 76 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, 77 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, 78 VE::SX63}; 79 80 static const unsigned F32RegDecoderTable[] = { 81 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, 82 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, 83 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, 84 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, 85 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34, 86 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, 87 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, 88 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, 89 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, 90 VE::SF63}; 91 92 static const unsigned F128RegDecoderTable[] = { 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7, 94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, 95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, 96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31}; 97 98 static const unsigned V64RegDecoderTable[] = { 99 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, 100 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, 101 VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, 102 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, 103 VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, 104 VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, 105 VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, 106 VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63}; 107 108 static const unsigned VMRegDecoderTable[] = { 109 VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, 110 VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, 111 VE::VM12, VE::VM13, VE::VM14, VE::VM15}; 112 113 static const unsigned VM512RegDecoderTable[] = {VE::VMP0, VE::VMP1, VE::VMP2, 114 VE::VMP3, VE::VMP4, VE::VMP5, 115 VE::VMP6, VE::VMP7}; 116 117 static const unsigned MiscRegDecoderTable[] = { 118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister, 119 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR, 120 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, 121 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, 122 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, 123 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, 124 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, 125 VE::PMC12, VE::PMC13, VE::PMC14}; 126 127 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const MCDisassembler *Decoder) { 130 if (RegNo > 63) 131 return MCDisassembler::Fail; 132 unsigned Reg = I32RegDecoderTable[RegNo]; 133 Inst.addOperand(MCOperand::createReg(Reg)); 134 return MCDisassembler::Success; 135 } 136 137 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, 138 uint64_t Address, 139 const MCDisassembler *Decoder) { 140 if (RegNo > 63) 141 return MCDisassembler::Fail; 142 unsigned Reg = I64RegDecoderTable[RegNo]; 143 Inst.addOperand(MCOperand::createReg(Reg)); 144 return MCDisassembler::Success; 145 } 146 147 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, 148 uint64_t Address, 149 const MCDisassembler *Decoder) { 150 if (RegNo > 63) 151 return MCDisassembler::Fail; 152 unsigned Reg = F32RegDecoderTable[RegNo]; 153 Inst.addOperand(MCOperand::createReg(Reg)); 154 return MCDisassembler::Success; 155 } 156 157 static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, 159 const MCDisassembler *Decoder) { 160 if (RegNo % 2 || RegNo > 63) 161 return MCDisassembler::Fail; 162 unsigned Reg = F128RegDecoderTable[RegNo / 2]; 163 Inst.addOperand(MCOperand::createReg(Reg)); 164 return MCDisassembler::Success; 165 } 166 167 static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, 169 const MCDisassembler *Decoder) { 170 unsigned Reg = VE::NoRegister; 171 if (RegNo == 255) 172 Reg = VE::VIX; 173 else if (RegNo > 63) 174 return MCDisassembler::Fail; 175 else 176 Reg = V64RegDecoderTable[RegNo]; 177 Inst.addOperand(MCOperand::createReg(Reg)); 178 return MCDisassembler::Success; 179 } 180 181 static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, 183 const MCDisassembler *Decoder) { 184 if (RegNo > 15) 185 return MCDisassembler::Fail; 186 unsigned Reg = VMRegDecoderTable[RegNo]; 187 Inst.addOperand(MCOperand::createReg(Reg)); 188 return MCDisassembler::Success; 189 } 190 191 static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, 192 uint64_t Address, 193 const MCDisassembler *Decoder) { 194 if (RegNo % 2 || RegNo > 15) 195 return MCDisassembler::Fail; 196 unsigned Reg = VM512RegDecoderTable[RegNo / 2]; 197 Inst.addOperand(MCOperand::createReg(Reg)); 198 return MCDisassembler::Success; 199 } 200 201 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, 203 const MCDisassembler *Decoder) { 204 if (RegNo > 30) 205 return MCDisassembler::Fail; 206 unsigned Reg = MiscRegDecoderTable[RegNo]; 207 if (Reg == VE::NoRegister) 208 return MCDisassembler::Fail; 209 Inst.addOperand(MCOperand::createReg(Reg)); 210 return MCDisassembler::Success; 211 } 212 213 static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address, 214 const MCDisassembler *Decoder); 215 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 216 const MCDisassembler *Decoder); 217 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 218 uint64_t Address, 219 const MCDisassembler *Decoder); 220 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 221 const MCDisassembler *Decoder); 222 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 223 uint64_t Address, 224 const MCDisassembler *Decoder); 225 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 226 const MCDisassembler *Decoder); 227 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 228 uint64_t Address, 229 const MCDisassembler *Decoder); 230 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, 231 uint64_t Address, 232 const MCDisassembler *Decoder); 233 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, 234 uint64_t Address, 235 const MCDisassembler *Decoder); 236 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn, 237 uint64_t Address, 238 const MCDisassembler *Decoder); 239 static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn, 240 uint64_t Address, 241 const MCDisassembler *Decoder); 242 static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address, 243 const MCDisassembler *Decoder); 244 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address, 245 const MCDisassembler *Decoder); 246 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 247 const MCDisassembler *Decoder); 248 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, 249 const MCDisassembler *Decoder); 250 static DecodeStatus DecodeSIMM32(MCInst &Inst, uint64_t insn, uint64_t Address, 251 const MCDisassembler *Decoder); 252 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn, 253 uint64_t Address, 254 const MCDisassembler *Decoder); 255 static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn, 256 uint64_t Address, 257 const MCDisassembler *Decoder); 258 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn, 259 uint64_t Address, 260 const MCDisassembler *Decoder); 261 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn, 262 uint64_t Address, 263 const MCDisassembler *Decoder); 264 265 #include "VEGenDisassemblerTables.inc" 266 267 /// Read four bytes from the ArrayRef and return 32 bit word. 268 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, 269 uint64_t &Size, uint64_t &Insn, 270 bool IsLittleEndian) { 271 // We want to read exactly 8 Bytes of data. 272 if (Bytes.size() < 8) { 273 Size = 0; 274 return MCDisassembler::Fail; 275 } 276 277 Insn = IsLittleEndian 278 ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | 279 ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) | 280 ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) | 281 ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56) 282 : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) | 283 ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) | 284 ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) | 285 ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56); 286 287 return MCDisassembler::Success; 288 } 289 290 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 291 ArrayRef<uint8_t> Bytes, 292 uint64_t Address, 293 raw_ostream &CStream) const { 294 uint64_t Insn; 295 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 296 DecodeStatus Result = 297 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian); 298 if (Result == MCDisassembler::Fail) 299 return MCDisassembler::Fail; 300 301 // Calling the auto-generated decoder function. 302 303 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI); 304 305 if (Result != MCDisassembler::Fail) { 306 Size = 8; 307 return Result; 308 } 309 310 return MCDisassembler::Fail; 311 } 312 313 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, 314 const MCDisassembler *Decoder); 315 316 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, 317 const MCDisassembler *Decoder) { 318 unsigned sy = fieldFromInstruction(insn, 40, 7); 319 bool cy = fieldFromInstruction(insn, 47, 1); 320 unsigned sz = fieldFromInstruction(insn, 32, 7); 321 bool cz = fieldFromInstruction(insn, 39, 1); 322 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 323 DecodeStatus status; 324 325 // Decode sz. 326 if (cz) { 327 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 328 if (status != MCDisassembler::Success) 329 return status; 330 } else { 331 MI.addOperand(MCOperand::createImm(0)); 332 } 333 334 // Decode sy. 335 if (cy) { 336 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 337 if (status != MCDisassembler::Success) 338 return status; 339 } else { 340 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 341 } 342 343 // Decode simm32. 344 MI.addOperand(MCOperand::createImm(simm32)); 345 346 return MCDisassembler::Success; 347 } 348 349 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, 350 const MCDisassembler *Decoder) { 351 unsigned sz = fieldFromInstruction(insn, 32, 7); 352 bool cz = fieldFromInstruction(insn, 39, 1); 353 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 354 DecodeStatus status; 355 356 // Decode sz. 357 if (cz) { 358 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 359 if (status != MCDisassembler::Success) 360 return status; 361 } else { 362 MI.addOperand(MCOperand::createImm(0)); 363 } 364 365 // Decode simm32. 366 MI.addOperand(MCOperand::createImm(simm32)); 367 368 return MCDisassembler::Success; 369 } 370 371 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, 372 const MCDisassembler *Decoder, bool isLoad, 373 DecodeFunc DecodeSX) { 374 unsigned sx = fieldFromInstruction(insn, 48, 7); 375 376 DecodeStatus status; 377 if (isLoad) { 378 status = DecodeSX(MI, sx, Address, Decoder); 379 if (status != MCDisassembler::Success) 380 return status; 381 } 382 383 status = DecodeASX(MI, insn, Address, Decoder); 384 if (status != MCDisassembler::Success) 385 return status; 386 387 if (!isLoad) { 388 status = DecodeSX(MI, sx, Address, Decoder); 389 if (status != MCDisassembler::Success) 390 return status; 391 } 392 return MCDisassembler::Success; 393 } 394 395 static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address, 396 const MCDisassembler *Decoder, bool isLoad, 397 DecodeFunc DecodeSX) { 398 unsigned sx = fieldFromInstruction(insn, 48, 7); 399 400 DecodeStatus status; 401 if (isLoad) { 402 status = DecodeSX(MI, sx, Address, Decoder); 403 if (status != MCDisassembler::Success) 404 return status; 405 } 406 407 status = DecodeAS(MI, insn, Address, Decoder); 408 if (status != MCDisassembler::Success) 409 return status; 410 411 if (!isLoad) { 412 status = DecodeSX(MI, sx, Address, Decoder); 413 if (status != MCDisassembler::Success) 414 return status; 415 } 416 return MCDisassembler::Success; 417 } 418 419 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 420 const MCDisassembler *Decoder) { 421 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); 422 } 423 424 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 425 uint64_t Address, 426 const MCDisassembler *Decoder) { 427 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); 428 } 429 430 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 431 const MCDisassembler *Decoder) { 432 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 433 } 434 435 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 436 uint64_t Address, 437 const MCDisassembler *Decoder) { 438 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); 439 } 440 441 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 442 const MCDisassembler *Decoder) { 443 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); 444 } 445 446 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 447 uint64_t Address, 448 const MCDisassembler *Decoder) { 449 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); 450 } 451 452 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, 453 uint64_t Address, 454 const MCDisassembler *Decoder) { 455 return DecodeMemAS(Inst, insn, Address, Decoder, true, 456 DecodeI64RegisterClass); 457 } 458 459 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, 460 uint64_t Address, 461 const MCDisassembler *Decoder) { 462 return DecodeMemAS(Inst, insn, Address, Decoder, false, 463 DecodeI64RegisterClass); 464 } 465 466 static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, 467 const MCDisassembler *Decoder, bool isImmOnly, 468 bool isUImm, DecodeFunc DecodeSX) { 469 unsigned sx = fieldFromInstruction(insn, 48, 7); 470 bool cy = fieldFromInstruction(insn, 47, 1); 471 unsigned sy = fieldFromInstruction(insn, 40, 7); 472 473 // Add $sx. 474 DecodeStatus status; 475 status = DecodeSX(MI, sx, Address, Decoder); 476 if (status != MCDisassembler::Success) 477 return status; 478 479 // Add $disp($sz). 480 status = DecodeAS(MI, insn, Address, Decoder); 481 if (status != MCDisassembler::Success) 482 return status; 483 484 // Add $sy. 485 if (cy && !isImmOnly) { 486 status = DecodeSX(MI, sy, Address, Decoder); 487 if (status != MCDisassembler::Success) 488 return status; 489 } else { 490 if (isUImm) 491 MI.addOperand(MCOperand::createImm(sy)); 492 else 493 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 494 } 495 496 // Add $sd. 497 status = DecodeSX(MI, sx, Address, Decoder); 498 if (status != MCDisassembler::Success) 499 return status; 500 501 return MCDisassembler::Success; 502 } 503 504 static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address, 505 const MCDisassembler *Decoder) { 506 return DecodeCAS(MI, insn, Address, Decoder, false, true, 507 DecodeI64RegisterClass); 508 } 509 510 static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address, 511 const MCDisassembler *Decoder) { 512 return DecodeCAS(MI, insn, Address, Decoder, false, true, 513 DecodeI32RegisterClass); 514 } 515 516 static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address, 517 const MCDisassembler *Decoder) { 518 return DecodeCAS(MI, insn, Address, Decoder, false, false, 519 DecodeI64RegisterClass); 520 } 521 522 static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address, 523 const MCDisassembler *Decoder) { 524 return DecodeCAS(MI, insn, Address, Decoder, false, false, 525 DecodeI32RegisterClass); 526 } 527 528 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 529 const MCDisassembler *Decoder) { 530 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 531 } 532 533 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, 534 const MCDisassembler *Decoder) { 535 uint64_t tgt = SignExtend64<7>(insn); 536 MI.addOperand(MCOperand::createImm(tgt)); 537 return MCDisassembler::Success; 538 } 539 540 static DecodeStatus DecodeSIMM32(MCInst &MI, uint64_t insn, uint64_t Address, 541 const MCDisassembler *Decoder) { 542 uint64_t tgt = SignExtend64<32>(insn); 543 MI.addOperand(MCOperand::createImm(tgt)); 544 return MCDisassembler::Success; 545 } 546 547 static bool isIntegerBCKind(MCInst &MI) { 548 549 #define BCm_kind(NAME) \ 550 case NAME##rri: \ 551 case NAME##rzi: \ 552 case NAME##iri: \ 553 case NAME##izi: \ 554 case NAME##rri_nt: \ 555 case NAME##rzi_nt: \ 556 case NAME##iri_nt: \ 557 case NAME##izi_nt: \ 558 case NAME##rri_t: \ 559 case NAME##rzi_t: \ 560 case NAME##iri_t: \ 561 case NAME##izi_t: 562 563 #define BCRm_kind(NAME) \ 564 case NAME##rr: \ 565 case NAME##ir: \ 566 case NAME##rr_nt: \ 567 case NAME##ir_nt: \ 568 case NAME##rr_t: \ 569 case NAME##ir_t: 570 571 { 572 using namespace llvm::VE; 573 switch (MI.getOpcode()) { 574 BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL) 575 BCRm_kind(BRCFW) return true; 576 } 577 } 578 #undef BCm_kind 579 580 return false; 581 } 582 583 // Decode CC Operand field. 584 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address, 585 const MCDisassembler *Decoder) { 586 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 587 return MCDisassembler::Success; 588 } 589 590 // Decode RD Operand field. 591 static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address, 592 const MCDisassembler *Decoder) { 593 MI.addOperand(MCOperand::createImm(VEValToRD(cf))); 594 return MCDisassembler::Success; 595 } 596 597 // Decode branch condition instruction and CCOperand field in it. 598 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn, 599 uint64_t Address, 600 const MCDisassembler *Decoder) { 601 unsigned cf = fieldFromInstruction(insn, 48, 4); 602 bool cy = fieldFromInstruction(insn, 47, 1); 603 unsigned sy = fieldFromInstruction(insn, 40, 7); 604 605 // Decode cf. 606 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 607 608 // Decode sy. 609 DecodeStatus status; 610 if (cy) { 611 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 612 if (status != MCDisassembler::Success) 613 return status; 614 } else { 615 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 616 } 617 618 // Decode MEMri. 619 return DecodeAS(MI, insn, Address, Decoder); 620 } 621 622 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, 623 uint64_t Address, 624 const MCDisassembler *Decoder) { 625 // Decode MEMri. 626 return DecodeAS(MI, insn, Address, Decoder); 627 } 628