1//===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// VE Subtarget features.
20//
21def FeatureEnableVPU
22  : SubtargetFeature<"vpu", "EnableVPU", "true",
23                     "Enable the VPU">;
24
25//===----------------------------------------------------------------------===//
26// Register File, Calling Conv, Instruction Descriptions
27//===----------------------------------------------------------------------===//
28
29include "VERegisterInfo.td"
30include "VECallingConv.td"
31include "VEInstrInfo.td"
32
33def VEInstrInfo : InstrInfo {}
34
35def VEAsmParser : AsmParser {
36  // Use both VE register name matcher to accept "S0~S63" register names
37  // and default register matcher to accept other registeres.
38  let AllowDuplicateRegisterNames = 1;
39  let ShouldEmitMatchRegisterAltName = 1;
40}
41
42//===----------------------------------------------------------------------===//
43// VE processors supported.
44//===----------------------------------------------------------------------===//
45
46class Proc<string Name, list<SubtargetFeature> Features>
47 : Processor<Name, NoItineraries, Features>;
48
49def : Proc<"generic", []>;
50
51//===----------------------------------------------------------------------===//
52// Declare the target which we are implementing
53//===----------------------------------------------------------------------===//
54
55def VEAsmWriter : AsmWriter {
56  string AsmWriterClassName  = "InstPrinter";
57  int PassSubtarget = 1;
58  int Variant = 0;
59}
60
61def VE : Target {
62  // Pull in Instruction Info:
63  let InstructionSet = VEInstrInfo;
64  let AssemblyParsers = [VEAsmParser];
65  let AssemblyWriters = [VEAsmWriter];
66  let AllowRegisterRenaming = 1;
67}
68