1//===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// SX-Aurora uses little endian, but instructions are encoded little bit
10// different manner.  Therefore, we need to tranlate the address of each
11// bitfield described in ISA documentation like below.
12//
13// ISA   |  InstrFormats.td
14// ---------------------------
15// 0-7   => 63-56
16// 8     => 55
17// 32-63 => 31-0
18
19//===----------------------------------------------------------------------===//
20// Instruction Format
21//===----------------------------------------------------------------------===//
22
23class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
24   : Instruction {
25  field bits<64> Inst;
26
27  let Namespace = "VE";
28  let Size = 8;
29
30  bits<8> op;
31  let Inst{63-56} = op;
32
33  dag OutOperandList = outs;
34  dag InOperandList = ins;
35  let AsmString   = asmstr;
36  let Pattern = pattern;
37
38  bits<1> VE_Vector = 0;
39  bits<1> VE_VLInUse = 0;
40  bits<3> VE_VLIndex = 0;
41  bits<1> VE_VLWithMask = 0;
42
43  /// These fields correspond to the fields in VEInstrInfo.h.  Any changes to
44  /// these must be reflected there!  See comments there for what these are.
45  ///
46  /// VLIndex is the index of VL register in MI's operands.  The HW instruction
47  /// doesn't have that field, but we add is in MI for the ease of optimization.
48  /// For example, the index of VL of (VST $sy, $sz, $sx, $vl) is 3 (beginning
49  /// from 0), and the index of VL of (VST $sy, $sz, $sx, $vm, $vl) is 4.  We
50  /// define vector instructions hierarchically, so use VE_VLIndex which is
51  /// defined by the type of instruction and VE_VLWithMask which is defined
52  /// whether the insturction use mask or not.
53  let TSFlags{0}   = VE_Vector;
54  let TSFlags{1}   = VE_VLInUse;
55  let TSFlags{4-2} = !add(VE_VLIndex, VE_VLWithMask);
56
57  let DecoderNamespace = "VE";
58  field bits<64> SoftFail = 0;
59}
60
61//-----------------------------------------------------------------------------
62// Section 5.1 RM Type
63//
64// RM type has sx, sy, sz, and imm32.
65// The effective address is generated by sz + sy + imm32.
66//-----------------------------------------------------------------------------
67
68class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
69   : InstVE<outs, ins, asmstr, pattern> {
70  bits<1>  cx = 0;
71  bits<7>  sx;
72  bits<1>  cy = 1;
73  bits<7>  sz;      // defines sz prior to sy to assign from sz
74  bits<7>  sy;
75  bits<1>  cz = 1;
76  bits<32> imm32;
77  let op = opVal;
78  let Inst{55} = cx;
79  let Inst{54-48} = sx;
80  let Inst{47} = cy;
81  let Inst{46-40} = sy;
82  let Inst{39} = cz;
83  let Inst{38-32} = sz;
84  let Inst{31-0}  = imm32;
85}
86
87//-----------------------------------------------------------------------------
88// Section 5.2 RRM Type
89//
90// RRM type is identical to RM, but the effective address is generated
91// by sz + imm32.  The sy field is used by other purposes.
92//-----------------------------------------------------------------------------
93
94class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
95          list<dag> pattern = []>
96   : RM<opVal, outs, ins, asmstr, pattern>;
97
98// RRMHM type is to load/store host memory
99// It is similar to RRM and not use sy.
100class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
101            list<dag> pattern = []>
102   : RRM<opVal, outs, ins, asmstr, pattern> {
103  bits<2> ry = 0;
104  let cy = 0;
105  let sy{6-2} = 0;
106  let sy{1-0} = ry;
107}
108
109//-----------------------------------------------------------------------------
110// Section 5.3 CF Type
111//
112// CF type is used for control flow.
113//-----------------------------------------------------------------------------
114
115class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
116   : InstVE<outs, ins, asmstr, pattern> {
117  bits<1>  cx = 0;
118  bits<1>  cx2 = 0;
119  bits<2>  bpf = 0;
120  bits<4>  cf;
121  bits<1>  cy = 1;
122  bits<7>  sy;
123  bits<1>  cz = 1;
124  bits<7>  sz;
125  bits<32> imm32;
126  let op = opVal;
127  let Inst{55} = cx;
128  let Inst{54} = cx2;
129  let Inst{53-52} = bpf;
130  let Inst{51-48} = cf;
131  let Inst{47} = cy;
132  let Inst{46-40} = sy;
133  let Inst{39} = cz;
134  let Inst{38-32} = sz;
135  let Inst{31-0}  = imm32;
136}
137
138//-----------------------------------------------------------------------------
139// Section 5.4 RR Type
140//
141// RR type is for generic arithmetic instructions.
142//-----------------------------------------------------------------------------
143
144class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
145   : InstVE<outs, ins, asmstr, pattern> {
146  bits<1>  cx = 0;
147  bits<7>  sx;
148  bits<1>  cy = 1;
149  bits<7>  sy;
150  bits<1>  cz = 1;
151  bits<7>  sz;          // m field places at the top sz field
152  bits<8>  vx = 0;
153  bits<8>  vz = 0;
154  bits<1> cw = 0;
155  bits<1> cw2 = 0;
156  bits<4> cfw = 0;
157  let op = opVal;
158  let Inst{55} = cx;
159  let Inst{54-48} = sx;
160  let Inst{47} = cy;
161  let Inst{46-40} = sy;
162  let Inst{39} = cz;
163  let Inst{38-32} = sz;
164  let Inst{31-24} = vx;
165  let Inst{23-16} = 0;
166  let Inst{15-8} = vz;
167  let Inst{7} = cw;
168  let Inst{6} = cw2;
169  let Inst{5-4} = 0;
170  let Inst{3-0} = cfw;
171}
172
173// RRFENCE type is special RR type for a FENCE instruction.
174class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr,
175              list<dag> pattern = []>
176   : InstVE<outs, ins, asmstr, pattern> {
177  bits<1> avo = 0;
178  bits<1> lf = 0;
179  bits<1> sf = 0;
180  bits<1> c2 = 0;
181  bits<1> c1 = 0;
182  bits<1> c0 = 0;
183  let op = opVal;
184  let Inst{55} = avo;
185  let Inst{54-50} = 0;
186  let Inst{49} = lf;
187  let Inst{48} = sf;
188  let Inst{47-43} = 0;
189  let Inst{42} = c2;
190  let Inst{41} = c1;
191  let Inst{40} = c0;
192  let Inst{39-0} = 0;
193}
194
195//-----------------------------------------------------------------------------
196// Section 5.5 RW Type
197//-----------------------------------------------------------------------------
198
199//-----------------------------------------------------------------------------
200// Section 5.6 RVM Type
201//
202// RVM type is for vector transfer instructions.
203//-----------------------------------------------------------------------------
204
205class RVM<bits<8>opVal, dag outs, dag ins, string asmstr,
206          list<dag> pattern = []>
207   : InstVE<outs, ins, asmstr, pattern> {
208  bits<1>  cx = 0;
209  bits<1>  vc = 0;
210  bits<1>  cs = 0;
211  bits<4>  m = 0;
212  bits<1>  cy = 1;
213  bits<7>  sy;
214  bits<1>  cz = 1;
215  bits<7>  sz;
216  bits<8>  vx;
217  bits<8>  vy = 0;
218  bits<7>  sw = 0;
219  let op = opVal;
220  let Inst{55} = cx;
221  let Inst{54} = vc;
222  let Inst{53} = cs;
223  let Inst{52} = 0;
224  let Inst{51-48} = m;
225  let Inst{47} = cy;
226  let Inst{46-40} = sy;
227  let Inst{39} = cz;
228  let Inst{38-32} = sz;
229  let Inst{31-24} = vx;
230  let Inst{23-16} = vy;
231  let Inst{15-8} = 0;
232  let Inst{7} = 0;
233  let Inst{6-0} = sw;
234
235  let VE_Vector = 1;
236}
237
238//-----------------------------------------------------------------------------
239// Section 5.7 RV Type
240//
241// RV type is for vector instructions.
242//-----------------------------------------------------------------------------
243
244class RV<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
245   : InstVE<outs, ins, asmstr, pattern> {
246  bits<1>  cx = 0;
247  bits<1>  cx2 = 0;
248  bits<1>  cs = 0;
249  bits<1>  cs2 = 0;
250  bits<4>  m = 0;
251  bits<1>  cy = 1;
252  bits<7>  sy;
253  bits<1>  cz = 0;
254  bits<7>  sz = 0;
255  bits<8>  vx = 0;
256  bits<8>  vy = 0;
257  bits<8>  vz = 0;
258  bits<8>  vw = 0;
259  let op = opVal;
260  let Inst{55} = cx;
261  let Inst{54} = cx2;
262  let Inst{53} = cs;
263  let Inst{52} = cs2;
264  let Inst{51-48} = m;
265  let Inst{47} = cy;
266  let Inst{46-40} = sy;
267  let Inst{39} = cz;
268  let Inst{38-32} = sz;
269  let Inst{31-24} = vx;
270  let Inst{23-16} = vy;
271  let Inst{15-8} = vz;
272  let Inst{7-0} = vw;
273
274  let VE_Vector = 1;
275}
276
277// Pseudo instructions.
278class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []>
279   : InstVE<outs, ins, asmstr, pattern> {
280  let isCodeGenOnly = 1;
281  let isPseudo = 1;
282}
283