1/// Pattern Matchings for VEL intrinsic instructions.
2
3/// Intrinsic patterns written by hand.
4
5// Pack patterns.
6def : Pat<(i64 (int_ve_vl_pack_f32p ADDRrii:$addr0, ADDRrii:$addr1)),
7          (ORrr (f2l (LDUrii MEMrii:$addr0)),
8                (i2l (LDLZXrii MEMrii:$addr1)))>;
9
10def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
11          (MULULrr
12            (i2l (LDLZXrii MEMrii:$addr)),
13            (LEASLrii (ANDrm (LEAzii 0, 0, (LO32 (i64 0x0000000100000001))),
14                             !add(32, 64)), 0,
15                      (HI32 (i64 0x0000000100000001))))>;
16
17// The extract/insert patterns.
18def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)),
19          (EXTRACT_SUBREG v512i1:$vm, sub_vm_even)>;
20
21def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)),
22          (EXTRACT_SUBREG v512i1:$vm, sub_vm_odd)>;
23
24def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)),
25          (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even)>;
26
27def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
28          (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
29
30// VMRG patterns.
31def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
32          (VMRGWrvml (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl)>;
33def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm,
34                                  v256f64:$pt, i32:$vl),
35          (VMRGWrvml_v (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl,
36                       v256f64:$pt)>;
37
38// VMV patterns.
39def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl),
40          (VMVrvl (i2l i32:$sy), v256f64:$vz, i32:$vl)>;
41def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl),
42          (VMVrvl_v (i2l i32:$sy), v256f64:$vz, i32:$vl, v256f64:$pt)>;
43def : Pat<(int_ve_vl_vmv_vsvmvl i32:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt,
44                                i32:$vl),
45          (VMVrvml_v (i2l i32:$sy), v256f64:$vz, v256i1:$vm, i32:$vl,
46                     v256f64:$pt)>;
47
48// LSV patterns.
49def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
50          (LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;
51
52// LVS patterns.
53def : Pat<(int_ve_vl_lvsl_svs v256f64:$vx, i32:$sy),
54          (LVSvr v256f64:$vx, (i2l i32:$sy))>;
55def : Pat<(int_ve_vl_lvsd_svs v256f64:$vx, i32:$sy),
56          (LVSvr v256f64:$vx, (i2l i32:$sy))>;
57def : Pat<(int_ve_vl_lvss_svs v256f64:$vx, i32:$sy),
58          (l2f (LVSvr v256f64:$vx, (i2l i32:$sy)))>;
59
60/// Intrinsic patterns automatically generated.
61include "VEInstrIntrinsicVL.gen.td"
62