1//===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the VE register file 11//===----------------------------------------------------------------------===// 12 13class VEReg<bits<7> Enc, string n> : Register<n> { 14 let HWEncoding{15-7} = 0; 15 let HWEncoding{6-0} = Enc; 16 let Namespace = "VE"; 17} 18 19// Registers are identified with 7-bit ID numbers. 20// R - 64-bit integer or floating-point registers 21class R<bits<7> Enc, string n, list<Register> subregs = [], 22 list<Register> aliases = []>: VEReg<Enc, n> { 23 let SubRegs = subregs; 24 let Aliases = aliases; 25} 26 27// Generic integer registers - 64 bits wide 28foreach I = 0-63 in 29 def SX#I : R<I, "S"#I, []>, 30 DwarfRegNum<[I]>; 31 32// Register classes. 33// 34// The register order is defined in terms of the preferred 35// allocation order. 36def I64 : RegisterClass<"VE", [i64], 64, 37 (sequence "SX%u", 0, 63)>; 38