1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file provides WebAssembly-specific target descriptions. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 16 17 #include "../WebAssemblySubtarget.h" 18 #include "llvm/BinaryFormat/Wasm.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/Support/DataTypes.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCAsmBackend; 26 class MCCodeEmitter; 27 class MCInstrInfo; 28 class MCObjectTargetWriter; 29 class Triple; 30 31 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); 32 33 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); 34 35 std::unique_ptr<MCObjectTargetWriter> 36 createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten); 37 38 namespace WebAssembly { 39 enum OperandType { 40 /// Basic block label in a branch construct. 41 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET, 42 /// Local index. 43 OPERAND_LOCAL, 44 /// Global index. 45 OPERAND_GLOBAL, 46 /// 32-bit integer immediates. 47 OPERAND_I32IMM, 48 /// 64-bit integer immediates. 49 OPERAND_I64IMM, 50 /// 32-bit floating-point immediates. 51 OPERAND_F32IMM, 52 /// 64-bit floating-point immediates. 53 OPERAND_F64IMM, 54 /// 8-bit vector lane immediate 55 OPERAND_VEC_I8IMM, 56 /// 16-bit vector lane immediate 57 OPERAND_VEC_I16IMM, 58 /// 32-bit vector lane immediate 59 OPERAND_VEC_I32IMM, 60 /// 64-bit vector lane immediate 61 OPERAND_VEC_I64IMM, 62 /// 32-bit unsigned function indices. 63 OPERAND_FUNCTION32, 64 /// 32-bit unsigned memory offsets. 65 OPERAND_OFFSET32, 66 /// 64-bit unsigned memory offsets. 67 OPERAND_OFFSET64, 68 /// p2align immediate for load and store address alignment. 69 OPERAND_P2ALIGN, 70 /// signature immediate for block/loop. 71 OPERAND_SIGNATURE, 72 /// type signature immediate for call_indirect. 73 OPERAND_TYPEINDEX, 74 /// Tag index. 75 OPERAND_TAG, 76 /// A list of branch targets for br_list. 77 OPERAND_BRLIST, 78 /// 32-bit unsigned table number. 79 OPERAND_TABLE, 80 }; 81 } // end namespace WebAssembly 82 83 namespace WebAssemblyII { 84 85 /// Target Operand Flag enum. 86 enum TOF { 87 MO_NO_FLAG = 0, 88 89 // On a symbol operand this indicates that the immediate is a wasm global 90 // index. The value of the wasm global will be set to the symbol address at 91 // runtime. This adds a level of indirection similar to the GOT on native 92 // platforms. 93 MO_GOT, 94 95 // Same as MO_GOT but the address stored in the global is a TLS address. 96 MO_GOT_TLS, 97 98 // On a symbol operand this indicates that the immediate is the symbol 99 // address relative the __memory_base wasm global. 100 // Only applicable to data symbols. 101 MO_MEMORY_BASE_REL, 102 103 // On a symbol operand this indicates that the immediate is the symbol 104 // address relative the __tls_base wasm global. 105 // Only applicable to data symbols. 106 MO_TLS_BASE_REL, 107 108 // On a symbol operand this indicates that the immediate is the symbol 109 // address relative the __table_base wasm global. 110 // Only applicable to function symbols. 111 MO_TABLE_BASE_REL, 112 }; 113 114 } // end namespace WebAssemblyII 115 116 } // end namespace llvm 117 118 // Defines symbolic names for WebAssembly registers. This defines a mapping from 119 // register name to register number. 120 // 121 #define GET_REGINFO_ENUM 122 #include "WebAssemblyGenRegisterInfo.inc" 123 124 // Defines symbolic names for the WebAssembly instructions. 125 // 126 #define GET_INSTRINFO_ENUM 127 #define GET_INSTRINFO_MC_HELPER_DECLS 128 #include "WebAssemblyGenInstrInfo.inc" 129 130 namespace llvm { 131 namespace WebAssembly { 132 133 /// Instruction opcodes emitted via means other than CodeGen. 134 static const unsigned Nop = 0x01; 135 static const unsigned End = 0x0b; 136 137 /// Return the default p2align value for a load or store with the given opcode. 138 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { 139 switch (Opc) { 140 #define WASM_LOAD_STORE(NAME) \ 141 case WebAssembly::NAME##_A32: \ 142 case WebAssembly::NAME##_A64: \ 143 case WebAssembly::NAME##_A32_S: \ 144 case WebAssembly::NAME##_A64_S: 145 WASM_LOAD_STORE(LOAD8_S_I32) 146 WASM_LOAD_STORE(LOAD8_U_I32) 147 WASM_LOAD_STORE(LOAD8_S_I64) 148 WASM_LOAD_STORE(LOAD8_U_I64) 149 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32) 150 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64) 151 WASM_LOAD_STORE(STORE8_I32) 152 WASM_LOAD_STORE(STORE8_I64) 153 WASM_LOAD_STORE(ATOMIC_STORE8_I32) 154 WASM_LOAD_STORE(ATOMIC_STORE8_I64) 155 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32) 156 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64) 157 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32) 158 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64) 159 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32) 160 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64) 161 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32) 162 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64) 163 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32) 164 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64) 165 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32) 166 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64) 167 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32) 168 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64) 169 WASM_LOAD_STORE(LOAD8_SPLAT) 170 WASM_LOAD_STORE(LOAD_LANE_I8x16) 171 WASM_LOAD_STORE(STORE_LANE_I8x16) 172 return 0; 173 WASM_LOAD_STORE(LOAD16_S_I32) 174 WASM_LOAD_STORE(LOAD16_U_I32) 175 WASM_LOAD_STORE(LOAD16_S_I64) 176 WASM_LOAD_STORE(LOAD16_U_I64) 177 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32) 178 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64) 179 WASM_LOAD_STORE(STORE16_I32) 180 WASM_LOAD_STORE(STORE16_I64) 181 WASM_LOAD_STORE(ATOMIC_STORE16_I32) 182 WASM_LOAD_STORE(ATOMIC_STORE16_I64) 183 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32) 184 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64) 185 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32) 186 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64) 187 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32) 188 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64) 189 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32) 190 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64) 191 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32) 192 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64) 193 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32) 194 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64) 195 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32) 196 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64) 197 WASM_LOAD_STORE(LOAD16_SPLAT) 198 WASM_LOAD_STORE(LOAD_LANE_I16x8) 199 WASM_LOAD_STORE(STORE_LANE_I16x8) 200 return 1; 201 WASM_LOAD_STORE(LOAD_I32) 202 WASM_LOAD_STORE(LOAD_F32) 203 WASM_LOAD_STORE(STORE_I32) 204 WASM_LOAD_STORE(STORE_F32) 205 WASM_LOAD_STORE(LOAD32_S_I64) 206 WASM_LOAD_STORE(LOAD32_U_I64) 207 WASM_LOAD_STORE(STORE32_I64) 208 WASM_LOAD_STORE(ATOMIC_LOAD_I32) 209 WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64) 210 WASM_LOAD_STORE(ATOMIC_STORE_I32) 211 WASM_LOAD_STORE(ATOMIC_STORE32_I64) 212 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32) 213 WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64) 214 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32) 215 WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64) 216 WASM_LOAD_STORE(ATOMIC_RMW_AND_I32) 217 WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64) 218 WASM_LOAD_STORE(ATOMIC_RMW_OR_I32) 219 WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64) 220 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32) 221 WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64) 222 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32) 223 WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64) 224 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32) 225 WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64) 226 WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY) 227 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32) 228 WASM_LOAD_STORE(LOAD32_SPLAT) 229 WASM_LOAD_STORE(LOAD_ZERO_I32x4) 230 WASM_LOAD_STORE(LOAD_LANE_I32x4) 231 WASM_LOAD_STORE(STORE_LANE_I32x4) 232 return 2; 233 WASM_LOAD_STORE(LOAD_I64) 234 WASM_LOAD_STORE(LOAD_F64) 235 WASM_LOAD_STORE(STORE_I64) 236 WASM_LOAD_STORE(STORE_F64) 237 WASM_LOAD_STORE(ATOMIC_LOAD_I64) 238 WASM_LOAD_STORE(ATOMIC_STORE_I64) 239 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64) 240 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64) 241 WASM_LOAD_STORE(ATOMIC_RMW_AND_I64) 242 WASM_LOAD_STORE(ATOMIC_RMW_OR_I64) 243 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64) 244 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64) 245 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64) 246 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64) 247 WASM_LOAD_STORE(LOAD64_SPLAT) 248 WASM_LOAD_STORE(LOAD_EXTEND_S_I16x8) 249 WASM_LOAD_STORE(LOAD_EXTEND_U_I16x8) 250 WASM_LOAD_STORE(LOAD_EXTEND_S_I32x4) 251 WASM_LOAD_STORE(LOAD_EXTEND_U_I32x4) 252 WASM_LOAD_STORE(LOAD_EXTEND_S_I64x2) 253 WASM_LOAD_STORE(LOAD_EXTEND_U_I64x2) 254 WASM_LOAD_STORE(LOAD_ZERO_I64x2) 255 WASM_LOAD_STORE(LOAD_LANE_I64x2) 256 WASM_LOAD_STORE(STORE_LANE_I64x2) 257 return 3; 258 WASM_LOAD_STORE(LOAD_V128) 259 WASM_LOAD_STORE(STORE_V128) 260 return 4; 261 default: 262 return -1; 263 } 264 #undef WASM_LOAD_STORE 265 } 266 267 inline unsigned GetDefaultP2Align(unsigned Opc) { 268 auto Align = GetDefaultP2AlignAny(Opc); 269 if (Align == -1U) { 270 llvm_unreachable("Only loads and stores have p2align values"); 271 } 272 return Align; 273 } 274 275 inline bool isArgument(unsigned Opc) { 276 switch (Opc) { 277 case WebAssembly::ARGUMENT_i32: 278 case WebAssembly::ARGUMENT_i32_S: 279 case WebAssembly::ARGUMENT_i64: 280 case WebAssembly::ARGUMENT_i64_S: 281 case WebAssembly::ARGUMENT_f32: 282 case WebAssembly::ARGUMENT_f32_S: 283 case WebAssembly::ARGUMENT_f64: 284 case WebAssembly::ARGUMENT_f64_S: 285 case WebAssembly::ARGUMENT_v16i8: 286 case WebAssembly::ARGUMENT_v16i8_S: 287 case WebAssembly::ARGUMENT_v8i16: 288 case WebAssembly::ARGUMENT_v8i16_S: 289 case WebAssembly::ARGUMENT_v4i32: 290 case WebAssembly::ARGUMENT_v4i32_S: 291 case WebAssembly::ARGUMENT_v2i64: 292 case WebAssembly::ARGUMENT_v2i64_S: 293 case WebAssembly::ARGUMENT_v4f32: 294 case WebAssembly::ARGUMENT_v4f32_S: 295 case WebAssembly::ARGUMENT_v2f64: 296 case WebAssembly::ARGUMENT_v2f64_S: 297 case WebAssembly::ARGUMENT_funcref: 298 case WebAssembly::ARGUMENT_funcref_S: 299 case WebAssembly::ARGUMENT_externref: 300 case WebAssembly::ARGUMENT_externref_S: 301 return true; 302 default: 303 return false; 304 } 305 } 306 307 inline bool isCopy(unsigned Opc) { 308 switch (Opc) { 309 case WebAssembly::COPY_I32: 310 case WebAssembly::COPY_I32_S: 311 case WebAssembly::COPY_I64: 312 case WebAssembly::COPY_I64_S: 313 case WebAssembly::COPY_F32: 314 case WebAssembly::COPY_F32_S: 315 case WebAssembly::COPY_F64: 316 case WebAssembly::COPY_F64_S: 317 case WebAssembly::COPY_V128: 318 case WebAssembly::COPY_V128_S: 319 case WebAssembly::COPY_FUNCREF: 320 case WebAssembly::COPY_FUNCREF_S: 321 case WebAssembly::COPY_EXTERNREF: 322 case WebAssembly::COPY_EXTERNREF_S: 323 return true; 324 default: 325 return false; 326 } 327 } 328 329 inline bool isTee(unsigned Opc) { 330 switch (Opc) { 331 case WebAssembly::TEE_I32: 332 case WebAssembly::TEE_I32_S: 333 case WebAssembly::TEE_I64: 334 case WebAssembly::TEE_I64_S: 335 case WebAssembly::TEE_F32: 336 case WebAssembly::TEE_F32_S: 337 case WebAssembly::TEE_F64: 338 case WebAssembly::TEE_F64_S: 339 case WebAssembly::TEE_V128: 340 case WebAssembly::TEE_V128_S: 341 case WebAssembly::TEE_FUNCREF: 342 case WebAssembly::TEE_FUNCREF_S: 343 case WebAssembly::TEE_EXTERNREF: 344 case WebAssembly::TEE_EXTERNREF_S: 345 return true; 346 default: 347 return false; 348 } 349 } 350 351 inline bool isCallDirect(unsigned Opc) { 352 switch (Opc) { 353 case WebAssembly::CALL: 354 case WebAssembly::CALL_S: 355 case WebAssembly::RET_CALL: 356 case WebAssembly::RET_CALL_S: 357 return true; 358 default: 359 return false; 360 } 361 } 362 363 inline bool isCallIndirect(unsigned Opc) { 364 switch (Opc) { 365 case WebAssembly::CALL_INDIRECT: 366 case WebAssembly::CALL_INDIRECT_S: 367 case WebAssembly::RET_CALL_INDIRECT: 368 case WebAssembly::RET_CALL_INDIRECT_S: 369 return true; 370 default: 371 return false; 372 } 373 } 374 375 inline bool isBrTable(const MachineInstr &MI) { 376 switch (MI.getOpcode()) { 377 case WebAssembly::BR_TABLE_I32: 378 case WebAssembly::BR_TABLE_I32_S: 379 case WebAssembly::BR_TABLE_I64: 380 case WebAssembly::BR_TABLE_I64_S: 381 return true; 382 default: 383 return false; 384 } 385 } 386 387 inline bool isMarker(unsigned Opc) { 388 switch (Opc) { 389 case WebAssembly::BLOCK: 390 case WebAssembly::BLOCK_S: 391 case WebAssembly::END_BLOCK: 392 case WebAssembly::END_BLOCK_S: 393 case WebAssembly::LOOP: 394 case WebAssembly::LOOP_S: 395 case WebAssembly::END_LOOP: 396 case WebAssembly::END_LOOP_S: 397 case WebAssembly::TRY: 398 case WebAssembly::TRY_S: 399 case WebAssembly::END_TRY: 400 case WebAssembly::END_TRY_S: 401 return true; 402 default: 403 return false; 404 } 405 } 406 407 inline bool isCatch(unsigned Opc) { 408 switch (Opc) { 409 case WebAssembly::CATCH: 410 case WebAssembly::CATCH_S: 411 case WebAssembly::CATCH_ALL: 412 case WebAssembly::CATCH_ALL_S: 413 return true; 414 default: 415 return false; 416 } 417 } 418 419 inline bool isLocalGet(unsigned Opc) { 420 switch (Opc) { 421 case WebAssembly::LOCAL_GET_I32: 422 case WebAssembly::LOCAL_GET_I32_S: 423 case WebAssembly::LOCAL_GET_I64: 424 case WebAssembly::LOCAL_GET_I64_S: 425 case WebAssembly::LOCAL_GET_F32: 426 case WebAssembly::LOCAL_GET_F32_S: 427 case WebAssembly::LOCAL_GET_F64: 428 case WebAssembly::LOCAL_GET_F64_S: 429 case WebAssembly::LOCAL_GET_V128: 430 case WebAssembly::LOCAL_GET_V128_S: 431 case WebAssembly::LOCAL_GET_FUNCREF: 432 case WebAssembly::LOCAL_GET_FUNCREF_S: 433 case WebAssembly::LOCAL_GET_EXTERNREF: 434 case WebAssembly::LOCAL_GET_EXTERNREF_S: 435 return true; 436 default: 437 return false; 438 } 439 } 440 441 inline bool isLocalSet(unsigned Opc) { 442 switch (Opc) { 443 case WebAssembly::LOCAL_SET_I32: 444 case WebAssembly::LOCAL_SET_I32_S: 445 case WebAssembly::LOCAL_SET_I64: 446 case WebAssembly::LOCAL_SET_I64_S: 447 case WebAssembly::LOCAL_SET_F32: 448 case WebAssembly::LOCAL_SET_F32_S: 449 case WebAssembly::LOCAL_SET_F64: 450 case WebAssembly::LOCAL_SET_F64_S: 451 case WebAssembly::LOCAL_SET_V128: 452 case WebAssembly::LOCAL_SET_V128_S: 453 case WebAssembly::LOCAL_SET_FUNCREF: 454 case WebAssembly::LOCAL_SET_FUNCREF_S: 455 case WebAssembly::LOCAL_SET_EXTERNREF: 456 case WebAssembly::LOCAL_SET_EXTERNREF_S: 457 return true; 458 default: 459 return false; 460 } 461 } 462 463 inline bool isLocalTee(unsigned Opc) { 464 switch (Opc) { 465 case WebAssembly::LOCAL_TEE_I32: 466 case WebAssembly::LOCAL_TEE_I32_S: 467 case WebAssembly::LOCAL_TEE_I64: 468 case WebAssembly::LOCAL_TEE_I64_S: 469 case WebAssembly::LOCAL_TEE_F32: 470 case WebAssembly::LOCAL_TEE_F32_S: 471 case WebAssembly::LOCAL_TEE_F64: 472 case WebAssembly::LOCAL_TEE_F64_S: 473 case WebAssembly::LOCAL_TEE_V128: 474 case WebAssembly::LOCAL_TEE_V128_S: 475 case WebAssembly::LOCAL_TEE_FUNCREF: 476 case WebAssembly::LOCAL_TEE_FUNCREF_S: 477 case WebAssembly::LOCAL_TEE_EXTERNREF: 478 case WebAssembly::LOCAL_TEE_EXTERNREF_S: 479 return true; 480 default: 481 return false; 482 } 483 } 484 485 } // end namespace WebAssembly 486 } // end namespace llvm 487 488 #endif 489