1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly SIMD operand code-gen constructs. 11/// 12//===----------------------------------------------------------------------===// 13 14// Instructions using the SIMD opcode prefix and requiring one of the SIMD 15// feature predicates. 16multiclass ABSTRACT_SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 17 list<dag> pattern_r, string asmstr_r, 18 string asmstr_s, bits<32> simdop, 19 Predicate simd_level> { 20 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 21 !if(!ge(simdop, 0x100), 22 !or(0xfd0000, !and(0xffff, simdop)), 23 !or(0xfd00, !and(0xff, simdop)))>, 24 Requires<[simd_level]>; 25} 26 27multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 28 list<dag> pattern_r, string asmstr_r = "", 29 string asmstr_s = "", bits<32> simdop = -1> { 30 defm "" : ABSTRACT_SIMD_I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, 31 asmstr_s, simdop, HasSIMD128>; 32} 33 34multiclass RELAXED_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 35 list<dag> pattern_r, string asmstr_r = "", 36 string asmstr_s = "", bits<32> simdop = -1> { 37 defm "" : ABSTRACT_SIMD_I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, 38 asmstr_s, simdop, HasRelaxedSIMD>; 39} 40 41 42defm "" : ARGUMENT<V128, v16i8>; 43defm "" : ARGUMENT<V128, v8i16>; 44defm "" : ARGUMENT<V128, v4i32>; 45defm "" : ARGUMENT<V128, v2i64>; 46defm "" : ARGUMENT<V128, v4f32>; 47defm "" : ARGUMENT<V128, v2f64>; 48 49// Constrained immediate argument types 50foreach SIZE = [8, 16] in 51def ImmI#SIZE : ImmLeaf<i32, 52 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));" 53>; 54foreach SIZE = [2, 4, 8, 16, 32] in 55def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; 56 57class Vec { 58 ValueType vt; 59 ValueType int_vt; 60 ValueType lane_vt; 61 WebAssemblyRegClass lane_rc; 62 int lane_bits; 63 ImmLeaf lane_idx; 64 SDPatternOperator lane_load; 65 PatFrag splat; 66 string prefix; 67 Vec split; 68} 69 70def I8x16 : Vec { 71 let vt = v16i8; 72 let int_vt = vt; 73 let lane_vt = i32; 74 let lane_rc = I32; 75 let lane_bits = 8; 76 let lane_idx = LaneIdx16; 77 let lane_load = extloadi8; 78 let splat = PatFrag<(ops node:$x), (v16i8 (splat_vector (i8 $x)))>; 79 let prefix = "i8x16"; 80} 81 82def I16x8 : Vec { 83 let vt = v8i16; 84 let int_vt = vt; 85 let lane_vt = i32; 86 let lane_rc = I32; 87 let lane_bits = 16; 88 let lane_idx = LaneIdx8; 89 let lane_load = extloadi16; 90 let splat = PatFrag<(ops node:$x), (v8i16 (splat_vector (i16 $x)))>; 91 let prefix = "i16x8"; 92 let split = I8x16; 93} 94 95def I32x4 : Vec { 96 let vt = v4i32; 97 let int_vt = vt; 98 let lane_vt = i32; 99 let lane_rc = I32; 100 let lane_bits = 32; 101 let lane_idx = LaneIdx4; 102 let lane_load = load; 103 let splat = PatFrag<(ops node:$x), (v4i32 (splat_vector (i32 $x)))>; 104 let prefix = "i32x4"; 105 let split = I16x8; 106} 107 108def I64x2 : Vec { 109 let vt = v2i64; 110 let int_vt = vt; 111 let lane_vt = i64; 112 let lane_rc = I64; 113 let lane_bits = 64; 114 let lane_idx = LaneIdx2; 115 let lane_load = load; 116 let splat = PatFrag<(ops node:$x), (v2i64 (splat_vector (i64 $x)))>; 117 let prefix = "i64x2"; 118 let split = I32x4; 119} 120 121def F32x4 : Vec { 122 let vt = v4f32; 123 let int_vt = v4i32; 124 let lane_vt = f32; 125 let lane_rc = F32; 126 let lane_bits = 32; 127 let lane_idx = LaneIdx4; 128 let lane_load = load; 129 let splat = PatFrag<(ops node:$x), (v4f32 (splat_vector (f32 $x)))>; 130 let prefix = "f32x4"; 131} 132 133def F64x2 : Vec { 134 let vt = v2f64; 135 let int_vt = v2i64; 136 let lane_vt = f64; 137 let lane_rc = F64; 138 let lane_bits = 64; 139 let lane_idx = LaneIdx2; 140 let lane_load = load; 141 let splat = PatFrag<(ops node:$x), (v2f64 (splat_vector (f64 $x)))>; 142 let prefix = "f64x2"; 143} 144 145defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2]; 146defvar IntVecs = [I8x16, I16x8, I32x4, I64x2]; 147 148//===----------------------------------------------------------------------===// 149// Load and store 150//===----------------------------------------------------------------------===// 151 152// Load: v128.load 153let mayLoad = 1, UseNamedOperandTable = 1 in { 154defm LOAD_V128_A32 : 155 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 156 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 157 "v128.load\t$dst, ${off}(${addr})$p2align", 158 "v128.load\t$off$p2align", 0>; 159defm LOAD_V128_A64 : 160 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 161 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 162 "v128.load\t$dst, ${off}(${addr})$p2align", 163 "v128.load\t$off$p2align", 0>; 164} 165 166// Def load patterns from WebAssemblyInstrMemory.td for vector types 167foreach vec = AllVecs in { 168defm : LoadPat<vec.vt, load, "LOAD_V128">; 169} 170 171// v128.loadX_splat 172multiclass SIMDLoadSplat<int size, bits<32> simdop> { 173 let mayLoad = 1, UseNamedOperandTable = 1 in { 174 defm LOAD#size#_SPLAT_A32 : 175 SIMD_I<(outs V128:$dst), 176 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 177 (outs), 178 (ins P2Align:$p2align, offset32_op:$off), [], 179 "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align", 180 "v128.load"#size#"_splat\t$off$p2align", simdop>; 181 defm LOAD#size#_SPLAT_A64 : 182 SIMD_I<(outs V128:$dst), 183 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 184 (outs), 185 (ins P2Align:$p2align, offset64_op:$off), [], 186 "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align", 187 "v128.load"#size#"_splat\t$off$p2align", simdop>; 188 } 189} 190 191defm "" : SIMDLoadSplat<8, 7>; 192defm "" : SIMDLoadSplat<16, 8>; 193defm "" : SIMDLoadSplat<32, 9>; 194defm "" : SIMDLoadSplat<64, 10>; 195 196foreach vec = AllVecs in { 197 defvar inst = "LOAD"#vec.lane_bits#"_SPLAT"; 198 defm : LoadPat<vec.vt, 199 PatFrag<(ops node:$addr), (splat_vector (vec.lane_vt (vec.lane_load node:$addr)))>, 200 inst>; 201} 202 203// Load and extend 204multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> { 205 defvar signed = vec.prefix#".load"#loadPat#"_s"; 206 defvar unsigned = vec.prefix#".load"#loadPat#"_u"; 207 let mayLoad = 1, UseNamedOperandTable = 1 in { 208 defm LOAD_EXTEND_S_#vec#_A32 : 209 SIMD_I<(outs V128:$dst), 210 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 211 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 212 signed#"\t$dst, ${off}(${addr})$p2align", 213 signed#"\t$off$p2align", simdop>; 214 defm LOAD_EXTEND_U_#vec#_A32 : 215 SIMD_I<(outs V128:$dst), 216 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 217 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 218 unsigned#"\t$dst, ${off}(${addr})$p2align", 219 unsigned#"\t$off$p2align", !add(simdop, 1)>; 220 defm LOAD_EXTEND_S_#vec#_A64 : 221 SIMD_I<(outs V128:$dst), 222 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 223 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 224 signed#"\t$dst, ${off}(${addr})$p2align", 225 signed#"\t$off$p2align", simdop>; 226 defm LOAD_EXTEND_U_#vec#_A64 : 227 SIMD_I<(outs V128:$dst), 228 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 229 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 230 unsigned#"\t$dst, ${off}(${addr})$p2align", 231 unsigned#"\t$off$p2align", !add(simdop, 1)>; 232 } 233} 234 235defm "" : SIMDLoadExtend<I16x8, "8x8", 1>; 236defm "" : SIMDLoadExtend<I32x4, "16x4", 3>; 237defm "" : SIMDLoadExtend<I64x2, "32x2", 5>; 238 239foreach vec = [I16x8, I32x4, I64x2] in 240foreach exts = [["sextloadvi", "_S"], 241 ["zextloadvi", "_U"], 242 ["extloadvi", "_U"]] in { 243defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits); 244defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec; 245defm : LoadPat<vec.vt, loadpat, inst>; 246} 247 248// Load lane into zero vector 249multiclass SIMDLoadZero<Vec vec, bits<32> simdop> { 250 defvar name = "v128.load"#vec.lane_bits#"_zero"; 251 let mayLoad = 1, UseNamedOperandTable = 1 in { 252 defm LOAD_ZERO_#vec#_A32 : 253 SIMD_I<(outs V128:$dst), 254 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 255 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 256 name#"\t$dst, ${off}(${addr})$p2align", 257 name#"\t$off$p2align", simdop>; 258 defm LOAD_ZERO_#vec#_A64 : 259 SIMD_I<(outs V128:$dst), 260 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 261 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 262 name#"\t$dst, ${off}(${addr})$p2align", 263 name#"\t$off$p2align", simdop>; 264 } // mayLoad = 1, UseNamedOperandTable = 1 265} 266 267defm "" : SIMDLoadZero<I32x4, 0x5c>; 268defm "" : SIMDLoadZero<I64x2, 0x5d>; 269 270// Use load_zero to load scalars into vectors as well where possible. 271// TODO: i16, and i8 scalars 272foreach vec = [I32x4, I64x2] in { 273 defvar inst = "LOAD_ZERO_"#vec; 274 defvar pat = PatFrag<(ops node:$addr), (scalar_to_vector (vec.lane_vt (load $addr)))>; 275 defm : LoadPat<vec.vt, pat, inst>; 276} 277 278// TODO: f32x4 and f64x2 as well 279foreach vec = [I32x4, I64x2] in { 280 defvar inst = "LOAD_ZERO_"#vec; 281 defvar pat = PatFrag<(ops node:$ptr), 282 (vector_insert (vec.splat (vec.lane_vt 0)), (vec.lane_vt (load $ptr)), 0)>; 283 defm : LoadPat<vec.vt, pat, inst>; 284} 285 286// Load lane 287multiclass SIMDLoadLane<Vec vec, bits<32> simdop> { 288 defvar name = "v128.load"#vec.lane_bits#"_lane"; 289 let mayLoad = 1, UseNamedOperandTable = 1 in { 290 defm LOAD_LANE_#vec#_A32 : 291 SIMD_I<(outs V128:$dst), 292 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 293 I32:$addr, V128:$vec), 294 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 295 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 296 name#"\t$off$p2align, $idx", simdop>; 297 defm LOAD_LANE_#vec#_A64 : 298 SIMD_I<(outs V128:$dst), 299 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 300 I64:$addr, V128:$vec), 301 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 302 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 303 name#"\t$off$p2align, $idx", simdop>; 304 } // mayLoad = 1, UseNamedOperandTable = 1 305} 306 307defm "" : SIMDLoadLane<I8x16, 0x54>; 308defm "" : SIMDLoadLane<I16x8, 0x55>; 309defm "" : SIMDLoadLane<I32x4, 0x56>; 310defm "" : SIMDLoadLane<I64x2, 0x57>; 311 312// Select loads with no constant offset. 313multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> { 314 defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32"); 315 defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64"); 316 def : Pat<(vec.vt (kind (i32 I32:$addr), 317 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))), 318 (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>, 319 Requires<[HasAddr32]>; 320 def : Pat<(vec.vt (kind (i64 I64:$addr), 321 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))), 322 (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>, 323 Requires<[HasAddr64]>; 324} 325 326def load8_lane : 327 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 328 (vector_insert $vec, (i32 (extloadi8 $ptr)), $idx)>; 329def load16_lane : 330 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 331 (vector_insert $vec, (i32 (extloadi16 $ptr)), $idx)>; 332def load32_lane : 333 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 334 (vector_insert $vec, (i32 (load $ptr)), $idx)>; 335def load64_lane : 336 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 337 (vector_insert $vec, (i64 (load $ptr)), $idx)>; 338// TODO: floating point lanes as well 339 340defm : LoadLanePatNoOffset<I8x16, load8_lane>; 341defm : LoadLanePatNoOffset<I16x8, load16_lane>; 342defm : LoadLanePatNoOffset<I32x4, load32_lane>; 343defm : LoadLanePatNoOffset<I64x2, load64_lane>; 344 345// TODO: Also support the other load patterns for load_lane once the instructions 346// are merged to the proposal. 347 348// Store: v128.store 349let mayStore = 1, UseNamedOperandTable = 1 in { 350defm STORE_V128_A32 : 351 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec), 352 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 353 "v128.store\t${off}(${addr})$p2align, $vec", 354 "v128.store\t$off$p2align", 11>; 355defm STORE_V128_A64 : 356 SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec), 357 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 358 "v128.store\t${off}(${addr})$p2align, $vec", 359 "v128.store\t$off$p2align", 11>; 360} 361 362// Def store patterns from WebAssemblyInstrMemory.td for vector types 363foreach vec = AllVecs in { 364defm : StorePat<vec.vt, store, "STORE_V128">; 365} 366 367// Store lane 368multiclass SIMDStoreLane<Vec vec, bits<32> simdop> { 369 defvar name = "v128.store"#vec.lane_bits#"_lane"; 370 let mayStore = 1, UseNamedOperandTable = 1 in { 371 defm STORE_LANE_#vec#_A32 : 372 SIMD_I<(outs), 373 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 374 I32:$addr, V128:$vec), 375 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 376 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 377 name#"\t$off$p2align, $idx", simdop>; 378 defm STORE_LANE_#vec#_A64 : 379 SIMD_I<(outs), 380 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 381 I64:$addr, V128:$vec), 382 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 383 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 384 name#"\t$off$p2align, $idx", simdop>; 385 } // mayStore = 1, UseNamedOperandTable = 1 386} 387 388defm "" : SIMDStoreLane<I8x16, 0x58>; 389defm "" : SIMDStoreLane<I16x8, 0x59>; 390defm "" : SIMDStoreLane<I32x4, 0x5a>; 391defm "" : SIMDStoreLane<I64x2, 0x5b>; 392 393multiclass StoreLanePat<Vec vec, SDPatternOperator kind> { 394 def : Pat<(kind (AddrOps32 offset32_op:$offset, I32:$addr), 395 (vec.vt V128:$vec), 396 (i32 vec.lane_idx:$idx)), 397 (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, $offset, imm:$idx, $addr, $vec)>, 398 Requires<[HasAddr32]>; 399 def : Pat<(kind (AddrOps64 offset64_op:$offset, I64:$addr), 400 (vec.vt V128:$vec), 401 (i32 vec.lane_idx:$idx)), 402 (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, $offset, imm:$idx, $addr, $vec)>, 403 Requires<[HasAddr64]>; 404} 405 406def store8_lane : 407 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 408 (truncstorei8 (i32 (vector_extract $vec, $idx)), $ptr)>; 409def store16_lane : 410 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 411 (truncstorei16 (i32 (vector_extract $vec, $idx)), $ptr)>; 412def store32_lane : 413 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 414 (store (i32 (vector_extract $vec, $idx)), $ptr)>; 415def store64_lane : 416 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 417 (store (i64 (vector_extract $vec, $idx)), $ptr)>; 418// TODO: floating point lanes as well 419 420let AddedComplexity = 1 in { 421defm : StoreLanePat<I8x16, store8_lane>; 422defm : StoreLanePat<I16x8, store16_lane>; 423defm : StoreLanePat<I32x4, store32_lane>; 424defm : StoreLanePat<I64x2, store64_lane>; 425} 426 427//===----------------------------------------------------------------------===// 428// Constructing SIMD values 429//===----------------------------------------------------------------------===// 430 431// Constant: v128.const 432multiclass ConstVec<Vec vec, dag ops, dag pat, string args> { 433 let isMoveImm = 1, isReMaterializable = 1 in 434 defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops, 435 [(set V128:$dst, (vec.vt pat))], 436 "v128.const\t$dst, "#args, 437 "v128.const\t"#args, 12>; 438} 439 440defm "" : ConstVec<I8x16, 441 (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1, 442 vec_i8imm_op:$i2, vec_i8imm_op:$i3, 443 vec_i8imm_op:$i4, vec_i8imm_op:$i5, 444 vec_i8imm_op:$i6, vec_i8imm_op:$i7, 445 vec_i8imm_op:$i8, vec_i8imm_op:$i9, 446 vec_i8imm_op:$iA, vec_i8imm_op:$iB, 447 vec_i8imm_op:$iC, vec_i8imm_op:$iD, 448 vec_i8imm_op:$iE, vec_i8imm_op:$iF), 449 (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3, 450 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7, 451 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB, 452 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF), 453 !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ", 454 "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>; 455defm "" : ConstVec<I16x8, 456 (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1, 457 vec_i16imm_op:$i2, vec_i16imm_op:$i3, 458 vec_i16imm_op:$i4, vec_i16imm_op:$i5, 459 vec_i16imm_op:$i6, vec_i16imm_op:$i7), 460 (build_vector 461 ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3, 462 ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7), 463 "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">; 464let IsCanonical = 1 in 465defm "" : ConstVec<I32x4, 466 (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1, 467 vec_i32imm_op:$i2, vec_i32imm_op:$i3), 468 (build_vector (i32 imm:$i0), (i32 imm:$i1), 469 (i32 imm:$i2), (i32 imm:$i3)), 470 "$i0, $i1, $i2, $i3">; 471defm "" : ConstVec<I64x2, 472 (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1), 473 (build_vector (i64 imm:$i0), (i64 imm:$i1)), 474 "$i0, $i1">; 475defm "" : ConstVec<F32x4, 476 (ins f32imm_op:$i0, f32imm_op:$i1, 477 f32imm_op:$i2, f32imm_op:$i3), 478 (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1), 479 (f32 fpimm:$i2), (f32 fpimm:$i3)), 480 "$i0, $i1, $i2, $i3">; 481defm "" : ConstVec<F64x2, 482 (ins f64imm_op:$i0, f64imm_op:$i1), 483 (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), 484 "$i0, $i1">; 485 486// Match splat(x) -> const.v128(x, ..., x) 487foreach vec = AllVecs in { 488 defvar numEls = !div(vec.vt.Size, vec.lane_bits); 489 defvar isFloat = !or(!eq(vec.lane_vt, f32), !eq(vec.lane_vt, f64)); 490 defvar immKind = !if(isFloat, fpimm, imm); 491 def : Pat<(vec.splat (vec.lane_vt immKind:$x)), 492 !dag(!cast<NI>("CONST_V128_"#vec), 493 !listsplat((vec.lane_vt immKind:$x), numEls), 494 ?)>; 495} 496 497// Shuffle lanes: shuffle 498defm SHUFFLE : 499 SIMD_I<(outs V128:$dst), 500 (ins V128:$x, V128:$y, 501 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 502 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 503 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 504 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 505 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 506 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 507 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 508 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 509 (outs), 510 (ins 511 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 512 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 513 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 514 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 515 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 516 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 517 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 518 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 519 [], 520 "i8x16.shuffle\t$dst, $x, $y, "# 521 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 522 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 523 "i8x16.shuffle\t"# 524 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 525 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 526 13>; 527 528// Shuffles after custom lowering 529def wasm_shuffle_t : SDTypeProfile<1, 18, []>; 530def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>; 531foreach vec = AllVecs in { 532// The @llvm.wasm.shuffle intrinsic has immediate arguments that become TargetConstants. 533def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y), 534 (i32 timm:$m0), (i32 timm:$m1), 535 (i32 timm:$m2), (i32 timm:$m3), 536 (i32 timm:$m4), (i32 timm:$m5), 537 (i32 timm:$m6), (i32 timm:$m7), 538 (i32 timm:$m8), (i32 timm:$m9), 539 (i32 timm:$mA), (i32 timm:$mB), 540 (i32 timm:$mC), (i32 timm:$mD), 541 (i32 timm:$mE), (i32 timm:$mF))), 542 (SHUFFLE $x, $y, 543 imm:$m0, imm:$m1, imm:$m2, imm:$m3, 544 imm:$m4, imm:$m5, imm:$m6, imm:$m7, 545 imm:$m8, imm:$m9, imm:$mA, imm:$mB, 546 imm:$mC, imm:$mD, imm:$mE, imm:$mF)>; 547// Normal shufflevector instructions may have normal constant arguemnts. 548def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y), 549 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 550 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 551 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 552 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 553 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 554 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 555 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 556 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))), 557 (SHUFFLE $x, $y, 558 imm:$m0, imm:$m1, imm:$m2, imm:$m3, 559 imm:$m4, imm:$m5, imm:$m6, imm:$m7, 560 imm:$m8, imm:$m9, imm:$mA, imm:$mB, 561 imm:$mC, imm:$mD, imm:$mE, imm:$mF)>; 562} 563 564// Swizzle lanes: i8x16.swizzle 565def wasm_swizzle_t : SDTypeProfile<1, 2, []>; 566def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>; 567defm SWIZZLE : 568 SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins), 569 [(set (v16i8 V128:$dst), 570 (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))], 571 "i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>; 572 573def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)), 574 (SWIZZLE $src, $mask)>; 575 576multiclass Splat<Vec vec, bits<32> simdop> { 577 defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x), 578 (outs), (ins), 579 [(set (vec.vt V128:$dst), 580 (vec.splat vec.lane_rc:$x))], 581 vec.prefix#".splat\t$dst, $x", vec.prefix#".splat", 582 simdop>; 583} 584 585defm "" : Splat<I8x16, 15>; 586defm "" : Splat<I16x8, 16>; 587defm "" : Splat<I32x4, 17>; 588defm "" : Splat<I64x2, 18>; 589defm "" : Splat<F32x4, 19>; 590defm "" : Splat<F64x2, 20>; 591 592// scalar_to_vector leaves high lanes undefined, so can be a splat 593foreach vec = AllVecs in 594def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))), 595 (!cast<Instruction>("SPLAT_"#vec) $x)>; 596 597//===----------------------------------------------------------------------===// 598// Accessing lanes 599//===----------------------------------------------------------------------===// 600 601// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u 602multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> { 603 defm EXTRACT_LANE_#vec#suffix : 604 SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx), 605 (outs), (ins vec_i8imm_op:$idx), [], 606 vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx", 607 vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>; 608} 609 610defm "" : ExtractLane<I8x16, 21, "_s">; 611defm "" : ExtractLane<I8x16, 22, "_u">; 612defm "" : ExtractLane<I16x8, 24, "_s">; 613defm "" : ExtractLane<I16x8, 25, "_u">; 614defm "" : ExtractLane<I32x4, 27>; 615defm "" : ExtractLane<I64x2, 29>; 616defm "" : ExtractLane<F32x4, 31>; 617defm "" : ExtractLane<F64x2, 33>; 618 619def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), 620 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>; 621def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), 622 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>; 623def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)), 624 (EXTRACT_LANE_I32x4 $vec, imm:$idx)>; 625def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)), 626 (EXTRACT_LANE_F32x4 $vec, imm:$idx)>; 627def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)), 628 (EXTRACT_LANE_I64x2 $vec, imm:$idx)>; 629def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)), 630 (EXTRACT_LANE_F64x2 $vec, imm:$idx)>; 631 632def : Pat< 633 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8), 634 (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>; 635def : Pat< 636 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)), 637 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>; 638def : Pat< 639 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16), 640 (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>; 641def : Pat< 642 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)), 643 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>; 644 645// Replace lane value: replace_lane 646multiclass ReplaceLane<Vec vec, bits<32> simdop> { 647 defm REPLACE_LANE_#vec : 648 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x), 649 (outs), (ins vec_i8imm_op:$idx), 650 [(set V128:$dst, (vector_insert 651 (vec.vt V128:$vec), 652 (vec.lane_vt vec.lane_rc:$x), 653 (i32 vec.lane_idx:$idx)))], 654 vec.prefix#".replace_lane\t$dst, $vec, $idx, $x", 655 vec.prefix#".replace_lane\t$idx", simdop>; 656} 657 658defm "" : ReplaceLane<I8x16, 23>; 659defm "" : ReplaceLane<I16x8, 26>; 660defm "" : ReplaceLane<I32x4, 28>; 661defm "" : ReplaceLane<I64x2, 30>; 662defm "" : ReplaceLane<F32x4, 32>; 663defm "" : ReplaceLane<F64x2, 34>; 664 665// Lower undef lane indices to zero 666def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef), 667 (REPLACE_LANE_I8x16 $vec, 0, $x)>; 668def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef), 669 (REPLACE_LANE_I16x8 $vec, 0, $x)>; 670def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef), 671 (REPLACE_LANE_I32x4 $vec, 0, $x)>; 672def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef), 673 (REPLACE_LANE_I64x2 $vec, 0, $x)>; 674def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef), 675 (REPLACE_LANE_F32x4 $vec, 0, $x)>; 676def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef), 677 (REPLACE_LANE_F64x2 $vec, 0, $x)>; 678 679//===----------------------------------------------------------------------===// 680// Comparisons 681//===----------------------------------------------------------------------===// 682 683multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> { 684 defm _#vec : 685 SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 686 [(set (vec.int_vt V128:$dst), 687 (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))], 688 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 689 vec.prefix#"."#name, simdop>; 690} 691 692multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { 693 defm "" : SIMDCondition<I8x16, name, cond, baseInst>; 694 defm "" : SIMDCondition<I16x8, name, cond, !add(baseInst, 10)>; 695 defm "" : SIMDCondition<I32x4, name, cond, !add(baseInst, 20)>; 696} 697 698multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { 699 defm "" : SIMDCondition<F32x4, name, cond, baseInst>; 700 defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>; 701} 702 703// Equality: eq 704let isCommutable = 1 in { 705defm EQ : SIMDConditionInt<"eq", SETEQ, 35>; 706defm EQ : SIMDCondition<I64x2, "eq", SETEQ, 214>; 707defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>; 708} // isCommutable = 1 709 710// Non-equality: ne 711let isCommutable = 1 in { 712defm NE : SIMDConditionInt<"ne", SETNE, 36>; 713defm NE : SIMDCondition<I64x2, "ne", SETNE, 215>; 714defm NE : SIMDConditionFP<"ne", SETUNE, 66>; 715} // isCommutable = 1 716 717// Less than: lt_s / lt_u / lt 718defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>; 719defm LT_S : SIMDCondition<I64x2, "lt_s", SETLT, 216>; 720defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>; 721defm LT : SIMDConditionFP<"lt", SETOLT, 67>; 722 723// Greater than: gt_s / gt_u / gt 724defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>; 725defm GT_S : SIMDCondition<I64x2, "gt_s", SETGT, 217>; 726defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>; 727defm GT : SIMDConditionFP<"gt", SETOGT, 68>; 728 729// Less than or equal: le_s / le_u / le 730defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>; 731defm LE_S : SIMDCondition<I64x2, "le_s", SETLE, 218>; 732defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>; 733defm LE : SIMDConditionFP<"le", SETOLE, 69>; 734 735// Greater than or equal: ge_s / ge_u / ge 736defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>; 737defm GE_S : SIMDCondition<I64x2, "ge_s", SETGE, 219>; 738defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>; 739defm GE : SIMDConditionFP<"ge", SETOGE, 70>; 740 741// Lower float comparisons that don't care about NaN to standard WebAssembly 742// float comparisons. These instructions are generated with nnan and in the 743// target-independent expansion of unordered comparisons and ordered ne. 744foreach nodes = [[seteq, EQ_F32x4], [setne, NE_F32x4], [setlt, LT_F32x4], 745 [setgt, GT_F32x4], [setle, LE_F32x4], [setge, GE_F32x4]] in 746def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 747 (nodes[1] $lhs, $rhs)>; 748 749foreach nodes = [[seteq, EQ_F64x2], [setne, NE_F64x2], [setlt, LT_F64x2], 750 [setgt, GT_F64x2], [setle, LE_F64x2], [setge, GE_F64x2]] in 751def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 752 (nodes[1] $lhs, $rhs)>; 753 754//===----------------------------------------------------------------------===// 755// Bitwise operations 756//===----------------------------------------------------------------------===// 757 758multiclass SIMDBinary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> { 759 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 760 (outs), (ins), 761 [(set (vec.vt V128:$dst), 762 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))], 763 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 764 vec.prefix#"."#name, simdop>; 765} 766 767multiclass SIMDBitwise<SDPatternOperator node, string name, bits<32> simdop, 768 bit commutable = false> { 769 let isCommutable = commutable in 770 defm "" : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 771 (outs), (ins), [], 772 "v128."#name#"\t$dst, $lhs, $rhs", "v128."#name, simdop>; 773 foreach vec = IntVecs in 774 def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 775 (!cast<NI>(NAME) $lhs, $rhs)>; 776} 777 778multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> { 779 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), 780 [(set (vec.vt V128:$dst), 781 (vec.vt (node (vec.vt V128:$v))))], 782 vec.prefix#"."#name#"\t$dst, $v", 783 vec.prefix#"."#name, simdop>; 784} 785 786// Bitwise logic: v128.not 787defm NOT : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), [], 788 "v128.not\t$dst, $v", "v128.not", 77>; 789foreach vec = IntVecs in 790def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>; 791 792// Bitwise logic: v128.and / v128.or / v128.xor 793defm AND : SIMDBitwise<and, "and", 78, true>; 794defm OR : SIMDBitwise<or, "or", 80, true>; 795defm XOR : SIMDBitwise<xor, "xor", 81, true>; 796 797// Bitwise logic: v128.andnot 798def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>; 799defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>; 800 801// Bitwise select: v128.bitselect 802defm BITSELECT : 803 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), [], 804 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>; 805 806foreach vec = AllVecs in 807def : Pat<(vec.vt (int_wasm_bitselect 808 (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))), 809 (BITSELECT $v1, $v2, $c)>; 810 811// Bitselect is equivalent to (c & v1) | (~c & v2) 812foreach vec = IntVecs in 813def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)), 814 (and (vnot V128:$c), (vec.vt V128:$v2)))), 815 (BITSELECT $v1, $v2, $c)>; 816 817// Bitselect is also equivalent to ((v1 ^ v2) & c) ^ v2 818foreach vec = IntVecs in 819def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)), 820 (vec.vt V128:$c)), 821 (vec.vt V128:$v2))), 822 (BITSELECT $v1, $v2, $c)>; 823 824// Same pattern with `c` negated so `a` and `b` get swapped. 825foreach vec = IntVecs in 826def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)), 827 (vnot (vec.vt V128:$c))), 828 (vec.vt V128:$v2))), 829 (BITSELECT $v2, $v1, $c)>; 830 831// Also implement vselect in terms of bitselect 832foreach vec = AllVecs in 833def : Pat<(vec.vt (vselect 834 (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))), 835 (BITSELECT $v1, $v2, $c)>; 836 837// MVP select on v128 values 838defm SELECT_V128 : 839 I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond), (outs), (ins), [], 840 "v128.select\t$dst, $lhs, $rhs, $cond", "v128.select", 0x1b>; 841 842foreach vec = AllVecs in { 843def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 844 (SELECT_V128 $lhs, $rhs, $cond)>; 845 846// ISD::SELECT requires its operand to conform to getBooleanContents, but 847// WebAssembly's select interprets any non-zero value as true, so we can fold 848// a setne with 0 into a select. 849def : Pat<(select 850 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 851 (SELECT_V128 $lhs, $rhs, $cond)>; 852 853// And again, this time with seteq instead of setne and the arms reversed. 854def : Pat<(select 855 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 856 (SELECT_V128 $rhs, $lhs, $cond)>; 857} // foreach vec 858 859//===----------------------------------------------------------------------===// 860// Integer unary arithmetic 861//===----------------------------------------------------------------------===// 862 863multiclass SIMDUnaryInt<SDPatternOperator node, string name, bits<32> baseInst> { 864 defm "" : SIMDUnary<I8x16, node, name, baseInst>; 865 defm "" : SIMDUnary<I16x8, node, name, !add(baseInst, 32)>; 866 defm "" : SIMDUnary<I32x4, node, name, !add(baseInst, 64)>; 867 defm "" : SIMDUnary<I64x2, node, name, !add(baseInst, 96)>; 868} 869 870// Integer vector negation 871def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, $in)>; 872 873// Integer absolute value: abs 874defm ABS : SIMDUnaryInt<abs, "abs", 96>; 875 876// Integer negation: neg 877defm NEG : SIMDUnaryInt<ivneg, "neg", 97>; 878 879// Population count: popcnt 880defm POPCNT : SIMDUnary<I8x16, ctpop, "popcnt", 0x62>; 881 882// Any lane true: any_true 883defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [], 884 "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>; 885 886foreach vec = IntVecs in 887def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>; 888 889// All lanes true: all_true 890multiclass SIMDAllTrue<Vec vec, bits<32> simdop> { 891 defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 892 [(set I32:$dst, 893 (i32 (int_wasm_alltrue (vec.vt V128:$vec))))], 894 vec.prefix#".all_true\t$dst, $vec", 895 vec.prefix#".all_true", simdop>; 896} 897 898defm "" : SIMDAllTrue<I8x16, 0x63>; 899defm "" : SIMDAllTrue<I16x8, 0x83>; 900defm "" : SIMDAllTrue<I32x4, 0xa3>; 901defm "" : SIMDAllTrue<I64x2, 0xc3>; 902 903// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1 904// can be folded out 905foreach reduction = 906 [["int_wasm_anytrue", "ANYTRUE", "I8x16"], 907 ["int_wasm_anytrue", "ANYTRUE", "I16x8"], 908 ["int_wasm_anytrue", "ANYTRUE", "I32x4"], 909 ["int_wasm_anytrue", "ANYTRUE", "I64x2"], 910 ["int_wasm_alltrue", "ALLTRUE_I8x16", "I8x16"], 911 ["int_wasm_alltrue", "ALLTRUE_I16x8", "I16x8"], 912 ["int_wasm_alltrue", "ALLTRUE_I32x4", "I32x4"], 913 ["int_wasm_alltrue", "ALLTRUE_I64x2", "I64x2"]] in { 914defvar intrinsic = !cast<Intrinsic>(reduction[0]); 915defvar inst = !cast<NI>(reduction[1]); 916defvar vec = !cast<Vec>(reduction[2]); 917def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>; 918def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>; 919def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>; 920} 921 922multiclass SIMDBitmask<Vec vec, bits<32> simdop> { 923 defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 924 [(set I32:$dst, 925 (i32 (int_wasm_bitmask (vec.vt V128:$vec))))], 926 vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask", 927 simdop>; 928} 929 930defm BITMASK : SIMDBitmask<I8x16, 100>; 931defm BITMASK : SIMDBitmask<I16x8, 132>; 932defm BITMASK : SIMDBitmask<I32x4, 164>; 933defm BITMASK : SIMDBitmask<I64x2, 196>; 934 935//===----------------------------------------------------------------------===// 936// Bit shifts 937//===----------------------------------------------------------------------===// 938 939multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> { 940 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins), 941 [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))], 942 vec.prefix#"."#name#"\t$dst, $vec, $x", 943 vec.prefix#"."#name, simdop>; 944} 945 946multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> { 947 defm "" : SIMDShift<I8x16, node, name, baseInst>; 948 defm "" : SIMDShift<I16x8, node, name, !add(baseInst, 32)>; 949 defm "" : SIMDShift<I32x4, node, name, !add(baseInst, 64)>; 950 defm "" : SIMDShift<I64x2, node, name, !add(baseInst, 96)>; 951} 952 953// WebAssembly SIMD shifts are nonstandard in that the shift amount is 954// an i32 rather than a vector, so they need custom nodes. 955def wasm_shift_t : 956 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; 957def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>; 958def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>; 959def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>; 960 961// Left shift by scalar: shl 962defm SHL : SIMDShiftInt<wasm_shl, "shl", 107>; 963 964// Right shift by scalar: shr_s / shr_u 965defm SHR_S : SIMDShiftInt<wasm_shr_s, "shr_s", 108>; 966defm SHR_U : SIMDShiftInt<wasm_shr_u, "shr_u", 109>; 967 968// Optimize away an explicit mask on a shift count. 969def : Pat<(wasm_shl (v16i8 V128:$lhs), (and I32:$rhs, 7)), 970 (SHL_I8x16 V128:$lhs, I32:$rhs)>; 971def : Pat<(wasm_shr_s (v16i8 V128:$lhs), (and I32:$rhs, 7)), 972 (SHR_S_I8x16 V128:$lhs, I32:$rhs)>; 973def : Pat<(wasm_shr_u (v16i8 V128:$lhs), (and I32:$rhs, 7)), 974 (SHR_U_I8x16 V128:$lhs, I32:$rhs)>; 975 976def : Pat<(wasm_shl (v8i16 V128:$lhs), (and I32:$rhs, 15)), 977 (SHL_I16x8 V128:$lhs, I32:$rhs)>; 978def : Pat<(wasm_shr_s (v8i16 V128:$lhs), (and I32:$rhs, 15)), 979 (SHR_S_I16x8 V128:$lhs, I32:$rhs)>; 980def : Pat<(wasm_shr_u (v8i16 V128:$lhs), (and I32:$rhs, 15)), 981 (SHR_U_I16x8 V128:$lhs, I32:$rhs)>; 982 983def : Pat<(wasm_shl (v4i32 V128:$lhs), (and I32:$rhs, 31)), 984 (SHL_I32x4 V128:$lhs, I32:$rhs)>; 985def : Pat<(wasm_shr_s (v4i32 V128:$lhs), (and I32:$rhs, 31)), 986 (SHR_S_I32x4 V128:$lhs, I32:$rhs)>; 987def : Pat<(wasm_shr_u (v4i32 V128:$lhs), (and I32:$rhs, 31)), 988 (SHR_U_I32x4 V128:$lhs, I32:$rhs)>; 989 990def : Pat<(wasm_shl (v2i64 V128:$lhs), (and I32:$rhs, 63)), 991 (SHL_I64x2 V128:$lhs, I32:$rhs)>; 992def : Pat<(wasm_shr_s (v2i64 V128:$lhs), (and I32:$rhs, 63)), 993 (SHR_S_I64x2 V128:$lhs, I32:$rhs)>; 994def : Pat<(wasm_shr_u (v2i64 V128:$lhs), (and I32:$rhs, 63)), 995 (SHR_U_I64x2 V128:$lhs, I32:$rhs)>; 996def : Pat<(wasm_shl (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 997 (SHL_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 998def : Pat<(wasm_shr_s (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 999 (SHR_S_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 1000def : Pat<(wasm_shr_u (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 1001 (SHR_U_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 1002 1003//===----------------------------------------------------------------------===// 1004// Integer binary arithmetic 1005//===----------------------------------------------------------------------===// 1006 1007multiclass SIMDBinaryIntNoI8x16<SDPatternOperator node, string name, bits<32> baseInst> { 1008 defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>; 1009 defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>; 1010 defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>; 1011} 1012 1013multiclass SIMDBinaryIntSmall<SDPatternOperator node, string name, bits<32> baseInst> { 1014 defm "" : SIMDBinary<I8x16, node, name, baseInst>; 1015 defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>; 1016} 1017 1018multiclass SIMDBinaryIntNoI64x2<SDPatternOperator node, string name, bits<32> baseInst> { 1019 defm "" : SIMDBinaryIntSmall<node, name, baseInst>; 1020 defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>; 1021} 1022 1023multiclass SIMDBinaryInt<SDPatternOperator node, string name, bits<32> baseInst> { 1024 defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>; 1025 defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>; 1026} 1027 1028// Integer addition: add / add_sat_s / add_sat_u 1029let isCommutable = 1 in { 1030defm ADD : SIMDBinaryInt<add, "add", 110>; 1031defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_sat_s", 111>; 1032defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_sat_u", 112>; 1033} // isCommutable = 1 1034 1035// Integer subtraction: sub / sub_sat_s / sub_sat_u 1036defm SUB : SIMDBinaryInt<sub, "sub", 113>; 1037defm SUB_SAT_S : 1038 SIMDBinaryIntSmall<int_wasm_sub_sat_signed, "sub_sat_s", 114>; 1039defm SUB_SAT_U : 1040 SIMDBinaryIntSmall<int_wasm_sub_sat_unsigned, "sub_sat_u", 115>; 1041 1042// Integer multiplication: mul 1043let isCommutable = 1 in 1044defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>; 1045 1046// Integer min_s / min_u / max_s / max_u 1047let isCommutable = 1 in { 1048defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>; 1049defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>; 1050defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>; 1051defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>; 1052} // isCommutable = 1 1053 1054// Integer unsigned rounding average: avgr_u 1055let isCommutable = 1 in { 1056defm AVGR_U : SIMDBinary<I8x16, int_wasm_avgr_unsigned, "avgr_u", 123>; 1057defm AVGR_U : SIMDBinary<I16x8, int_wasm_avgr_unsigned, "avgr_u", 155>; 1058} 1059 1060def add_nuw : PatFrag<(ops node:$lhs, node:$rhs), (add $lhs, $rhs), 1061 "return N->getFlags().hasNoUnsignedWrap();">; 1062 1063foreach vec = [I8x16, I16x8] in { 1064defvar inst = !cast<NI>("AVGR_U_"#vec); 1065def : Pat<(wasm_shr_u 1066 (add_nuw 1067 (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 1068 (vec.splat (i32 1))), 1069 (i32 1)), 1070 (inst $lhs, $rhs)>; 1071} 1072 1073// Widening dot product: i32x4.dot_i16x8_s 1074let isCommutable = 1 in 1075defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 1076 [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))], 1077 "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s", 1078 186>; 1079 1080// Extending multiplication: extmul_{low,high}_P, extmul_high 1081def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1082def extend_low_s : SDNode<"WebAssemblyISD::EXTEND_LOW_S", extend_t>; 1083def extend_high_s : SDNode<"WebAssemblyISD::EXTEND_HIGH_S", extend_t>; 1084def extend_low_u : SDNode<"WebAssemblyISD::EXTEND_LOW_U", extend_t>; 1085def extend_high_u : SDNode<"WebAssemblyISD::EXTEND_HIGH_U", extend_t>; 1086 1087multiclass SIMDExtBinary<Vec vec, SDPatternOperator node, string name, 1088 bits<32> simdop> { 1089 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 1090 (outs), (ins), 1091 [(set (vec.vt V128:$dst), (node 1092 (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))], 1093 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 1094 vec.prefix#"."#name, simdop>; 1095} 1096 1097class ExtMulPat<SDNode extend> : 1098 PatFrag<(ops node:$lhs, node:$rhs), 1099 (mul (extend $lhs), (extend $rhs))> {} 1100 1101def extmul_low_s : ExtMulPat<extend_low_s>; 1102def extmul_high_s : ExtMulPat<extend_high_s>; 1103def extmul_low_u : ExtMulPat<extend_low_u>; 1104def extmul_high_u : ExtMulPat<extend_high_u>; 1105 1106defm EXTMUL_LOW_S : 1107 SIMDExtBinary<I16x8, extmul_low_s, "extmul_low_i8x16_s", 0x9c>; 1108defm EXTMUL_HIGH_S : 1109 SIMDExtBinary<I16x8, extmul_high_s, "extmul_high_i8x16_s", 0x9d>; 1110defm EXTMUL_LOW_U : 1111 SIMDExtBinary<I16x8, extmul_low_u, "extmul_low_i8x16_u", 0x9e>; 1112defm EXTMUL_HIGH_U : 1113 SIMDExtBinary<I16x8, extmul_high_u, "extmul_high_i8x16_u", 0x9f>; 1114 1115defm EXTMUL_LOW_S : 1116 SIMDExtBinary<I32x4, extmul_low_s, "extmul_low_i16x8_s", 0xbc>; 1117defm EXTMUL_HIGH_S : 1118 SIMDExtBinary<I32x4, extmul_high_s, "extmul_high_i16x8_s", 0xbd>; 1119defm EXTMUL_LOW_U : 1120 SIMDExtBinary<I32x4, extmul_low_u, "extmul_low_i16x8_u", 0xbe>; 1121defm EXTMUL_HIGH_U : 1122 SIMDExtBinary<I32x4, extmul_high_u, "extmul_high_i16x8_u", 0xbf>; 1123 1124defm EXTMUL_LOW_S : 1125 SIMDExtBinary<I64x2, extmul_low_s, "extmul_low_i32x4_s", 0xdc>; 1126defm EXTMUL_HIGH_S : 1127 SIMDExtBinary<I64x2, extmul_high_s, "extmul_high_i32x4_s", 0xdd>; 1128defm EXTMUL_LOW_U : 1129 SIMDExtBinary<I64x2, extmul_low_u, "extmul_low_i32x4_u", 0xde>; 1130defm EXTMUL_HIGH_U : 1131 SIMDExtBinary<I64x2, extmul_high_u, "extmul_high_i32x4_u", 0xdf>; 1132 1133//===----------------------------------------------------------------------===// 1134// Floating-point unary arithmetic 1135//===----------------------------------------------------------------------===// 1136 1137multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> { 1138 defm "" : SIMDUnary<F32x4, node, name, baseInst>; 1139 defm "" : SIMDUnary<F64x2, node, name, !add(baseInst, 12)>; 1140} 1141 1142// Absolute value: abs 1143defm ABS : SIMDUnaryFP<fabs, "abs", 224>; 1144 1145// Negation: neg 1146defm NEG : SIMDUnaryFP<fneg, "neg", 225>; 1147 1148// Square root: sqrt 1149defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>; 1150 1151// Rounding: ceil, floor, trunc, nearest 1152defm CEIL : SIMDUnary<F32x4, fceil, "ceil", 0x67>; 1153defm FLOOR : SIMDUnary<F32x4, ffloor, "floor", 0x68>; 1154defm TRUNC: SIMDUnary<F32x4, ftrunc, "trunc", 0x69>; 1155defm NEAREST: SIMDUnary<F32x4, fnearbyint, "nearest", 0x6a>; 1156defm CEIL : SIMDUnary<F64x2, fceil, "ceil", 0x74>; 1157defm FLOOR : SIMDUnary<F64x2, ffloor, "floor", 0x75>; 1158defm TRUNC: SIMDUnary<F64x2, ftrunc, "trunc", 0x7a>; 1159defm NEAREST: SIMDUnary<F64x2, fnearbyint, "nearest", 0x94>; 1160 1161// WebAssembly doesn't expose inexact exceptions, so map frint to fnearbyint. 1162def : Pat<(v4f32 (frint (v4f32 V128:$src))), (NEAREST_F32x4 V128:$src)>; 1163def : Pat<(v2f64 (frint (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>; 1164 1165// WebAssembly always rounds ties-to-even, so map froundeven to fnearbyint. 1166def : Pat<(v4f32 (froundeven (v4f32 V128:$src))), (NEAREST_F32x4 V128:$src)>; 1167def : Pat<(v2f64 (froundeven (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>; 1168 1169//===----------------------------------------------------------------------===// 1170// Floating-point binary arithmetic 1171//===----------------------------------------------------------------------===// 1172 1173multiclass SIMDBinaryFP<SDPatternOperator node, string name, bits<32> baseInst> { 1174 defm "" : SIMDBinary<F32x4, node, name, baseInst>; 1175 defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>; 1176} 1177 1178// Addition: add 1179let isCommutable = 1 in 1180defm ADD : SIMDBinaryFP<fadd, "add", 228>; 1181 1182// Subtraction: sub 1183defm SUB : SIMDBinaryFP<fsub, "sub", 229>; 1184 1185// Multiplication: mul 1186let isCommutable = 1 in 1187defm MUL : SIMDBinaryFP<fmul, "mul", 230>; 1188 1189// Division: div 1190defm DIV : SIMDBinaryFP<fdiv, "div", 231>; 1191 1192// NaN-propagating minimum: min 1193defm MIN : SIMDBinaryFP<fminimum, "min", 232>; 1194 1195// NaN-propagating maximum: max 1196defm MAX : SIMDBinaryFP<fmaximum, "max", 233>; 1197 1198// Pseudo-minimum: pmin 1199def pmin : PatFrags<(ops node:$lhs, node:$rhs), [ 1200 (vselect (setolt $rhs, $lhs), $rhs, $lhs), 1201 (vselect (setole $rhs, $lhs), $rhs, $lhs), 1202 (vselect (setogt $lhs, $rhs), $rhs, $lhs), 1203 (vselect (setoge $lhs, $rhs), $rhs, $lhs) 1204]>; 1205defm PMIN : SIMDBinaryFP<pmin, "pmin", 234>; 1206 1207// Pseudo-maximum: pmax 1208def pmax : PatFrags<(ops node:$lhs, node:$rhs), [ 1209 (vselect (setogt $rhs, $lhs), $rhs, $lhs), 1210 (vselect (setoge $rhs, $lhs), $rhs, $lhs), 1211 (vselect (setolt $lhs, $rhs), $rhs, $lhs), 1212 (vselect (setole $lhs, $rhs), $rhs, $lhs) 1213]>; 1214defm PMAX : SIMDBinaryFP<pmax, "pmax", 235>; 1215 1216// Also match the pmin/pmax cases where the operands are int vectors (but the 1217// comparison is still a floating point comparison). This can happen when using 1218// the wasm_simd128.h intrinsics because v128_t is an integer vector. 1219foreach vec = [F32x4, F64x2] in { 1220defvar pmin = !cast<NI>("PMIN_"#vec); 1221defvar pmax = !cast<NI>("PMAX_"#vec); 1222def : Pat<(vec.int_vt (vselect 1223 (setolt (vec.vt (bitconvert V128:$rhs)), 1224 (vec.vt (bitconvert V128:$lhs))), 1225 V128:$rhs, V128:$lhs)), 1226 (pmin $lhs, $rhs)>; 1227def : Pat<(vec.int_vt (vselect 1228 (setolt (vec.vt (bitconvert V128:$lhs)), 1229 (vec.vt (bitconvert V128:$rhs))), 1230 V128:$rhs, V128:$lhs)), 1231 (pmax $lhs, $rhs)>; 1232} 1233 1234// And match the pmin/pmax LLVM intrinsics as well 1235def : Pat<(v4f32 (int_wasm_pmin (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 1236 (PMIN_F32x4 V128:$lhs, V128:$rhs)>; 1237def : Pat<(v4f32 (int_wasm_pmax (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 1238 (PMAX_F32x4 V128:$lhs, V128:$rhs)>; 1239def : Pat<(v2f64 (int_wasm_pmin (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 1240 (PMIN_F64x2 V128:$lhs, V128:$rhs)>; 1241def : Pat<(v2f64 (int_wasm_pmax (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 1242 (PMAX_F64x2 V128:$lhs, V128:$rhs)>; 1243 1244//===----------------------------------------------------------------------===// 1245// Conversions 1246//===----------------------------------------------------------------------===// 1247 1248multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name, 1249 bits<32> simdop> { 1250 defm op#_#vec : 1251 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 1252 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))], 1253 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>; 1254} 1255 1256// Floating point to integer with saturation: trunc_sat 1257defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>; 1258defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>; 1259 1260// Support the saturating variety as well. 1261def trunc_s_sat32 : PatFrag<(ops node:$x), (fp_to_sint_sat $x, i32)>; 1262def trunc_u_sat32 : PatFrag<(ops node:$x), (fp_to_uint_sat $x, i32)>; 1263def : Pat<(v4i32 (trunc_s_sat32 (v4f32 V128:$src))), (fp_to_sint_I32x4 $src)>; 1264def : Pat<(v4i32 (trunc_u_sat32 (v4f32 V128:$src))), (fp_to_uint_I32x4 $src)>; 1265 1266def trunc_sat_zero_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1267def trunc_sat_zero_s : 1268 SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_S", trunc_sat_zero_t>; 1269def trunc_sat_zero_u : 1270 SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_U", trunc_sat_zero_t>; 1271defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_s, "trunc_sat_f64x2_s_zero", 1272 0xfc>; 1273defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_u, "trunc_sat_f64x2_u_zero", 1274 0xfd>; 1275 1276// Integer to floating point: convert 1277def convert_low_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1278def convert_low_s : SDNode<"WebAssemblyISD::CONVERT_LOW_S", convert_low_t>; 1279def convert_low_u : SDNode<"WebAssemblyISD::CONVERT_LOW_U", convert_low_t>; 1280defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>; 1281defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>; 1282defm "" : SIMDConvert<F64x2, I32x4, convert_low_s, "convert_low_i32x4_s", 0xfe>; 1283defm "" : SIMDConvert<F64x2, I32x4, convert_low_u, "convert_low_i32x4_u", 0xff>; 1284 1285// Extending operations 1286// TODO: refactor this to be uniform for i64x2 if the numbering is not changed. 1287multiclass SIMDExtend<Vec vec, bits<32> baseInst> { 1288 defm "" : SIMDConvert<vec, vec.split, extend_low_s, 1289 "extend_low_"#vec.split.prefix#"_s", baseInst>; 1290 defm "" : SIMDConvert<vec, vec.split, extend_high_s, 1291 "extend_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>; 1292 defm "" : SIMDConvert<vec, vec.split, extend_low_u, 1293 "extend_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>; 1294 defm "" : SIMDConvert<vec, vec.split, extend_high_u, 1295 "extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>; 1296} 1297 1298defm "" : SIMDExtend<I16x8, 0x87>; 1299defm "" : SIMDExtend<I32x4, 0xa7>; 1300defm "" : SIMDExtend<I64x2, 0xc7>; 1301 1302// Narrowing operations 1303multiclass SIMDNarrow<Vec vec, bits<32> baseInst> { 1304 defvar name = vec.split.prefix#".narrow_"#vec.prefix; 1305 defm NARROW_S_#vec.split : 1306 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1307 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed 1308 (vec.vt V128:$low), (vec.vt V128:$high))))], 1309 name#"_s\t$dst, $low, $high", name#"_s", baseInst>; 1310 defm NARROW_U_#vec.split : 1311 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1312 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned 1313 (vec.vt V128:$low), (vec.vt V128:$high))))], 1314 name#"_u\t$dst, $low, $high", name#"_u", !add(baseInst, 1)>; 1315} 1316 1317defm "" : SIMDNarrow<I16x8, 101>; 1318defm "" : SIMDNarrow<I32x4, 133>; 1319 1320// WebAssemblyISD::NARROW_U 1321def wasm_narrow_t : SDTypeProfile<1, 2, []>; 1322def wasm_narrow_u : SDNode<"WebAssemblyISD::NARROW_U", wasm_narrow_t>; 1323def : Pat<(v16i8 (wasm_narrow_u (v8i16 V128:$left), (v8i16 V128:$right))), 1324 (NARROW_U_I8x16 $left, $right)>; 1325def : Pat<(v8i16 (wasm_narrow_u (v4i32 V128:$left), (v4i32 V128:$right))), 1326 (NARROW_U_I16x8 $left, $right)>; 1327 1328// Bitcasts are nops 1329// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types 1330foreach t1 = AllVecs in 1331foreach t2 = AllVecs in 1332if !ne(t1, t2) then 1333def : Pat<(t1.vt (bitconvert (t2.vt V128:$v))), (t1.vt V128:$v)>; 1334 1335// Extended pairwise addition 1336defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_signed, 1337 "extadd_pairwise_i8x16_s", 0x7c>; 1338defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_unsigned, 1339 "extadd_pairwise_i8x16_u", 0x7d>; 1340defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed, 1341 "extadd_pairwise_i16x8_s", 0x7e>; 1342defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned, 1343 "extadd_pairwise_i16x8_u", 0x7f>; 1344 1345// f64x2 <-> f32x4 conversions 1346def demote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1347def demote_zero : SDNode<"WebAssemblyISD::DEMOTE_ZERO", demote_t>; 1348defm "" : SIMDConvert<F32x4, F64x2, demote_zero, 1349 "demote_f64x2_zero", 0x5e>; 1350 1351def promote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1352def promote_low : SDNode<"WebAssemblyISD::PROMOTE_LOW", promote_t>; 1353defm "" : SIMDConvert<F64x2, F32x4, promote_low, "promote_low_f32x4", 0x5f>; 1354 1355// Lower extending loads to load64_zero + promote_low 1356def extloadv2f32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1357 let MemoryVT = v2f32; 1358} 1359// Adapted from the body of LoadPatNoOffset 1360// TODO: other addressing patterns 1361def : Pat<(v2f64 (extloadv2f32 (i32 I32:$addr))), 1362 (promote_low_F64x2 (LOAD_ZERO_I64x2_A32 0, 0, I32:$addr))>, 1363 Requires<[HasAddr32]>; 1364def : Pat<(v2f64 (extloadv2f32 (i64 I64:$addr))), 1365 (promote_low_F64x2 (LOAD_ZERO_I64x2_A64 0, 0, I64:$addr))>, 1366 Requires<[HasAddr64]>; 1367 1368//===----------------------------------------------------------------------===// 1369// Saturating Rounding Q-Format Multiplication 1370//===----------------------------------------------------------------------===// 1371 1372defm Q15MULR_SAT_S : 1373 SIMDBinary<I16x8, int_wasm_q15mulr_sat_signed, "q15mulr_sat_s", 0x82>; 1374 1375//===----------------------------------------------------------------------===// 1376// Relaxed swizzle 1377//===----------------------------------------------------------------------===// 1378 1379defm RELAXED_SWIZZLE : 1380 RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins), 1381 [(set (v16i8 V128:$dst), 1382 (int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))], 1383 "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 0x100>; 1384 1385//===----------------------------------------------------------------------===// 1386// Relaxed floating-point to int conversions 1387//===----------------------------------------------------------------------===// 1388 1389multiclass RelaxedConvert<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> { 1390 defm op#_#vec : 1391 RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 1392 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))], 1393 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>; 1394} 1395 1396defm "" : RelaxedConvert<I32x4, F32x4, int_wasm_relaxed_trunc_signed, 1397 "relaxed_trunc_f32x4_s", 0x101>; 1398defm "" : RelaxedConvert<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned, 1399 "relaxed_trunc_f32x4_u", 0x102>; 1400defm "" : RelaxedConvert<I32x4, F64x2, int_wasm_relaxed_trunc_signed_zero, 1401 "relaxed_trunc_f64x2_s_zero", 0x103>; 1402defm "" : RelaxedConvert<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero, 1403 "relaxed_trunc_f64x2_u_zero", 0x104>; 1404 1405//===----------------------------------------------------------------------===// 1406// Relaxed (Negative) Multiply-Add (madd/nmadd) 1407//===----------------------------------------------------------------------===// 1408 1409multiclass SIMDMADD<Vec vec, bits<32> simdopA, bits<32> simdopS> { 1410 defm MADD_#vec : 1411 RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), 1412 [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd 1413 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], 1414 vec.prefix#".relaxed_madd\t$dst, $a, $b, $c", 1415 vec.prefix#".relaxed_madd", simdopA>; 1416 defm NMADD_#vec : 1417 RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), 1418 [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd 1419 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], 1420 vec.prefix#".relaxed_nmadd\t$dst, $a, $b, $c", 1421 vec.prefix#".relaxed_nmadd", simdopS>; 1422} 1423 1424defm "" : SIMDMADD<F32x4, 0x105, 0x106>; 1425defm "" : SIMDMADD<F64x2, 0x107, 0x108>; 1426 1427//===----------------------------------------------------------------------===// 1428// Laneselect 1429//===----------------------------------------------------------------------===// 1430 1431multiclass SIMDLANESELECT<Vec vec, bits<32> op> { 1432 defm LANESELECT_#vec : 1433 RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), 1434 [(set (vec.vt V128:$dst), (int_wasm_relaxed_laneselect 1435 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], 1436 vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c", 1437 vec.prefix#".relaxed_laneselect", op>; 1438} 1439 1440defm "" : SIMDLANESELECT<I8x16, 0x109>; 1441defm "" : SIMDLANESELECT<I16x8, 0x10a>; 1442defm "" : SIMDLANESELECT<I32x4, 0x10b>; 1443defm "" : SIMDLANESELECT<I64x2, 0x10c>; 1444 1445//===----------------------------------------------------------------------===// 1446// Relaxed floating-point min and max. 1447//===----------------------------------------------------------------------===// 1448 1449multiclass RelaxedBinary<Vec vec, SDPatternOperator node, string name, 1450 bits<32> simdop> { 1451 defm _#vec : RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 1452 (outs), (ins), 1453 [(set (vec.vt V128:$dst), 1454 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))], 1455 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 1456 vec.prefix#"."#name, simdop>; 1457} 1458 1459defm SIMD_RELAXED_FMIN : 1460 RelaxedBinary<F32x4, int_wasm_relaxed_min, "relaxed_min", 0x10d>; 1461defm SIMD_RELAXED_FMAX : 1462 RelaxedBinary<F32x4, int_wasm_relaxed_max, "relaxed_max", 0x10e>; 1463defm SIMD_RELAXED_FMIN : 1464 RelaxedBinary<F64x2, int_wasm_relaxed_min, "relaxed_min", 0x10f>; 1465defm SIMD_RELAXED_FMAX : 1466 RelaxedBinary<F64x2, int_wasm_relaxed_max, "relaxed_max", 0x110>; 1467 1468//===----------------------------------------------------------------------===// 1469// Relaxed rounding q15 multiplication 1470//===----------------------------------------------------------------------===// 1471 1472defm RELAXED_Q15MULR_S : 1473 RelaxedBinary<I16x8, int_wasm_relaxed_q15mulr_signed, "relaxed_q15mulr_s", 1474 0x111>; 1475 1476//===----------------------------------------------------------------------===// 1477// Relaxed integer dot product 1478//===----------------------------------------------------------------------===// 1479 1480defm RELAXED_DOT : 1481 RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 1482 [(set (v8i16 V128:$dst), (int_wasm_relaxed_dot_i8x16_i7x16_signed 1483 (v16i8 V128:$lhs), (v16i8 V128:$rhs)))], 1484 "i16x8.relaxed_dot_i8x16_i7x16_s\t$dst, $lhs, $rhs", 1485 "i16x8.relaxed_dot_i8x16_i7x16_s", 0x112>; 1486 1487defm RELAXED_DOT_ADD : 1488 RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, V128:$acc), 1489 (outs), (ins), 1490 [(set (v4i32 V128:$dst), (int_wasm_relaxed_dot_i8x16_i7x16_add_signed 1491 (v16i8 V128:$lhs), (v16i8 V128:$rhs), (v4i32 V128:$acc)))], 1492 "i32x4.relaxed_dot_i8x16_i7x16_add_s\t$dst, $lhs, $rhs, $acc", 1493 "i32x4.relaxed_dot_i8x16_i7x16_add_s", 0x113>; 1494 1495//===----------------------------------------------------------------------===// 1496// Relaxed BFloat16 dot product 1497//===----------------------------------------------------------------------===// 1498 1499defm RELAXED_DOT_BFLOAT : 1500 RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, V128:$acc), 1501 (outs), (ins), 1502 [(set (v4f32 V128:$dst), (int_wasm_relaxed_dot_bf16x8_add_f32 1503 (v8i16 V128:$lhs), (v8i16 V128:$rhs), (v4f32 V128:$acc)))], 1504 "f32x4.relaxed_dot_bf16x8_add_f32\t$dst, $lhs, $rhs, $acc", 1505 "f32x4.relaxed_dot_bf16x8_add_f32", 0x114>; 1506