10b57cec5SDimitry Andric //===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file is part of the X86 Disassembler. 100b57cec5SDimitry Andric // It contains the public interface of the instruction decoder. 110b57cec5SDimitry Andric // Documentation for the disassembler can be found in X86Disassembler.h. 120b57cec5SDimitry Andric // 130b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H 160b57cec5SDimitry Andric #define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #include "llvm/ADT/ArrayRef.h" 190b57cec5SDimitry Andric #include "llvm/Support/X86DisassemblerDecoderCommon.h" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric namespace llvm { 220b57cec5SDimitry Andric namespace X86Disassembler { 235f757f3fSDimitry Andric // Helper macros 245f757f3fSDimitry Andric #define bitFromOffset0(val) ((val) & 0x1) 255f757f3fSDimitry Andric #define bitFromOffset1(val) (((val) >> 1) & 0x1) 265f757f3fSDimitry Andric #define bitFromOffset2(val) (((val) >> 2) & 0x1) 275f757f3fSDimitry Andric #define bitFromOffset3(val) (((val) >> 3) & 0x1) 285f757f3fSDimitry Andric #define bitFromOffset4(val) (((val) >> 4) & 0x1) 295f757f3fSDimitry Andric #define bitFromOffset5(val) (((val) >> 5) & 0x1) 305f757f3fSDimitry Andric #define bitFromOffset6(val) (((val) >> 6) & 0x1) 315f757f3fSDimitry Andric #define bitFromOffset7(val) (((val) >> 7) & 0x1) 325f757f3fSDimitry Andric #define twoBitsFromOffset0(val) ((val) & 0x3) 335f757f3fSDimitry Andric #define twoBitsFromOffset6(val) (((val) >> 6) & 0x3) 345f757f3fSDimitry Andric #define threeBitsFromOffset0(val) ((val) & 0x7) 355f757f3fSDimitry Andric #define threeBitsFromOffset3(val) (((val) >> 3) & 0x7) 365f757f3fSDimitry Andric #define fiveBitsFromOffset0(val) ((val) & 0x1f) 375f757f3fSDimitry Andric #define invertedBitFromOffset2(val) (((~(val)) >> 2) & 0x1) 385f757f3fSDimitry Andric #define invertedBitFromOffset3(val) (((~(val)) >> 3) & 0x1) 395f757f3fSDimitry Andric #define invertedBitFromOffset4(val) (((~(val)) >> 4) & 0x1) 405f757f3fSDimitry Andric #define invertedBitFromOffset5(val) (((~(val)) >> 5) & 0x1) 415f757f3fSDimitry Andric #define invertedBitFromOffset6(val) (((~(val)) >> 6) & 0x1) 425f757f3fSDimitry Andric #define invertedBitFromOffset7(val) (((~(val)) >> 7) & 0x1) 435f757f3fSDimitry Andric #define invertedFourBitsFromOffset3(val) (((~(val)) >> 3) & 0xf) 445f757f3fSDimitry Andric // MOD/RM 455f757f3fSDimitry Andric #define modFromModRM(modRM) twoBitsFromOffset6(modRM) 465f757f3fSDimitry Andric #define regFromModRM(modRM) threeBitsFromOffset3(modRM) 475f757f3fSDimitry Andric #define rmFromModRM(modRM) threeBitsFromOffset0(modRM) 485f757f3fSDimitry Andric // SIB 495f757f3fSDimitry Andric #define scaleFromSIB(sib) twoBitsFromOffset6(sib) 505f757f3fSDimitry Andric #define indexFromSIB(sib) threeBitsFromOffset3(sib) 515f757f3fSDimitry Andric #define baseFromSIB(sib) threeBitsFromOffset0(sib) 525f757f3fSDimitry Andric // REX 535f757f3fSDimitry Andric #define wFromREX(rex) bitFromOffset3(rex) 545f757f3fSDimitry Andric #define rFromREX(rex) bitFromOffset2(rex) 555f757f3fSDimitry Andric #define xFromREX(rex) bitFromOffset1(rex) 565f757f3fSDimitry Andric #define bFromREX(rex) bitFromOffset0(rex) 575f757f3fSDimitry Andric // REX2 585f757f3fSDimitry Andric #define mFromREX2(rex2) bitFromOffset7(rex2) 595f757f3fSDimitry Andric #define r2FromREX2(rex2) bitFromOffset6(rex2) 605f757f3fSDimitry Andric #define x2FromREX2(rex2) bitFromOffset5(rex2) 615f757f3fSDimitry Andric #define b2FromREX2(rex2) bitFromOffset4(rex2) 625f757f3fSDimitry Andric #define wFromREX2(rex2) bitFromOffset3(rex2) 635f757f3fSDimitry Andric #define rFromREX2(rex2) bitFromOffset2(rex2) 645f757f3fSDimitry Andric #define xFromREX2(rex2) bitFromOffset1(rex2) 655f757f3fSDimitry Andric #define bFromREX2(rex2) bitFromOffset0(rex2) 665f757f3fSDimitry Andric // XOP 675f757f3fSDimitry Andric #define rFromXOP2of3(xop) invertedBitFromOffset7(xop) 685f757f3fSDimitry Andric #define xFromXOP2of3(xop) invertedBitFromOffset6(xop) 695f757f3fSDimitry Andric #define bFromXOP2of3(xop) invertedBitFromOffset5(xop) 705f757f3fSDimitry Andric #define mmmmmFromXOP2of3(xop) fiveBitsFromOffset0(xop) 715f757f3fSDimitry Andric #define wFromXOP3of3(xop) bitFromOffset7(xop) 725f757f3fSDimitry Andric #define vvvvFromXOP3of3(xop) invertedFourBitsFromOffset3(xop) 735f757f3fSDimitry Andric #define lFromXOP3of3(xop) bitFromOffset2(xop) 745f757f3fSDimitry Andric #define ppFromXOP3of3(xop) twoBitsFromOffset0(xop) 755f757f3fSDimitry Andric // VEX2 765f757f3fSDimitry Andric #define rFromVEX2of2(vex) invertedBitFromOffset7(vex) 775f757f3fSDimitry Andric #define vvvvFromVEX2of2(vex) invertedFourBitsFromOffset3(vex) 785f757f3fSDimitry Andric #define lFromVEX2of2(vex) bitFromOffset2(vex) 795f757f3fSDimitry Andric #define ppFromVEX2of2(vex) twoBitsFromOffset0(vex) 805f757f3fSDimitry Andric // VEX3 815f757f3fSDimitry Andric #define rFromVEX2of3(vex) invertedBitFromOffset7(vex) 825f757f3fSDimitry Andric #define xFromVEX2of3(vex) invertedBitFromOffset6(vex) 835f757f3fSDimitry Andric #define bFromVEX2of3(vex) invertedBitFromOffset5(vex) 845f757f3fSDimitry Andric #define mmmmmFromVEX2of3(vex) fiveBitsFromOffset0(vex) 855f757f3fSDimitry Andric #define wFromVEX3of3(vex) bitFromOffset7(vex) 865f757f3fSDimitry Andric #define vvvvFromVEX3of3(vex) invertedFourBitsFromOffset3(vex) 875f757f3fSDimitry Andric #define lFromVEX3of3(vex) bitFromOffset2(vex) 885f757f3fSDimitry Andric #define ppFromVEX3of3(vex) twoBitsFromOffset0(vex) 895f757f3fSDimitry Andric // EVEX 905f757f3fSDimitry Andric #define rFromEVEX2of4(evex) invertedBitFromOffset7(evex) 915f757f3fSDimitry Andric #define xFromEVEX2of4(evex) invertedBitFromOffset6(evex) 925f757f3fSDimitry Andric #define bFromEVEX2of4(evex) invertedBitFromOffset5(evex) 935f757f3fSDimitry Andric #define r2FromEVEX2of4(evex) invertedBitFromOffset4(evex) 945f757f3fSDimitry Andric #define b2FromEVEX2of4(evex) bitFromOffset3(evex) 955f757f3fSDimitry Andric #define mmmFromEVEX2of4(evex) threeBitsFromOffset0(evex) 965f757f3fSDimitry Andric #define wFromEVEX3of4(evex) bitFromOffset7(evex) 975f757f3fSDimitry Andric #define vvvvFromEVEX3of4(evex) invertedFourBitsFromOffset3(evex) 985f757f3fSDimitry Andric #define x2FromEVEX3of4(evex) invertedBitFromOffset2(evex) 995f757f3fSDimitry Andric #define ppFromEVEX3of4(evex) twoBitsFromOffset0(evex) 1005f757f3fSDimitry Andric #define zFromEVEX4of4(evex) bitFromOffset7(evex) 1015f757f3fSDimitry Andric #define l2FromEVEX4of4(evex) bitFromOffset6(evex) 1025f757f3fSDimitry Andric #define lFromEVEX4of4(evex) bitFromOffset5(evex) 1035f757f3fSDimitry Andric #define bFromEVEX4of4(evex) bitFromOffset4(evex) 1045f757f3fSDimitry Andric #define v2FromEVEX4of4(evex) invertedBitFromOffset3(evex) 1055f757f3fSDimitry Andric #define aaaFromEVEX4of4(evex) threeBitsFromOffset0(evex) 106647cbc5dSDimitry Andric #define nfFromEVEX4of4(evex) bitFromOffset2(evex) 1070b57cec5SDimitry Andric 1080b57cec5SDimitry Andric // These enums represent Intel registers for use by the decoder. 1090b57cec5SDimitry Andric #define REGS_8BIT \ 1100b57cec5SDimitry Andric ENTRY(AL) \ 1110b57cec5SDimitry Andric ENTRY(CL) \ 1120b57cec5SDimitry Andric ENTRY(DL) \ 1130b57cec5SDimitry Andric ENTRY(BL) \ 1140b57cec5SDimitry Andric ENTRY(AH) \ 1150b57cec5SDimitry Andric ENTRY(CH) \ 1160b57cec5SDimitry Andric ENTRY(DH) \ 1170b57cec5SDimitry Andric ENTRY(BH) \ 1180b57cec5SDimitry Andric ENTRY(R8B) \ 1190b57cec5SDimitry Andric ENTRY(R9B) \ 1200b57cec5SDimitry Andric ENTRY(R10B) \ 1210b57cec5SDimitry Andric ENTRY(R11B) \ 1220b57cec5SDimitry Andric ENTRY(R12B) \ 1230b57cec5SDimitry Andric ENTRY(R13B) \ 1240b57cec5SDimitry Andric ENTRY(R14B) \ 1250b57cec5SDimitry Andric ENTRY(R15B) \ 1265f757f3fSDimitry Andric ENTRY(R16B) \ 1275f757f3fSDimitry Andric ENTRY(R17B) \ 1285f757f3fSDimitry Andric ENTRY(R18B) \ 1295f757f3fSDimitry Andric ENTRY(R19B) \ 1305f757f3fSDimitry Andric ENTRY(R20B) \ 1315f757f3fSDimitry Andric ENTRY(R21B) \ 1325f757f3fSDimitry Andric ENTRY(R22B) \ 1335f757f3fSDimitry Andric ENTRY(R23B) \ 1345f757f3fSDimitry Andric ENTRY(R24B) \ 1355f757f3fSDimitry Andric ENTRY(R25B) \ 1365f757f3fSDimitry Andric ENTRY(R26B) \ 1375f757f3fSDimitry Andric ENTRY(R27B) \ 1385f757f3fSDimitry Andric ENTRY(R28B) \ 1395f757f3fSDimitry Andric ENTRY(R29B) \ 1405f757f3fSDimitry Andric ENTRY(R30B) \ 1415f757f3fSDimitry Andric ENTRY(R31B) \ 1420b57cec5SDimitry Andric ENTRY(SPL) \ 1430b57cec5SDimitry Andric ENTRY(BPL) \ 1440b57cec5SDimitry Andric ENTRY(SIL) \ 1450b57cec5SDimitry Andric ENTRY(DIL) 1460b57cec5SDimitry Andric 1470b57cec5SDimitry Andric #define EA_BASES_16BIT \ 1480b57cec5SDimitry Andric ENTRY(BX_SI) \ 1490b57cec5SDimitry Andric ENTRY(BX_DI) \ 1500b57cec5SDimitry Andric ENTRY(BP_SI) \ 1510b57cec5SDimitry Andric ENTRY(BP_DI) \ 1520b57cec5SDimitry Andric ENTRY(SI) \ 1530b57cec5SDimitry Andric ENTRY(DI) \ 1540b57cec5SDimitry Andric ENTRY(BP) \ 1550b57cec5SDimitry Andric ENTRY(BX) \ 1560b57cec5SDimitry Andric ENTRY(R8W) \ 1570b57cec5SDimitry Andric ENTRY(R9W) \ 1580b57cec5SDimitry Andric ENTRY(R10W) \ 1590b57cec5SDimitry Andric ENTRY(R11W) \ 1600b57cec5SDimitry Andric ENTRY(R12W) \ 1610b57cec5SDimitry Andric ENTRY(R13W) \ 1620b57cec5SDimitry Andric ENTRY(R14W) \ 1635f757f3fSDimitry Andric ENTRY(R15W) \ 1645f757f3fSDimitry Andric ENTRY(R16W) \ 1655f757f3fSDimitry Andric ENTRY(R17W) \ 1665f757f3fSDimitry Andric ENTRY(R18W) \ 1675f757f3fSDimitry Andric ENTRY(R19W) \ 1685f757f3fSDimitry Andric ENTRY(R20W) \ 1695f757f3fSDimitry Andric ENTRY(R21W) \ 1705f757f3fSDimitry Andric ENTRY(R22W) \ 1715f757f3fSDimitry Andric ENTRY(R23W) \ 1725f757f3fSDimitry Andric ENTRY(R24W) \ 1735f757f3fSDimitry Andric ENTRY(R25W) \ 1745f757f3fSDimitry Andric ENTRY(R26W) \ 1755f757f3fSDimitry Andric ENTRY(R27W) \ 1765f757f3fSDimitry Andric ENTRY(R28W) \ 1775f757f3fSDimitry Andric ENTRY(R29W) \ 1785f757f3fSDimitry Andric ENTRY(R30W) \ 1795f757f3fSDimitry Andric ENTRY(R31W) 1800b57cec5SDimitry Andric 1810b57cec5SDimitry Andric #define REGS_16BIT \ 1820b57cec5SDimitry Andric ENTRY(AX) \ 1830b57cec5SDimitry Andric ENTRY(CX) \ 1840b57cec5SDimitry Andric ENTRY(DX) \ 1850b57cec5SDimitry Andric ENTRY(BX) \ 1860b57cec5SDimitry Andric ENTRY(SP) \ 1870b57cec5SDimitry Andric ENTRY(BP) \ 1880b57cec5SDimitry Andric ENTRY(SI) \ 1890b57cec5SDimitry Andric ENTRY(DI) \ 1900b57cec5SDimitry Andric ENTRY(R8W) \ 1910b57cec5SDimitry Andric ENTRY(R9W) \ 1920b57cec5SDimitry Andric ENTRY(R10W) \ 1930b57cec5SDimitry Andric ENTRY(R11W) \ 1940b57cec5SDimitry Andric ENTRY(R12W) \ 1950b57cec5SDimitry Andric ENTRY(R13W) \ 1960b57cec5SDimitry Andric ENTRY(R14W) \ 1975f757f3fSDimitry Andric ENTRY(R15W) \ 1985f757f3fSDimitry Andric ENTRY(R16W) \ 1995f757f3fSDimitry Andric ENTRY(R17W) \ 2005f757f3fSDimitry Andric ENTRY(R18W) \ 2015f757f3fSDimitry Andric ENTRY(R19W) \ 2025f757f3fSDimitry Andric ENTRY(R20W) \ 2035f757f3fSDimitry Andric ENTRY(R21W) \ 2045f757f3fSDimitry Andric ENTRY(R22W) \ 2055f757f3fSDimitry Andric ENTRY(R23W) \ 2065f757f3fSDimitry Andric ENTRY(R24W) \ 2075f757f3fSDimitry Andric ENTRY(R25W) \ 2085f757f3fSDimitry Andric ENTRY(R26W) \ 2095f757f3fSDimitry Andric ENTRY(R27W) \ 2105f757f3fSDimitry Andric ENTRY(R28W) \ 2115f757f3fSDimitry Andric ENTRY(R29W) \ 2125f757f3fSDimitry Andric ENTRY(R30W) \ 2135f757f3fSDimitry Andric ENTRY(R31W) 2140b57cec5SDimitry Andric 2150b57cec5SDimitry Andric #define EA_BASES_32BIT \ 2160b57cec5SDimitry Andric ENTRY(EAX) \ 2170b57cec5SDimitry Andric ENTRY(ECX) \ 2180b57cec5SDimitry Andric ENTRY(EDX) \ 2190b57cec5SDimitry Andric ENTRY(EBX) \ 2200b57cec5SDimitry Andric ENTRY(sib) \ 2210b57cec5SDimitry Andric ENTRY(EBP) \ 2220b57cec5SDimitry Andric ENTRY(ESI) \ 2230b57cec5SDimitry Andric ENTRY(EDI) \ 2240b57cec5SDimitry Andric ENTRY(R8D) \ 2250b57cec5SDimitry Andric ENTRY(R9D) \ 2260b57cec5SDimitry Andric ENTRY(R10D) \ 2270b57cec5SDimitry Andric ENTRY(R11D) \ 2280b57cec5SDimitry Andric ENTRY(R12D) \ 2290b57cec5SDimitry Andric ENTRY(R13D) \ 2300b57cec5SDimitry Andric ENTRY(R14D) \ 2315f757f3fSDimitry Andric ENTRY(R15D) \ 2325f757f3fSDimitry Andric ENTRY(R16D) \ 2335f757f3fSDimitry Andric ENTRY(R17D) \ 2345f757f3fSDimitry Andric ENTRY(R18D) \ 2355f757f3fSDimitry Andric ENTRY(R19D) \ 2365f757f3fSDimitry Andric ENTRY(R20D) \ 2375f757f3fSDimitry Andric ENTRY(R21D) \ 2385f757f3fSDimitry Andric ENTRY(R22D) \ 2395f757f3fSDimitry Andric ENTRY(R23D) \ 2405f757f3fSDimitry Andric ENTRY(R24D) \ 2415f757f3fSDimitry Andric ENTRY(R25D) \ 2425f757f3fSDimitry Andric ENTRY(R26D) \ 2435f757f3fSDimitry Andric ENTRY(R27D) \ 2445f757f3fSDimitry Andric ENTRY(R28D) \ 2455f757f3fSDimitry Andric ENTRY(R29D) \ 2465f757f3fSDimitry Andric ENTRY(R30D) \ 2475f757f3fSDimitry Andric ENTRY(R31D) 2480b57cec5SDimitry Andric 2490b57cec5SDimitry Andric #define REGS_32BIT \ 2500b57cec5SDimitry Andric ENTRY(EAX) \ 2510b57cec5SDimitry Andric ENTRY(ECX) \ 2520b57cec5SDimitry Andric ENTRY(EDX) \ 2530b57cec5SDimitry Andric ENTRY(EBX) \ 2540b57cec5SDimitry Andric ENTRY(ESP) \ 2550b57cec5SDimitry Andric ENTRY(EBP) \ 2560b57cec5SDimitry Andric ENTRY(ESI) \ 2570b57cec5SDimitry Andric ENTRY(EDI) \ 2580b57cec5SDimitry Andric ENTRY(R8D) \ 2590b57cec5SDimitry Andric ENTRY(R9D) \ 2600b57cec5SDimitry Andric ENTRY(R10D) \ 2610b57cec5SDimitry Andric ENTRY(R11D) \ 2620b57cec5SDimitry Andric ENTRY(R12D) \ 2630b57cec5SDimitry Andric ENTRY(R13D) \ 2640b57cec5SDimitry Andric ENTRY(R14D) \ 2655f757f3fSDimitry Andric ENTRY(R15D) \ 2665f757f3fSDimitry Andric ENTRY(R16D) \ 2675f757f3fSDimitry Andric ENTRY(R17D) \ 2685f757f3fSDimitry Andric ENTRY(R18D) \ 2695f757f3fSDimitry Andric ENTRY(R19D) \ 2705f757f3fSDimitry Andric ENTRY(R20D) \ 2715f757f3fSDimitry Andric ENTRY(R21D) \ 2725f757f3fSDimitry Andric ENTRY(R22D) \ 2735f757f3fSDimitry Andric ENTRY(R23D) \ 2745f757f3fSDimitry Andric ENTRY(R24D) \ 2755f757f3fSDimitry Andric ENTRY(R25D) \ 2765f757f3fSDimitry Andric ENTRY(R26D) \ 2775f757f3fSDimitry Andric ENTRY(R27D) \ 2785f757f3fSDimitry Andric ENTRY(R28D) \ 2795f757f3fSDimitry Andric ENTRY(R29D) \ 2805f757f3fSDimitry Andric ENTRY(R30D) \ 2815f757f3fSDimitry Andric ENTRY(R31D) 2820b57cec5SDimitry Andric 2830b57cec5SDimitry Andric #define EA_BASES_64BIT \ 2840b57cec5SDimitry Andric ENTRY(RAX) \ 2850b57cec5SDimitry Andric ENTRY(RCX) \ 2860b57cec5SDimitry Andric ENTRY(RDX) \ 2870b57cec5SDimitry Andric ENTRY(RBX) \ 2880b57cec5SDimitry Andric ENTRY(sib64) \ 2890b57cec5SDimitry Andric ENTRY(RBP) \ 2900b57cec5SDimitry Andric ENTRY(RSI) \ 2910b57cec5SDimitry Andric ENTRY(RDI) \ 2920b57cec5SDimitry Andric ENTRY(R8) \ 2930b57cec5SDimitry Andric ENTRY(R9) \ 2940b57cec5SDimitry Andric ENTRY(R10) \ 2950b57cec5SDimitry Andric ENTRY(R11) \ 2960b57cec5SDimitry Andric ENTRY(R12) \ 2970b57cec5SDimitry Andric ENTRY(R13) \ 2980b57cec5SDimitry Andric ENTRY(R14) \ 2995f757f3fSDimitry Andric ENTRY(R15) \ 3005f757f3fSDimitry Andric ENTRY(R16) \ 3015f757f3fSDimitry Andric ENTRY(R17) \ 3025f757f3fSDimitry Andric ENTRY(R18) \ 3035f757f3fSDimitry Andric ENTRY(R19) \ 3045f757f3fSDimitry Andric ENTRY(R20) \ 3055f757f3fSDimitry Andric ENTRY(R21) \ 3065f757f3fSDimitry Andric ENTRY(R22) \ 3075f757f3fSDimitry Andric ENTRY(R23) \ 3085f757f3fSDimitry Andric ENTRY(R24) \ 3095f757f3fSDimitry Andric ENTRY(R25) \ 3105f757f3fSDimitry Andric ENTRY(R26) \ 3115f757f3fSDimitry Andric ENTRY(R27) \ 3125f757f3fSDimitry Andric ENTRY(R28) \ 3135f757f3fSDimitry Andric ENTRY(R29) \ 3145f757f3fSDimitry Andric ENTRY(R30) \ 3155f757f3fSDimitry Andric ENTRY(R31) 3160b57cec5SDimitry Andric 3170b57cec5SDimitry Andric #define REGS_64BIT \ 3180b57cec5SDimitry Andric ENTRY(RAX) \ 3190b57cec5SDimitry Andric ENTRY(RCX) \ 3200b57cec5SDimitry Andric ENTRY(RDX) \ 3210b57cec5SDimitry Andric ENTRY(RBX) \ 3220b57cec5SDimitry Andric ENTRY(RSP) \ 3230b57cec5SDimitry Andric ENTRY(RBP) \ 3240b57cec5SDimitry Andric ENTRY(RSI) \ 3250b57cec5SDimitry Andric ENTRY(RDI) \ 3260b57cec5SDimitry Andric ENTRY(R8) \ 3270b57cec5SDimitry Andric ENTRY(R9) \ 3280b57cec5SDimitry Andric ENTRY(R10) \ 3290b57cec5SDimitry Andric ENTRY(R11) \ 3300b57cec5SDimitry Andric ENTRY(R12) \ 3310b57cec5SDimitry Andric ENTRY(R13) \ 3320b57cec5SDimitry Andric ENTRY(R14) \ 3335f757f3fSDimitry Andric ENTRY(R15) \ 3345f757f3fSDimitry Andric ENTRY(R16) \ 3355f757f3fSDimitry Andric ENTRY(R17) \ 3365f757f3fSDimitry Andric ENTRY(R18) \ 3375f757f3fSDimitry Andric ENTRY(R19) \ 3385f757f3fSDimitry Andric ENTRY(R20) \ 3395f757f3fSDimitry Andric ENTRY(R21) \ 3405f757f3fSDimitry Andric ENTRY(R22) \ 3415f757f3fSDimitry Andric ENTRY(R23) \ 3425f757f3fSDimitry Andric ENTRY(R24) \ 3435f757f3fSDimitry Andric ENTRY(R25) \ 3445f757f3fSDimitry Andric ENTRY(R26) \ 3455f757f3fSDimitry Andric ENTRY(R27) \ 3465f757f3fSDimitry Andric ENTRY(R28) \ 3475f757f3fSDimitry Andric ENTRY(R29) \ 3485f757f3fSDimitry Andric ENTRY(R30) \ 3495f757f3fSDimitry Andric ENTRY(R31) 3500b57cec5SDimitry Andric 3510b57cec5SDimitry Andric #define REGS_MMX \ 3520b57cec5SDimitry Andric ENTRY(MM0) \ 3530b57cec5SDimitry Andric ENTRY(MM1) \ 3540b57cec5SDimitry Andric ENTRY(MM2) \ 3550b57cec5SDimitry Andric ENTRY(MM3) \ 3560b57cec5SDimitry Andric ENTRY(MM4) \ 3570b57cec5SDimitry Andric ENTRY(MM5) \ 3580b57cec5SDimitry Andric ENTRY(MM6) \ 3590b57cec5SDimitry Andric ENTRY(MM7) 3600b57cec5SDimitry Andric 3610b57cec5SDimitry Andric #define REGS_XMM \ 3620b57cec5SDimitry Andric ENTRY(XMM0) \ 3630b57cec5SDimitry Andric ENTRY(XMM1) \ 3640b57cec5SDimitry Andric ENTRY(XMM2) \ 3650b57cec5SDimitry Andric ENTRY(XMM3) \ 3660b57cec5SDimitry Andric ENTRY(XMM4) \ 3670b57cec5SDimitry Andric ENTRY(XMM5) \ 3680b57cec5SDimitry Andric ENTRY(XMM6) \ 3690b57cec5SDimitry Andric ENTRY(XMM7) \ 3700b57cec5SDimitry Andric ENTRY(XMM8) \ 3710b57cec5SDimitry Andric ENTRY(XMM9) \ 3720b57cec5SDimitry Andric ENTRY(XMM10) \ 3730b57cec5SDimitry Andric ENTRY(XMM11) \ 3740b57cec5SDimitry Andric ENTRY(XMM12) \ 3750b57cec5SDimitry Andric ENTRY(XMM13) \ 3760b57cec5SDimitry Andric ENTRY(XMM14) \ 3770b57cec5SDimitry Andric ENTRY(XMM15) \ 3780b57cec5SDimitry Andric ENTRY(XMM16) \ 3790b57cec5SDimitry Andric ENTRY(XMM17) \ 3800b57cec5SDimitry Andric ENTRY(XMM18) \ 3810b57cec5SDimitry Andric ENTRY(XMM19) \ 3820b57cec5SDimitry Andric ENTRY(XMM20) \ 3830b57cec5SDimitry Andric ENTRY(XMM21) \ 3840b57cec5SDimitry Andric ENTRY(XMM22) \ 3850b57cec5SDimitry Andric ENTRY(XMM23) \ 3860b57cec5SDimitry Andric ENTRY(XMM24) \ 3870b57cec5SDimitry Andric ENTRY(XMM25) \ 3880b57cec5SDimitry Andric ENTRY(XMM26) \ 3890b57cec5SDimitry Andric ENTRY(XMM27) \ 3900b57cec5SDimitry Andric ENTRY(XMM28) \ 3910b57cec5SDimitry Andric ENTRY(XMM29) \ 3920b57cec5SDimitry Andric ENTRY(XMM30) \ 3930b57cec5SDimitry Andric ENTRY(XMM31) 3940b57cec5SDimitry Andric 3950b57cec5SDimitry Andric #define REGS_YMM \ 3960b57cec5SDimitry Andric ENTRY(YMM0) \ 3970b57cec5SDimitry Andric ENTRY(YMM1) \ 3980b57cec5SDimitry Andric ENTRY(YMM2) \ 3990b57cec5SDimitry Andric ENTRY(YMM3) \ 4000b57cec5SDimitry Andric ENTRY(YMM4) \ 4010b57cec5SDimitry Andric ENTRY(YMM5) \ 4020b57cec5SDimitry Andric ENTRY(YMM6) \ 4030b57cec5SDimitry Andric ENTRY(YMM7) \ 4040b57cec5SDimitry Andric ENTRY(YMM8) \ 4050b57cec5SDimitry Andric ENTRY(YMM9) \ 4060b57cec5SDimitry Andric ENTRY(YMM10) \ 4070b57cec5SDimitry Andric ENTRY(YMM11) \ 4080b57cec5SDimitry Andric ENTRY(YMM12) \ 4090b57cec5SDimitry Andric ENTRY(YMM13) \ 4100b57cec5SDimitry Andric ENTRY(YMM14) \ 4110b57cec5SDimitry Andric ENTRY(YMM15) \ 4120b57cec5SDimitry Andric ENTRY(YMM16) \ 4130b57cec5SDimitry Andric ENTRY(YMM17) \ 4140b57cec5SDimitry Andric ENTRY(YMM18) \ 4150b57cec5SDimitry Andric ENTRY(YMM19) \ 4160b57cec5SDimitry Andric ENTRY(YMM20) \ 4170b57cec5SDimitry Andric ENTRY(YMM21) \ 4180b57cec5SDimitry Andric ENTRY(YMM22) \ 4190b57cec5SDimitry Andric ENTRY(YMM23) \ 4200b57cec5SDimitry Andric ENTRY(YMM24) \ 4210b57cec5SDimitry Andric ENTRY(YMM25) \ 4220b57cec5SDimitry Andric ENTRY(YMM26) \ 4230b57cec5SDimitry Andric ENTRY(YMM27) \ 4240b57cec5SDimitry Andric ENTRY(YMM28) \ 4250b57cec5SDimitry Andric ENTRY(YMM29) \ 4260b57cec5SDimitry Andric ENTRY(YMM30) \ 4270b57cec5SDimitry Andric ENTRY(YMM31) 4280b57cec5SDimitry Andric 4290b57cec5SDimitry Andric #define REGS_ZMM \ 4300b57cec5SDimitry Andric ENTRY(ZMM0) \ 4310b57cec5SDimitry Andric ENTRY(ZMM1) \ 4320b57cec5SDimitry Andric ENTRY(ZMM2) \ 4330b57cec5SDimitry Andric ENTRY(ZMM3) \ 4340b57cec5SDimitry Andric ENTRY(ZMM4) \ 4350b57cec5SDimitry Andric ENTRY(ZMM5) \ 4360b57cec5SDimitry Andric ENTRY(ZMM6) \ 4370b57cec5SDimitry Andric ENTRY(ZMM7) \ 4380b57cec5SDimitry Andric ENTRY(ZMM8) \ 4390b57cec5SDimitry Andric ENTRY(ZMM9) \ 4400b57cec5SDimitry Andric ENTRY(ZMM10) \ 4410b57cec5SDimitry Andric ENTRY(ZMM11) \ 4420b57cec5SDimitry Andric ENTRY(ZMM12) \ 4430b57cec5SDimitry Andric ENTRY(ZMM13) \ 4440b57cec5SDimitry Andric ENTRY(ZMM14) \ 4450b57cec5SDimitry Andric ENTRY(ZMM15) \ 4460b57cec5SDimitry Andric ENTRY(ZMM16) \ 4470b57cec5SDimitry Andric ENTRY(ZMM17) \ 4480b57cec5SDimitry Andric ENTRY(ZMM18) \ 4490b57cec5SDimitry Andric ENTRY(ZMM19) \ 4500b57cec5SDimitry Andric ENTRY(ZMM20) \ 4510b57cec5SDimitry Andric ENTRY(ZMM21) \ 4520b57cec5SDimitry Andric ENTRY(ZMM22) \ 4530b57cec5SDimitry Andric ENTRY(ZMM23) \ 4540b57cec5SDimitry Andric ENTRY(ZMM24) \ 4550b57cec5SDimitry Andric ENTRY(ZMM25) \ 4560b57cec5SDimitry Andric ENTRY(ZMM26) \ 4570b57cec5SDimitry Andric ENTRY(ZMM27) \ 4580b57cec5SDimitry Andric ENTRY(ZMM28) \ 4590b57cec5SDimitry Andric ENTRY(ZMM29) \ 4600b57cec5SDimitry Andric ENTRY(ZMM30) \ 4610b57cec5SDimitry Andric ENTRY(ZMM31) 4620b57cec5SDimitry Andric 4630b57cec5SDimitry Andric #define REGS_MASKS \ 4640b57cec5SDimitry Andric ENTRY(K0) \ 4650b57cec5SDimitry Andric ENTRY(K1) \ 4660b57cec5SDimitry Andric ENTRY(K2) \ 4670b57cec5SDimitry Andric ENTRY(K3) \ 4680b57cec5SDimitry Andric ENTRY(K4) \ 4690b57cec5SDimitry Andric ENTRY(K5) \ 4700b57cec5SDimitry Andric ENTRY(K6) \ 4710b57cec5SDimitry Andric ENTRY(K7) 4720b57cec5SDimitry Andric 4730b57cec5SDimitry Andric #define REGS_MASK_PAIRS \ 4740b57cec5SDimitry Andric ENTRY(K0_K1) \ 4750b57cec5SDimitry Andric ENTRY(K2_K3) \ 4760b57cec5SDimitry Andric ENTRY(K4_K5) \ 4770b57cec5SDimitry Andric ENTRY(K6_K7) 4780b57cec5SDimitry Andric 4790b57cec5SDimitry Andric #define REGS_SEGMENT \ 4800b57cec5SDimitry Andric ENTRY(ES) \ 4810b57cec5SDimitry Andric ENTRY(CS) \ 4820b57cec5SDimitry Andric ENTRY(SS) \ 4830b57cec5SDimitry Andric ENTRY(DS) \ 4840b57cec5SDimitry Andric ENTRY(FS) \ 4850b57cec5SDimitry Andric ENTRY(GS) 4860b57cec5SDimitry Andric 4870b57cec5SDimitry Andric #define REGS_DEBUG \ 4880b57cec5SDimitry Andric ENTRY(DR0) \ 4890b57cec5SDimitry Andric ENTRY(DR1) \ 4900b57cec5SDimitry Andric ENTRY(DR2) \ 4910b57cec5SDimitry Andric ENTRY(DR3) \ 4920b57cec5SDimitry Andric ENTRY(DR4) \ 4930b57cec5SDimitry Andric ENTRY(DR5) \ 4940b57cec5SDimitry Andric ENTRY(DR6) \ 4950b57cec5SDimitry Andric ENTRY(DR7) \ 4960b57cec5SDimitry Andric ENTRY(DR8) \ 4970b57cec5SDimitry Andric ENTRY(DR9) \ 4980b57cec5SDimitry Andric ENTRY(DR10) \ 4990b57cec5SDimitry Andric ENTRY(DR11) \ 5000b57cec5SDimitry Andric ENTRY(DR12) \ 5010b57cec5SDimitry Andric ENTRY(DR13) \ 5020b57cec5SDimitry Andric ENTRY(DR14) \ 5030b57cec5SDimitry Andric ENTRY(DR15) 5040b57cec5SDimitry Andric 5050b57cec5SDimitry Andric #define REGS_CONTROL \ 5060b57cec5SDimitry Andric ENTRY(CR0) \ 5070b57cec5SDimitry Andric ENTRY(CR1) \ 5080b57cec5SDimitry Andric ENTRY(CR2) \ 5090b57cec5SDimitry Andric ENTRY(CR3) \ 5100b57cec5SDimitry Andric ENTRY(CR4) \ 5110b57cec5SDimitry Andric ENTRY(CR5) \ 5120b57cec5SDimitry Andric ENTRY(CR6) \ 5130b57cec5SDimitry Andric ENTRY(CR7) \ 5140b57cec5SDimitry Andric ENTRY(CR8) \ 5150b57cec5SDimitry Andric ENTRY(CR9) \ 5160b57cec5SDimitry Andric ENTRY(CR10) \ 5170b57cec5SDimitry Andric ENTRY(CR11) \ 5180b57cec5SDimitry Andric ENTRY(CR12) \ 5190b57cec5SDimitry Andric ENTRY(CR13) \ 5200b57cec5SDimitry Andric ENTRY(CR14) \ 5210b57cec5SDimitry Andric ENTRY(CR15) 5220b57cec5SDimitry Andric 5235ffd83dbSDimitry Andric #undef REGS_TMM 5245ffd83dbSDimitry Andric #define REGS_TMM \ 5255ffd83dbSDimitry Andric ENTRY(TMM0) \ 5265ffd83dbSDimitry Andric ENTRY(TMM1) \ 5275ffd83dbSDimitry Andric ENTRY(TMM2) \ 5285ffd83dbSDimitry Andric ENTRY(TMM3) \ 5295ffd83dbSDimitry Andric ENTRY(TMM4) \ 5305ffd83dbSDimitry Andric ENTRY(TMM5) \ 5315ffd83dbSDimitry Andric ENTRY(TMM6) \ 5325ffd83dbSDimitry Andric ENTRY(TMM7) 5335ffd83dbSDimitry Andric 5340b57cec5SDimitry Andric #define ALL_EA_BASES \ 5350b57cec5SDimitry Andric EA_BASES_16BIT \ 5360b57cec5SDimitry Andric EA_BASES_32BIT \ 5370b57cec5SDimitry Andric EA_BASES_64BIT 5380b57cec5SDimitry Andric 5390b57cec5SDimitry Andric #define ALL_SIB_BASES \ 5400b57cec5SDimitry Andric REGS_32BIT \ 5410b57cec5SDimitry Andric REGS_64BIT 5420b57cec5SDimitry Andric 5430b57cec5SDimitry Andric #define ALL_REGS \ 5440b57cec5SDimitry Andric REGS_8BIT \ 5450b57cec5SDimitry Andric REGS_16BIT \ 5460b57cec5SDimitry Andric REGS_32BIT \ 5470b57cec5SDimitry Andric REGS_64BIT \ 5480b57cec5SDimitry Andric REGS_MMX \ 5490b57cec5SDimitry Andric REGS_XMM \ 5500b57cec5SDimitry Andric REGS_YMM \ 5510b57cec5SDimitry Andric REGS_ZMM \ 5520b57cec5SDimitry Andric REGS_MASKS \ 5530b57cec5SDimitry Andric REGS_MASK_PAIRS \ 5540b57cec5SDimitry Andric REGS_SEGMENT \ 5550b57cec5SDimitry Andric REGS_DEBUG \ 5560b57cec5SDimitry Andric REGS_CONTROL \ 5575ffd83dbSDimitry Andric REGS_TMM \ 5580b57cec5SDimitry Andric ENTRY(RIP) 5590b57cec5SDimitry Andric 5600b57cec5SDimitry Andric /// All possible values of the base field for effective-address 5610b57cec5SDimitry Andric /// computations, a.k.a. the Mod and R/M fields of the ModR/M byte. 5620b57cec5SDimitry Andric /// We distinguish between bases (EA_BASE_*) and registers that just happen 5630b57cec5SDimitry Andric /// to be referred to when Mod == 0b11 (EA_REG_*). 5640b57cec5SDimitry Andric enum EABase { 5650b57cec5SDimitry Andric EA_BASE_NONE, 5660b57cec5SDimitry Andric #define ENTRY(x) EA_BASE_##x, 5670b57cec5SDimitry Andric ALL_EA_BASES 5680b57cec5SDimitry Andric #undef ENTRY 5690b57cec5SDimitry Andric #define ENTRY(x) EA_REG_##x, 5700b57cec5SDimitry Andric ALL_REGS 5710b57cec5SDimitry Andric #undef ENTRY 5720b57cec5SDimitry Andric EA_max 5730b57cec5SDimitry Andric }; 5740b57cec5SDimitry Andric 5750b57cec5SDimitry Andric /// All possible values of the SIB index field. 5760b57cec5SDimitry Andric /// borrows entries from ALL_EA_BASES with the special case that 5770b57cec5SDimitry Andric /// sib is synonymous with NONE. 5780b57cec5SDimitry Andric /// Vector SIB: index can be XMM or YMM. 5790b57cec5SDimitry Andric enum SIBIndex { 5800b57cec5SDimitry Andric SIB_INDEX_NONE, 5810b57cec5SDimitry Andric #define ENTRY(x) SIB_INDEX_##x, 5820b57cec5SDimitry Andric ALL_EA_BASES 5830b57cec5SDimitry Andric REGS_XMM 5840b57cec5SDimitry Andric REGS_YMM 5850b57cec5SDimitry Andric REGS_ZMM 5860b57cec5SDimitry Andric #undef ENTRY 5870b57cec5SDimitry Andric SIB_INDEX_max 5880b57cec5SDimitry Andric }; 5890b57cec5SDimitry Andric 5900b57cec5SDimitry Andric /// All possible values of the SIB base field. 5910b57cec5SDimitry Andric enum SIBBase { 5920b57cec5SDimitry Andric SIB_BASE_NONE, 5930b57cec5SDimitry Andric #define ENTRY(x) SIB_BASE_##x, 5940b57cec5SDimitry Andric ALL_SIB_BASES 5950b57cec5SDimitry Andric #undef ENTRY 5960b57cec5SDimitry Andric SIB_BASE_max 5970b57cec5SDimitry Andric }; 5980b57cec5SDimitry Andric 5990b57cec5SDimitry Andric /// Possible displacement types for effective-address computations. 600480093f4SDimitry Andric enum EADisplacement { 6010b57cec5SDimitry Andric EA_DISP_NONE, 6020b57cec5SDimitry Andric EA_DISP_8, 6030b57cec5SDimitry Andric EA_DISP_16, 6040b57cec5SDimitry Andric EA_DISP_32 605480093f4SDimitry Andric }; 6060b57cec5SDimitry Andric 6070b57cec5SDimitry Andric /// All possible values of the reg field in the ModR/M byte. 6080b57cec5SDimitry Andric enum Reg { 6090b57cec5SDimitry Andric #define ENTRY(x) MODRM_REG_##x, 6100b57cec5SDimitry Andric ALL_REGS 6110b57cec5SDimitry Andric #undef ENTRY 6120b57cec5SDimitry Andric MODRM_REG_max 6130b57cec5SDimitry Andric }; 6140b57cec5SDimitry Andric 6150b57cec5SDimitry Andric /// All possible segment overrides. 6160b57cec5SDimitry Andric enum SegmentOverride { 6170b57cec5SDimitry Andric SEG_OVERRIDE_NONE, 6180b57cec5SDimitry Andric SEG_OVERRIDE_CS, 6190b57cec5SDimitry Andric SEG_OVERRIDE_SS, 6200b57cec5SDimitry Andric SEG_OVERRIDE_DS, 6210b57cec5SDimitry Andric SEG_OVERRIDE_ES, 6220b57cec5SDimitry Andric SEG_OVERRIDE_FS, 6230b57cec5SDimitry Andric SEG_OVERRIDE_GS, 6240b57cec5SDimitry Andric SEG_OVERRIDE_max 6250b57cec5SDimitry Andric }; 6260b57cec5SDimitry Andric 6270b57cec5SDimitry Andric /// Possible values for the VEX.m-mmmm field 6280b57cec5SDimitry Andric enum VEXLeadingOpcodeByte { 6290b57cec5SDimitry Andric VEX_LOB_0F = 0x1, 6300b57cec5SDimitry Andric VEX_LOB_0F38 = 0x2, 631349cc55cSDimitry Andric VEX_LOB_0F3A = 0x3, 6325f757f3fSDimitry Andric VEX_LOB_MAP4 = 0x4, 633349cc55cSDimitry Andric VEX_LOB_MAP5 = 0x5, 6345f757f3fSDimitry Andric VEX_LOB_MAP6 = 0x6, 6355f757f3fSDimitry Andric VEX_LOB_MAP7 = 0x7 6360b57cec5SDimitry Andric }; 6370b57cec5SDimitry Andric 6380b57cec5SDimitry Andric enum XOPMapSelect { 6390b57cec5SDimitry Andric XOP_MAP_SELECT_8 = 0x8, 6400b57cec5SDimitry Andric XOP_MAP_SELECT_9 = 0x9, 6410b57cec5SDimitry Andric XOP_MAP_SELECT_A = 0xA 6420b57cec5SDimitry Andric }; 6430b57cec5SDimitry Andric 6440b57cec5SDimitry Andric /// Possible values for the VEX.pp/EVEX.pp field 6450b57cec5SDimitry Andric enum VEXPrefixCode { 6460b57cec5SDimitry Andric VEX_PREFIX_NONE = 0x0, 6470b57cec5SDimitry Andric VEX_PREFIX_66 = 0x1, 6480b57cec5SDimitry Andric VEX_PREFIX_F3 = 0x2, 6490b57cec5SDimitry Andric VEX_PREFIX_F2 = 0x3 6500b57cec5SDimitry Andric }; 6510b57cec5SDimitry Andric 6520b57cec5SDimitry Andric enum VectorExtensionType { 6530b57cec5SDimitry Andric TYPE_NO_VEX_XOP = 0x0, 6540b57cec5SDimitry Andric TYPE_VEX_2B = 0x1, 6550b57cec5SDimitry Andric TYPE_VEX_3B = 0x2, 6560b57cec5SDimitry Andric TYPE_EVEX = 0x3, 6570b57cec5SDimitry Andric TYPE_XOP = 0x4 6580b57cec5SDimitry Andric }; 6590b57cec5SDimitry Andric 6600b57cec5SDimitry Andric /// The specification for how to extract and interpret a full instruction and 6610b57cec5SDimitry Andric /// its operands. 6620b57cec5SDimitry Andric struct InstructionSpecifier { 6630b57cec5SDimitry Andric uint16_t operands; 6640b57cec5SDimitry Andric }; 6650b57cec5SDimitry Andric 6660b57cec5SDimitry Andric /// The x86 internal instruction, which is produced by the decoder. 6670b57cec5SDimitry Andric struct InternalInstruction { 6680b57cec5SDimitry Andric // Opaque value passed to the reader 669480093f4SDimitry Andric llvm::ArrayRef<uint8_t> bytes; 6700b57cec5SDimitry Andric // The address of the next byte to read via the reader 6710b57cec5SDimitry Andric uint64_t readerCursor; 6720b57cec5SDimitry Andric 6730b57cec5SDimitry Andric // General instruction information 6740b57cec5SDimitry Andric 6750b57cec5SDimitry Andric // The mode to disassemble for (64-bit, protected, real) 6760b57cec5SDimitry Andric DisassemblerMode mode; 6770b57cec5SDimitry Andric // The start of the instruction, usable with the reader 6780b57cec5SDimitry Andric uint64_t startLocation; 6790b57cec5SDimitry Andric // The length of the instruction, in bytes 6800b57cec5SDimitry Andric size_t length; 6810b57cec5SDimitry Andric 6820b57cec5SDimitry Andric // Prefix state 6830b57cec5SDimitry Andric 6840b57cec5SDimitry Andric // The possible mandatory prefix 6850b57cec5SDimitry Andric uint8_t mandatoryPrefix; 6860b57cec5SDimitry Andric // The value of the vector extension prefix(EVEX/VEX/XOP), if present 6870b57cec5SDimitry Andric uint8_t vectorExtensionPrefix[4]; 6880b57cec5SDimitry Andric // The type of the vector extension prefix 6890b57cec5SDimitry Andric VectorExtensionType vectorExtensionType; 6905f757f3fSDimitry Andric // The value of the REX2 prefix, if present 6915f757f3fSDimitry Andric uint8_t rex2ExtensionPrefix[2]; 6920b57cec5SDimitry Andric // The value of the REX prefix, if present 6930b57cec5SDimitry Andric uint8_t rexPrefix; 6940b57cec5SDimitry Andric // The segment override type 6950b57cec5SDimitry Andric SegmentOverride segmentOverride; 6960b57cec5SDimitry Andric // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease 6970b57cec5SDimitry Andric bool xAcquireRelease; 6980b57cec5SDimitry Andric 6990b57cec5SDimitry Andric // Address-size override 7000b57cec5SDimitry Andric bool hasAdSize; 7010b57cec5SDimitry Andric // Operand-size override 7020b57cec5SDimitry Andric bool hasOpSize; 7030b57cec5SDimitry Andric // Lock prefix 7040b57cec5SDimitry Andric bool hasLockPrefix; 7050b57cec5SDimitry Andric // The repeat prefix if any 7060b57cec5SDimitry Andric uint8_t repeatPrefix; 7070b57cec5SDimitry Andric 7080b57cec5SDimitry Andric // Sizes of various critical pieces of data, in bytes 7090b57cec5SDimitry Andric uint8_t registerSize; 7100b57cec5SDimitry Andric uint8_t addressSize; 7110b57cec5SDimitry Andric uint8_t displacementSize; 7120b57cec5SDimitry Andric uint8_t immediateSize; 7130b57cec5SDimitry Andric 7140b57cec5SDimitry Andric // Offsets from the start of the instruction to the pieces of data, which is 7150b57cec5SDimitry Andric // needed to find relocation entries for adding symbolic operands. 7160b57cec5SDimitry Andric uint8_t displacementOffset; 7170b57cec5SDimitry Andric uint8_t immediateOffset; 7180b57cec5SDimitry Andric 7190b57cec5SDimitry Andric // opcode state 7200b57cec5SDimitry Andric 7210b57cec5SDimitry Andric // The last byte of the opcode, not counting any ModR/M extension 7220b57cec5SDimitry Andric uint8_t opcode; 7230b57cec5SDimitry Andric 7240b57cec5SDimitry Andric // decode state 7250b57cec5SDimitry Andric 7260b57cec5SDimitry Andric // The type of opcode, used for indexing into the array of decode tables 7270b57cec5SDimitry Andric OpcodeType opcodeType; 7280b57cec5SDimitry Andric // The instruction ID, extracted from the decode table 7290b57cec5SDimitry Andric uint16_t instructionID; 7300b57cec5SDimitry Andric // The specifier for the instruction, from the instruction info table 7310b57cec5SDimitry Andric const InstructionSpecifier *spec; 7320b57cec5SDimitry Andric 7330b57cec5SDimitry Andric // state for additional bytes, consumed during operand decode. Pattern: 7340b57cec5SDimitry Andric // consumed___ indicates that the byte was already consumed and does not 7350b57cec5SDimitry Andric // need to be consumed again. 7360b57cec5SDimitry Andric 7370b57cec5SDimitry Andric // The VEX.vvvv field, which contains a third register operand for some AVX 7380b57cec5SDimitry Andric // instructions. 7390b57cec5SDimitry Andric Reg vvvv; 7400b57cec5SDimitry Andric 7410b57cec5SDimitry Andric // The writemask for AVX-512 instructions which is contained in EVEX.aaa 7420b57cec5SDimitry Andric Reg writemask; 7430b57cec5SDimitry Andric 7440b57cec5SDimitry Andric // The ModR/M byte, which contains most register operands and some portion of 7450b57cec5SDimitry Andric // all memory operands. 7460b57cec5SDimitry Andric bool consumedModRM; 7470b57cec5SDimitry Andric uint8_t modRM; 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andric // The SIB byte, used for more complex 32- or 64-bit memory operands 7500b57cec5SDimitry Andric uint8_t sib; 7510b57cec5SDimitry Andric 7520b57cec5SDimitry Andric // The displacement, used for memory operands 7530b57cec5SDimitry Andric int32_t displacement; 7540b57cec5SDimitry Andric 7550b57cec5SDimitry Andric // Immediates. There can be two in some cases 7560b57cec5SDimitry Andric uint8_t numImmediatesConsumed; 7570b57cec5SDimitry Andric uint8_t numImmediatesTranslated; 7580b57cec5SDimitry Andric uint64_t immediates[2]; 7590b57cec5SDimitry Andric 7600b57cec5SDimitry Andric // A register or immediate operand encoded into the opcode 7610b57cec5SDimitry Andric Reg opcodeRegister; 7620b57cec5SDimitry Andric 7630b57cec5SDimitry Andric // Portions of the ModR/M byte 7640b57cec5SDimitry Andric 7650b57cec5SDimitry Andric // These fields determine the allowable values for the ModR/M fields, which 7660b57cec5SDimitry Andric // depend on operand and address widths. 7670b57cec5SDimitry Andric EABase eaRegBase; 7680b57cec5SDimitry Andric Reg regBase; 7690b57cec5SDimitry Andric 7700b57cec5SDimitry Andric // The Mod and R/M fields can encode a base for an effective address, or a 7710b57cec5SDimitry Andric // register. These are separated into two fields here. 7720b57cec5SDimitry Andric EABase eaBase; 7730b57cec5SDimitry Andric EADisplacement eaDisplacement; 7740b57cec5SDimitry Andric // The reg field always encodes a register 7750b57cec5SDimitry Andric Reg reg; 7760b57cec5SDimitry Andric 7770b57cec5SDimitry Andric // SIB state 7780b57cec5SDimitry Andric SIBIndex sibIndexBase; 7790b57cec5SDimitry Andric SIBIndex sibIndex; 7800b57cec5SDimitry Andric uint8_t sibScale; 7810b57cec5SDimitry Andric SIBBase sibBase; 7820b57cec5SDimitry Andric 7830b57cec5SDimitry Andric // Embedded rounding control. 7840b57cec5SDimitry Andric uint8_t RC; 7850b57cec5SDimitry Andric 7860b57cec5SDimitry Andric ArrayRef<OperandSpecifier> operands; 7870b57cec5SDimitry Andric }; 7880b57cec5SDimitry Andric 7890b57cec5SDimitry Andric } // namespace X86Disassembler 7900b57cec5SDimitry Andric } // namespace llvm 7910b57cec5SDimitry Andric 7920b57cec5SDimitry Andric #endif 793