1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86MCTargetDesc.h" 14 #include "TargetInfo/X86TargetInfo.h" 15 #include "X86ATTInstPrinter.h" 16 #include "X86BaseInfo.h" 17 #include "X86IntelInstPrinter.h" 18 #include "X86MCAsmInfo.h" 19 #include "X86TargetStreamer.h" 20 #include "llvm/ADT/APInt.h" 21 #include "llvm/DebugInfo/CodeView/CodeView.h" 22 #include "llvm/MC/MCDwarf.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCStreamer.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/MC/MachineLocation.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/TargetParser/Host.h" 32 #include "llvm/TargetParser/Triple.h" 33 34 using namespace llvm; 35 36 #define GET_REGINFO_MC_DESC 37 #include "X86GenRegisterInfo.inc" 38 39 #define GET_INSTRINFO_MC_DESC 40 #define GET_INSTRINFO_MC_HELPERS 41 #define ENABLE_INSTR_PREDICATE_VERIFIER 42 #include "X86GenInstrInfo.inc" 43 44 #define GET_SUBTARGETINFO_MC_DESC 45 #include "X86GenSubtargetInfo.inc" 46 47 std::string X86_MC::ParseX86Triple(const Triple &TT) { 48 std::string FS; 49 // SSE2 should default to enabled in 64-bit mode, but can be turned off 50 // explicitly. 51 if (TT.isArch64Bit()) 52 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2"; 53 else if (TT.getEnvironment() != Triple::CODE16) 54 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 55 else 56 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 57 58 return FS; 59 } 60 61 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 62 if (TT.getArch() == Triple::x86_64) 63 return DWARFFlavour::X86_64; 64 65 if (TT.isOSDarwin()) 66 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 67 if (TT.isOSCygMing()) 68 // Unsupported by now, just quick fallback 69 return DWARFFlavour::X86_32_Generic; 70 return DWARFFlavour::X86_32_Generic; 71 } 72 73 bool X86_MC::hasLockPrefix(const MCInst &MI) { 74 return MI.getFlags() & X86::IP_HAS_LOCK; 75 } 76 77 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { 78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); 80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; 81 82 return (Base.isReg() && Base.getReg() != 0 && RC.contains(Base.getReg())) || 83 (Index.isReg() && Index.getReg() != 0 && RC.contains(Index.getReg())); 84 } 85 86 bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op, 87 const MCSubtargetInfo &STI) { 88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); 90 91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && Base.getReg() == 0 && 92 Index.isReg() && Index.getReg() == 0) 93 return true; 94 return isMemOperand(MI, Op, X86::GR16RegClassID); 95 } 96 97 bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) { 98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); 100 if (Base.isReg() && Base.getReg() == X86::EIP) { 101 assert(Index.isReg() && Index.getReg() == 0 && "Invalid eip-based address"); 102 return true; 103 } 104 if (Index.isReg() && Index.getReg() == X86::EIZ) 105 return true; 106 return isMemOperand(MI, Op, X86::GR32RegClassID); 107 } 108 109 #ifndef NDEBUG 110 bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) { 111 return isMemOperand(MI, Op, X86::GR64RegClassID); 112 } 113 #endif 114 115 bool X86_MC::needsAddressSizeOverride(const MCInst &MI, 116 const MCSubtargetInfo &STI, 117 int MemoryOperand, uint64_t TSFlags) { 118 uint64_t AdSize = TSFlags & X86II::AdSizeMask; 119 bool Is16BitMode = STI.hasFeature(X86::Is16Bit); 120 bool Is32BitMode = STI.hasFeature(X86::Is32Bit); 121 bool Is64BitMode = STI.hasFeature(X86::Is64Bit); 122 if ((Is16BitMode && AdSize == X86II::AdSize32) || 123 (Is32BitMode && AdSize == X86II::AdSize16) || 124 (Is64BitMode && AdSize == X86II::AdSize32)) 125 return true; 126 uint64_t Form = TSFlags & X86II::FormMask; 127 switch (Form) { 128 default: 129 break; 130 case X86II::RawFrmDstSrc: { 131 unsigned siReg = MI.getOperand(1).getReg(); 132 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || 133 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || 134 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && 135 "SI and DI register sizes do not match"); 136 return (!Is32BitMode && siReg == X86::ESI) || 137 (Is32BitMode && siReg == X86::SI); 138 } 139 case X86II::RawFrmSrc: { 140 unsigned siReg = MI.getOperand(0).getReg(); 141 return (!Is32BitMode && siReg == X86::ESI) || 142 (Is32BitMode && siReg == X86::SI); 143 } 144 case X86II::RawFrmDst: { 145 unsigned siReg = MI.getOperand(0).getReg(); 146 return (!Is32BitMode && siReg == X86::EDI) || 147 (Is32BitMode && siReg == X86::DI); 148 } 149 } 150 151 // Determine where the memory operand starts, if present. 152 if (MemoryOperand < 0) 153 return false; 154 155 if (STI.hasFeature(X86::Is64Bit)) { 156 assert(!is16BitMemOperand(MI, MemoryOperand, STI)); 157 return is32BitMemOperand(MI, MemoryOperand); 158 } 159 if (STI.hasFeature(X86::Is32Bit)) { 160 assert(!is64BitMemOperand(MI, MemoryOperand)); 161 return is16BitMemOperand(MI, MemoryOperand, STI); 162 } 163 assert(STI.hasFeature(X86::Is16Bit)); 164 assert(!is64BitMemOperand(MI, MemoryOperand)); 165 return !is16BitMemOperand(MI, MemoryOperand, STI); 166 } 167 168 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 169 // FIXME: TableGen these. 170 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 171 unsigned SEH = MRI->getEncodingValue(Reg); 172 MRI->mapLLVMRegToSEHReg(Reg, SEH); 173 } 174 175 // Mapping from CodeView to MC register id. 176 static const struct { 177 codeview::RegisterId CVReg; 178 MCPhysReg Reg; 179 } RegMap[] = { 180 {codeview::RegisterId::AL, X86::AL}, 181 {codeview::RegisterId::CL, X86::CL}, 182 {codeview::RegisterId::DL, X86::DL}, 183 {codeview::RegisterId::BL, X86::BL}, 184 {codeview::RegisterId::AH, X86::AH}, 185 {codeview::RegisterId::CH, X86::CH}, 186 {codeview::RegisterId::DH, X86::DH}, 187 {codeview::RegisterId::BH, X86::BH}, 188 {codeview::RegisterId::AX, X86::AX}, 189 {codeview::RegisterId::CX, X86::CX}, 190 {codeview::RegisterId::DX, X86::DX}, 191 {codeview::RegisterId::BX, X86::BX}, 192 {codeview::RegisterId::SP, X86::SP}, 193 {codeview::RegisterId::BP, X86::BP}, 194 {codeview::RegisterId::SI, X86::SI}, 195 {codeview::RegisterId::DI, X86::DI}, 196 {codeview::RegisterId::EAX, X86::EAX}, 197 {codeview::RegisterId::ECX, X86::ECX}, 198 {codeview::RegisterId::EDX, X86::EDX}, 199 {codeview::RegisterId::EBX, X86::EBX}, 200 {codeview::RegisterId::ESP, X86::ESP}, 201 {codeview::RegisterId::EBP, X86::EBP}, 202 {codeview::RegisterId::ESI, X86::ESI}, 203 {codeview::RegisterId::EDI, X86::EDI}, 204 205 {codeview::RegisterId::EFLAGS, X86::EFLAGS}, 206 207 {codeview::RegisterId::ST0, X86::ST0}, 208 {codeview::RegisterId::ST1, X86::ST1}, 209 {codeview::RegisterId::ST2, X86::ST2}, 210 {codeview::RegisterId::ST3, X86::ST3}, 211 {codeview::RegisterId::ST4, X86::ST4}, 212 {codeview::RegisterId::ST5, X86::ST5}, 213 {codeview::RegisterId::ST6, X86::ST6}, 214 {codeview::RegisterId::ST7, X86::ST7}, 215 216 {codeview::RegisterId::ST0, X86::FP0}, 217 {codeview::RegisterId::ST1, X86::FP1}, 218 {codeview::RegisterId::ST2, X86::FP2}, 219 {codeview::RegisterId::ST3, X86::FP3}, 220 {codeview::RegisterId::ST4, X86::FP4}, 221 {codeview::RegisterId::ST5, X86::FP5}, 222 {codeview::RegisterId::ST6, X86::FP6}, 223 {codeview::RegisterId::ST7, X86::FP7}, 224 225 {codeview::RegisterId::MM0, X86::MM0}, 226 {codeview::RegisterId::MM1, X86::MM1}, 227 {codeview::RegisterId::MM2, X86::MM2}, 228 {codeview::RegisterId::MM3, X86::MM3}, 229 {codeview::RegisterId::MM4, X86::MM4}, 230 {codeview::RegisterId::MM5, X86::MM5}, 231 {codeview::RegisterId::MM6, X86::MM6}, 232 {codeview::RegisterId::MM7, X86::MM7}, 233 234 {codeview::RegisterId::XMM0, X86::XMM0}, 235 {codeview::RegisterId::XMM1, X86::XMM1}, 236 {codeview::RegisterId::XMM2, X86::XMM2}, 237 {codeview::RegisterId::XMM3, X86::XMM3}, 238 {codeview::RegisterId::XMM4, X86::XMM4}, 239 {codeview::RegisterId::XMM5, X86::XMM5}, 240 {codeview::RegisterId::XMM6, X86::XMM6}, 241 {codeview::RegisterId::XMM7, X86::XMM7}, 242 243 {codeview::RegisterId::XMM8, X86::XMM8}, 244 {codeview::RegisterId::XMM9, X86::XMM9}, 245 {codeview::RegisterId::XMM10, X86::XMM10}, 246 {codeview::RegisterId::XMM11, X86::XMM11}, 247 {codeview::RegisterId::XMM12, X86::XMM12}, 248 {codeview::RegisterId::XMM13, X86::XMM13}, 249 {codeview::RegisterId::XMM14, X86::XMM14}, 250 {codeview::RegisterId::XMM15, X86::XMM15}, 251 252 {codeview::RegisterId::SIL, X86::SIL}, 253 {codeview::RegisterId::DIL, X86::DIL}, 254 {codeview::RegisterId::BPL, X86::BPL}, 255 {codeview::RegisterId::SPL, X86::SPL}, 256 {codeview::RegisterId::RAX, X86::RAX}, 257 {codeview::RegisterId::RBX, X86::RBX}, 258 {codeview::RegisterId::RCX, X86::RCX}, 259 {codeview::RegisterId::RDX, X86::RDX}, 260 {codeview::RegisterId::RSI, X86::RSI}, 261 {codeview::RegisterId::RDI, X86::RDI}, 262 {codeview::RegisterId::RBP, X86::RBP}, 263 {codeview::RegisterId::RSP, X86::RSP}, 264 {codeview::RegisterId::R8, X86::R8}, 265 {codeview::RegisterId::R9, X86::R9}, 266 {codeview::RegisterId::R10, X86::R10}, 267 {codeview::RegisterId::R11, X86::R11}, 268 {codeview::RegisterId::R12, X86::R12}, 269 {codeview::RegisterId::R13, X86::R13}, 270 {codeview::RegisterId::R14, X86::R14}, 271 {codeview::RegisterId::R15, X86::R15}, 272 {codeview::RegisterId::R8B, X86::R8B}, 273 {codeview::RegisterId::R9B, X86::R9B}, 274 {codeview::RegisterId::R10B, X86::R10B}, 275 {codeview::RegisterId::R11B, X86::R11B}, 276 {codeview::RegisterId::R12B, X86::R12B}, 277 {codeview::RegisterId::R13B, X86::R13B}, 278 {codeview::RegisterId::R14B, X86::R14B}, 279 {codeview::RegisterId::R15B, X86::R15B}, 280 {codeview::RegisterId::R8W, X86::R8W}, 281 {codeview::RegisterId::R9W, X86::R9W}, 282 {codeview::RegisterId::R10W, X86::R10W}, 283 {codeview::RegisterId::R11W, X86::R11W}, 284 {codeview::RegisterId::R12W, X86::R12W}, 285 {codeview::RegisterId::R13W, X86::R13W}, 286 {codeview::RegisterId::R14W, X86::R14W}, 287 {codeview::RegisterId::R15W, X86::R15W}, 288 {codeview::RegisterId::R8D, X86::R8D}, 289 {codeview::RegisterId::R9D, X86::R9D}, 290 {codeview::RegisterId::R10D, X86::R10D}, 291 {codeview::RegisterId::R11D, X86::R11D}, 292 {codeview::RegisterId::R12D, X86::R12D}, 293 {codeview::RegisterId::R13D, X86::R13D}, 294 {codeview::RegisterId::R14D, X86::R14D}, 295 {codeview::RegisterId::R15D, X86::R15D}, 296 {codeview::RegisterId::AMD64_YMM0, X86::YMM0}, 297 {codeview::RegisterId::AMD64_YMM1, X86::YMM1}, 298 {codeview::RegisterId::AMD64_YMM2, X86::YMM2}, 299 {codeview::RegisterId::AMD64_YMM3, X86::YMM3}, 300 {codeview::RegisterId::AMD64_YMM4, X86::YMM4}, 301 {codeview::RegisterId::AMD64_YMM5, X86::YMM5}, 302 {codeview::RegisterId::AMD64_YMM6, X86::YMM6}, 303 {codeview::RegisterId::AMD64_YMM7, X86::YMM7}, 304 {codeview::RegisterId::AMD64_YMM8, X86::YMM8}, 305 {codeview::RegisterId::AMD64_YMM9, X86::YMM9}, 306 {codeview::RegisterId::AMD64_YMM10, X86::YMM10}, 307 {codeview::RegisterId::AMD64_YMM11, X86::YMM11}, 308 {codeview::RegisterId::AMD64_YMM12, X86::YMM12}, 309 {codeview::RegisterId::AMD64_YMM13, X86::YMM13}, 310 {codeview::RegisterId::AMD64_YMM14, X86::YMM14}, 311 {codeview::RegisterId::AMD64_YMM15, X86::YMM15}, 312 {codeview::RegisterId::AMD64_YMM16, X86::YMM16}, 313 {codeview::RegisterId::AMD64_YMM17, X86::YMM17}, 314 {codeview::RegisterId::AMD64_YMM18, X86::YMM18}, 315 {codeview::RegisterId::AMD64_YMM19, X86::YMM19}, 316 {codeview::RegisterId::AMD64_YMM20, X86::YMM20}, 317 {codeview::RegisterId::AMD64_YMM21, X86::YMM21}, 318 {codeview::RegisterId::AMD64_YMM22, X86::YMM22}, 319 {codeview::RegisterId::AMD64_YMM23, X86::YMM23}, 320 {codeview::RegisterId::AMD64_YMM24, X86::YMM24}, 321 {codeview::RegisterId::AMD64_YMM25, X86::YMM25}, 322 {codeview::RegisterId::AMD64_YMM26, X86::YMM26}, 323 {codeview::RegisterId::AMD64_YMM27, X86::YMM27}, 324 {codeview::RegisterId::AMD64_YMM28, X86::YMM28}, 325 {codeview::RegisterId::AMD64_YMM29, X86::YMM29}, 326 {codeview::RegisterId::AMD64_YMM30, X86::YMM30}, 327 {codeview::RegisterId::AMD64_YMM31, X86::YMM31}, 328 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0}, 329 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1}, 330 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2}, 331 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3}, 332 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4}, 333 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5}, 334 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6}, 335 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7}, 336 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8}, 337 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9}, 338 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10}, 339 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11}, 340 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12}, 341 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13}, 342 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14}, 343 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15}, 344 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16}, 345 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17}, 346 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18}, 347 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19}, 348 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20}, 349 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21}, 350 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22}, 351 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23}, 352 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24}, 353 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25}, 354 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26}, 355 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27}, 356 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28}, 357 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29}, 358 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30}, 359 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31}, 360 {codeview::RegisterId::AMD64_K0, X86::K0}, 361 {codeview::RegisterId::AMD64_K1, X86::K1}, 362 {codeview::RegisterId::AMD64_K2, X86::K2}, 363 {codeview::RegisterId::AMD64_K3, X86::K3}, 364 {codeview::RegisterId::AMD64_K4, X86::K4}, 365 {codeview::RegisterId::AMD64_K5, X86::K5}, 366 {codeview::RegisterId::AMD64_K6, X86::K6}, 367 {codeview::RegisterId::AMD64_K7, X86::K7}, 368 {codeview::RegisterId::AMD64_XMM16, X86::XMM16}, 369 {codeview::RegisterId::AMD64_XMM17, X86::XMM17}, 370 {codeview::RegisterId::AMD64_XMM18, X86::XMM18}, 371 {codeview::RegisterId::AMD64_XMM19, X86::XMM19}, 372 {codeview::RegisterId::AMD64_XMM20, X86::XMM20}, 373 {codeview::RegisterId::AMD64_XMM21, X86::XMM21}, 374 {codeview::RegisterId::AMD64_XMM22, X86::XMM22}, 375 {codeview::RegisterId::AMD64_XMM23, X86::XMM23}, 376 {codeview::RegisterId::AMD64_XMM24, X86::XMM24}, 377 {codeview::RegisterId::AMD64_XMM25, X86::XMM25}, 378 {codeview::RegisterId::AMD64_XMM26, X86::XMM26}, 379 {codeview::RegisterId::AMD64_XMM27, X86::XMM27}, 380 {codeview::RegisterId::AMD64_XMM28, X86::XMM28}, 381 {codeview::RegisterId::AMD64_XMM29, X86::XMM29}, 382 {codeview::RegisterId::AMD64_XMM30, X86::XMM30}, 383 {codeview::RegisterId::AMD64_XMM31, X86::XMM31}, 384 385 }; 386 for (const auto &I : RegMap) 387 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 388 } 389 390 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 391 StringRef CPU, StringRef FS) { 392 std::string ArchFS = X86_MC::ParseX86Triple(TT); 393 assert(!ArchFS.empty() && "Failed to parse X86 triple"); 394 if (!FS.empty()) 395 ArchFS = (Twine(ArchFS) + "," + FS).str(); 396 397 if (CPU.empty()) 398 CPU = "generic"; 399 400 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS); 401 } 402 403 static MCInstrInfo *createX86MCInstrInfo() { 404 MCInstrInfo *X = new MCInstrInfo(); 405 InitX86MCInstrInfo(X); 406 return X; 407 } 408 409 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 410 unsigned RA = (TT.getArch() == Triple::x86_64) 411 ? X86::RIP // Should have dwarf #16. 412 : X86::EIP; // Should have dwarf #8. 413 414 MCRegisterInfo *X = new MCRegisterInfo(); 415 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 416 X86_MC::getDwarfRegFlavour(TT, true), RA); 417 X86_MC::initLLVMToSEHAndCVRegMapping(X); 418 return X; 419 } 420 421 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 422 const Triple &TheTriple, 423 const MCTargetOptions &Options) { 424 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 425 426 MCAsmInfo *MAI; 427 if (TheTriple.isOSBinFormatMachO()) { 428 if (is64Bit) 429 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 430 else 431 MAI = new X86MCAsmInfoDarwin(TheTriple); 432 } else if (TheTriple.isOSBinFormatELF()) { 433 // Force the use of an ELF container. 434 MAI = new X86ELFMCAsmInfo(TheTriple); 435 } else if (TheTriple.isWindowsMSVCEnvironment() || 436 TheTriple.isWindowsCoreCLREnvironment()) { 437 if (Options.getAssemblyLanguage().equals_insensitive("masm")) 438 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple); 439 else 440 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 441 } else if (TheTriple.isOSCygMing() || 442 TheTriple.isWindowsItaniumEnvironment()) { 443 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 444 } else if (TheTriple.isUEFI()) { 445 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 446 } else { 447 // The default is ELF. 448 MAI = new X86ELFMCAsmInfo(TheTriple); 449 } 450 451 // Initialize initial frame state. 452 // Calculate amount of bytes used for return address storing 453 int stackGrowth = is64Bit ? -8 : -4; 454 455 // Initial state of the frame pointer is esp+stackGrowth. 456 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 457 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( 458 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 459 MAI->addInitialFrameState(Inst); 460 461 // Add return address to move list 462 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 463 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 464 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 465 MAI->addInitialFrameState(Inst2); 466 467 return MAI; 468 } 469 470 static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 471 unsigned SyntaxVariant, 472 const MCAsmInfo &MAI, 473 const MCInstrInfo &MII, 474 const MCRegisterInfo &MRI) { 475 if (SyntaxVariant == 0) 476 return new X86ATTInstPrinter(MAI, MII, MRI); 477 if (SyntaxVariant == 1) 478 return new X86IntelInstPrinter(MAI, MII, MRI); 479 return nullptr; 480 } 481 482 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 483 MCContext &Ctx) { 484 // Default to the stock relocation info. 485 return llvm::createMCRelocationInfo(TheTriple, Ctx); 486 } 487 488 namespace llvm { 489 namespace X86_MC { 490 491 class X86MCInstrAnalysis : public MCInstrAnalysis { 492 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete; 493 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete; 494 virtual ~X86MCInstrAnalysis() = default; 495 496 public: 497 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {} 498 499 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 500 #include "X86GenSubtargetInfo.inc" 501 502 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, 503 APInt &Mask) const override; 504 std::vector<std::pair<uint64_t, uint64_t>> 505 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 506 const Triple &TargetTriple) const override; 507 508 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 509 uint64_t &Target) const override; 510 std::optional<uint64_t> 511 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, 512 uint64_t Addr, uint64_t Size) const override; 513 std::optional<uint64_t> 514 getMemoryOperandRelocationOffset(const MCInst &Inst, 515 uint64_t Size) const override; 516 }; 517 518 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 519 #include "X86GenSubtargetInfo.inc" 520 521 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, 522 const MCInst &Inst, 523 APInt &Mask) const { 524 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 525 unsigned NumDefs = Desc.getNumDefs(); 526 unsigned NumImplicitDefs = Desc.implicit_defs().size(); 527 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs && 528 "Unexpected number of bits in the mask!"); 529 530 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX; 531 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; 532 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP; 533 534 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); 535 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); 536 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); 537 538 auto ClearsSuperReg = [=](unsigned RegID) { 539 // On X86-64, a general purpose integer register is viewed as a 64-bit 540 // register internal to the processor. 541 // An update to the lower 32 bits of a 64 bit integer register is 542 // architecturally defined to zero extend the upper 32 bits. 543 if (GR32RC.contains(RegID)) 544 return true; 545 546 // Early exit if this instruction has no vex/evex/xop prefix. 547 if (!HasEVEX && !HasVEX && !HasXOP) 548 return false; 549 550 // All VEX and EVEX encoded instructions are defined to zero the high bits 551 // of the destination register up to VLMAX (i.e. the maximum vector register 552 // width pertaining to the instruction). 553 // We assume the same behavior for XOP instructions too. 554 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); 555 }; 556 557 Mask.clearAllBits(); 558 for (unsigned I = 0, E = NumDefs; I < E; ++I) { 559 const MCOperand &Op = Inst.getOperand(I); 560 if (ClearsSuperReg(Op.getReg())) 561 Mask.setBit(I); 562 } 563 564 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) { 565 const MCPhysReg Reg = Desc.implicit_defs()[I]; 566 if (ClearsSuperReg(Reg)) 567 Mask.setBit(NumDefs + I); 568 } 569 570 return Mask.getBoolValue(); 571 } 572 573 static std::vector<std::pair<uint64_t, uint64_t>> 574 findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) { 575 // Do a lightweight parsing of PLT entries. 576 std::vector<std::pair<uint64_t, uint64_t>> Result; 577 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 578 // Recognize a jmp. 579 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) { 580 // The jmp instruction at the beginning of each PLT entry jumps to the 581 // address of the base of the .got.plt section plus the immediate. 582 // Set the 1 << 32 bit to let ELFObjectFileBase::getPltEntries convert the 583 // offset to an address. Imm may be a negative int32_t if the GOT entry is 584 // in .got. 585 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 586 Result.emplace_back(PltSectionVA + Byte, Imm | (uint64_t(1) << 32)); 587 Byte += 6; 588 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 589 // The jmp instruction at the beginning of each PLT entry jumps to the 590 // immediate. 591 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 592 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 593 Byte += 6; 594 } else 595 Byte++; 596 } 597 return Result; 598 } 599 600 static std::vector<std::pair<uint64_t, uint64_t>> 601 findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) { 602 // Do a lightweight parsing of PLT entries. 603 std::vector<std::pair<uint64_t, uint64_t>> Result; 604 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 605 // Recognize a jmp. 606 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 607 // The jmp instruction at the beginning of each PLT entry jumps to the 608 // address of the next instruction plus the immediate. 609 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 610 Result.push_back( 611 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm)); 612 Byte += 6; 613 } else 614 Byte++; 615 } 616 return Result; 617 } 618 619 std::vector<std::pair<uint64_t, uint64_t>> 620 X86MCInstrAnalysis::findPltEntries(uint64_t PltSectionVA, 621 ArrayRef<uint8_t> PltContents, 622 const Triple &TargetTriple) const { 623 switch (TargetTriple.getArch()) { 624 case Triple::x86: 625 return findX86PltEntries(PltSectionVA, PltContents); 626 case Triple::x86_64: 627 return findX86_64PltEntries(PltSectionVA, PltContents); 628 default: 629 return {}; 630 } 631 } 632 633 bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, 634 uint64_t Size, uint64_t &Target) const { 635 if (Inst.getNumOperands() == 0 || 636 Info->get(Inst.getOpcode()).operands()[0].OperandType != 637 MCOI::OPERAND_PCREL) 638 return false; 639 Target = Addr + Size + Inst.getOperand(0).getImm(); 640 return true; 641 } 642 643 std::optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress( 644 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, 645 uint64_t Size) const { 646 const MCInstrDesc &MCID = Info->get(Inst.getOpcode()); 647 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags); 648 if (MemOpStart == -1) 649 return std::nullopt; 650 MemOpStart += X86II::getOperandBias(MCID); 651 652 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); 653 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); 654 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); 655 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); 656 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); 657 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || 658 !Disp.isImm()) 659 return std::nullopt; 660 661 // RIP-relative addressing. 662 if (BaseReg.getReg() == X86::RIP) 663 return Addr + Size + Disp.getImm(); 664 665 return std::nullopt; 666 } 667 668 std::optional<uint64_t> 669 X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst, 670 uint64_t Size) const { 671 if (Inst.getOpcode() != X86::LEA64r) 672 return std::nullopt; 673 const MCInstrDesc &MCID = Info->get(Inst.getOpcode()); 674 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags); 675 if (MemOpStart == -1) 676 return std::nullopt; 677 MemOpStart += X86II::getOperandBias(MCID); 678 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); 679 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); 680 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); 681 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); 682 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); 683 // Must be a simple rip-relative address. 684 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() != 0 || 685 IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm()) 686 return std::nullopt; 687 // rip-relative ModR/M immediate is 32 bits. 688 assert(Size > 4 && "invalid instruction size for rip-relative lea"); 689 return Size - 4; 690 } 691 692 } // end of namespace X86_MC 693 694 } // end of namespace llvm 695 696 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 697 return new X86_MC::X86MCInstrAnalysis(Info); 698 } 699 700 // Force static initialization. 701 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC() { 702 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) { 703 // Register the MC asm info. 704 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 705 706 // Register the MC instruction info. 707 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 708 709 // Register the MC register info. 710 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 711 712 // Register the MC subtarget info. 713 TargetRegistry::RegisterMCSubtargetInfo(*T, 714 X86_MC::createX86MCSubtargetInfo); 715 716 // Register the MC instruction analyzer. 717 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 718 719 // Register the code emitter. 720 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 721 722 // Register the obj target streamer. 723 TargetRegistry::RegisterObjectTargetStreamer(*T, 724 createX86ObjectTargetStreamer); 725 726 // Register the asm target streamer. 727 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer); 728 729 // Register the null streamer. 730 TargetRegistry::RegisterNullTargetStreamer(*T, createX86NullTargetStreamer); 731 732 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 733 734 // Register the MCInstPrinter. 735 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 736 737 // Register the MC relocation info. 738 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 739 } 740 741 // Register the asm backend. 742 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(), 743 createX86_32AsmBackend); 744 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(), 745 createX86_64AsmBackend); 746 } 747 748 MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size, 749 bool High) { 750 switch (Size) { 751 default: llvm_unreachable("illegal register size"); 752 case 8: 753 if (High) { 754 switch (Reg.id()) { 755 default: return X86::NoRegister; 756 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 757 return X86::AH; 758 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 759 return X86::DH; 760 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 761 return X86::CH; 762 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 763 return X86::BH; 764 } 765 } else { 766 switch (Reg.id()) { 767 default: return X86::NoRegister; 768 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 769 return X86::AL; 770 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 771 return X86::DL; 772 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 773 return X86::CL; 774 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 775 return X86::BL; 776 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 777 return X86::SIL; 778 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 779 return X86::DIL; 780 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 781 return X86::BPL; 782 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 783 return X86::SPL; 784 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 785 return X86::R8B; 786 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 787 return X86::R9B; 788 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 789 return X86::R10B; 790 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 791 return X86::R11B; 792 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 793 return X86::R12B; 794 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 795 return X86::R13B; 796 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 797 return X86::R14B; 798 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 799 return X86::R15B; 800 } 801 } 802 case 16: 803 switch (Reg.id()) { 804 default: return X86::NoRegister; 805 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 806 return X86::AX; 807 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 808 return X86::DX; 809 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 810 return X86::CX; 811 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 812 return X86::BX; 813 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 814 return X86::SI; 815 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 816 return X86::DI; 817 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 818 return X86::BP; 819 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 820 return X86::SP; 821 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 822 return X86::R8W; 823 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 824 return X86::R9W; 825 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 826 return X86::R10W; 827 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 828 return X86::R11W; 829 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 830 return X86::R12W; 831 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 832 return X86::R13W; 833 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 834 return X86::R14W; 835 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 836 return X86::R15W; 837 } 838 case 32: 839 switch (Reg.id()) { 840 default: return X86::NoRegister; 841 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 842 return X86::EAX; 843 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 844 return X86::EDX; 845 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 846 return X86::ECX; 847 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 848 return X86::EBX; 849 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 850 return X86::ESI; 851 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 852 return X86::EDI; 853 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 854 return X86::EBP; 855 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 856 return X86::ESP; 857 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 858 return X86::R8D; 859 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 860 return X86::R9D; 861 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 862 return X86::R10D; 863 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 864 return X86::R11D; 865 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 866 return X86::R12D; 867 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 868 return X86::R13D; 869 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 870 return X86::R14D; 871 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 872 return X86::R15D; 873 } 874 case 64: 875 switch (Reg.id()) { 876 default: return X86::NoRegister; 877 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 878 return X86::RAX; 879 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 880 return X86::RDX; 881 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 882 return X86::RCX; 883 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 884 return X86::RBX; 885 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 886 return X86::RSI; 887 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 888 return X86::RDI; 889 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 890 return X86::RBP; 891 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 892 return X86::RSP; 893 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 894 return X86::R8; 895 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 896 return X86::R9; 897 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 898 return X86::R10; 899 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 900 return X86::R11; 901 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 902 return X86::R12; 903 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 904 return X86::R13; 905 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 906 return X86::R14; 907 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 908 return X86::R15; 909 } 910 } 911 } 912