1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86MCTargetDesc.h" 14 #include "TargetInfo/X86TargetInfo.h" 15 #include "X86ATTInstPrinter.h" 16 #include "X86BaseInfo.h" 17 #include "X86IntelInstPrinter.h" 18 #include "X86MCAsmInfo.h" 19 #include "llvm/ADT/APInt.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/DebugInfo/CodeView/CodeView.h" 22 #include "llvm/MC/MCDwarf.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCStreamer.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/MC/MachineLocation.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/Host.h" 31 #include "llvm/Support/TargetRegistry.h" 32 33 using namespace llvm; 34 35 #define GET_REGINFO_MC_DESC 36 #include "X86GenRegisterInfo.inc" 37 38 #define GET_INSTRINFO_MC_DESC 39 #define GET_INSTRINFO_MC_HELPERS 40 #include "X86GenInstrInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "X86GenSubtargetInfo.inc" 44 45 std::string X86_MC::ParseX86Triple(const Triple &TT) { 46 std::string FS; 47 // SSE2 should default to enabled in 64-bit mode, but can be turned off 48 // explicitly. 49 if (TT.isArch64Bit()) 50 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2"; 51 else if (TT.getEnvironment() != Triple::CODE16) 52 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 53 else 54 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 55 56 return FS; 57 } 58 59 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 60 if (TT.getArch() == Triple::x86_64) 61 return DWARFFlavour::X86_64; 62 63 if (TT.isOSDarwin()) 64 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 65 if (TT.isOSCygMing()) 66 // Unsupported by now, just quick fallback 67 return DWARFFlavour::X86_32_Generic; 68 return DWARFFlavour::X86_32_Generic; 69 } 70 71 bool X86_MC::hasLockPrefix(const MCInst &MI) { 72 return MI.getFlags() & X86::IP_HAS_LOCK; 73 } 74 75 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 76 // FIXME: TableGen these. 77 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 78 unsigned SEH = MRI->getEncodingValue(Reg); 79 MRI->mapLLVMRegToSEHReg(Reg, SEH); 80 } 81 82 // Mapping from CodeView to MC register id. 83 static const struct { 84 codeview::RegisterId CVReg; 85 MCPhysReg Reg; 86 } RegMap[] = { 87 {codeview::RegisterId::AL, X86::AL}, 88 {codeview::RegisterId::CL, X86::CL}, 89 {codeview::RegisterId::DL, X86::DL}, 90 {codeview::RegisterId::BL, X86::BL}, 91 {codeview::RegisterId::AH, X86::AH}, 92 {codeview::RegisterId::CH, X86::CH}, 93 {codeview::RegisterId::DH, X86::DH}, 94 {codeview::RegisterId::BH, X86::BH}, 95 {codeview::RegisterId::AX, X86::AX}, 96 {codeview::RegisterId::CX, X86::CX}, 97 {codeview::RegisterId::DX, X86::DX}, 98 {codeview::RegisterId::BX, X86::BX}, 99 {codeview::RegisterId::SP, X86::SP}, 100 {codeview::RegisterId::BP, X86::BP}, 101 {codeview::RegisterId::SI, X86::SI}, 102 {codeview::RegisterId::DI, X86::DI}, 103 {codeview::RegisterId::EAX, X86::EAX}, 104 {codeview::RegisterId::ECX, X86::ECX}, 105 {codeview::RegisterId::EDX, X86::EDX}, 106 {codeview::RegisterId::EBX, X86::EBX}, 107 {codeview::RegisterId::ESP, X86::ESP}, 108 {codeview::RegisterId::EBP, X86::EBP}, 109 {codeview::RegisterId::ESI, X86::ESI}, 110 {codeview::RegisterId::EDI, X86::EDI}, 111 112 {codeview::RegisterId::EFLAGS, X86::EFLAGS}, 113 114 {codeview::RegisterId::ST0, X86::FP0}, 115 {codeview::RegisterId::ST1, X86::FP1}, 116 {codeview::RegisterId::ST2, X86::FP2}, 117 {codeview::RegisterId::ST3, X86::FP3}, 118 {codeview::RegisterId::ST4, X86::FP4}, 119 {codeview::RegisterId::ST5, X86::FP5}, 120 {codeview::RegisterId::ST6, X86::FP6}, 121 {codeview::RegisterId::ST7, X86::FP7}, 122 123 {codeview::RegisterId::MM0, X86::MM0}, 124 {codeview::RegisterId::MM1, X86::MM1}, 125 {codeview::RegisterId::MM2, X86::MM2}, 126 {codeview::RegisterId::MM3, X86::MM3}, 127 {codeview::RegisterId::MM4, X86::MM4}, 128 {codeview::RegisterId::MM5, X86::MM5}, 129 {codeview::RegisterId::MM6, X86::MM6}, 130 {codeview::RegisterId::MM7, X86::MM7}, 131 132 {codeview::RegisterId::XMM0, X86::XMM0}, 133 {codeview::RegisterId::XMM1, X86::XMM1}, 134 {codeview::RegisterId::XMM2, X86::XMM2}, 135 {codeview::RegisterId::XMM3, X86::XMM3}, 136 {codeview::RegisterId::XMM4, X86::XMM4}, 137 {codeview::RegisterId::XMM5, X86::XMM5}, 138 {codeview::RegisterId::XMM6, X86::XMM6}, 139 {codeview::RegisterId::XMM7, X86::XMM7}, 140 141 {codeview::RegisterId::XMM8, X86::XMM8}, 142 {codeview::RegisterId::XMM9, X86::XMM9}, 143 {codeview::RegisterId::XMM10, X86::XMM10}, 144 {codeview::RegisterId::XMM11, X86::XMM11}, 145 {codeview::RegisterId::XMM12, X86::XMM12}, 146 {codeview::RegisterId::XMM13, X86::XMM13}, 147 {codeview::RegisterId::XMM14, X86::XMM14}, 148 {codeview::RegisterId::XMM15, X86::XMM15}, 149 150 {codeview::RegisterId::SIL, X86::SIL}, 151 {codeview::RegisterId::DIL, X86::DIL}, 152 {codeview::RegisterId::BPL, X86::BPL}, 153 {codeview::RegisterId::SPL, X86::SPL}, 154 {codeview::RegisterId::RAX, X86::RAX}, 155 {codeview::RegisterId::RBX, X86::RBX}, 156 {codeview::RegisterId::RCX, X86::RCX}, 157 {codeview::RegisterId::RDX, X86::RDX}, 158 {codeview::RegisterId::RSI, X86::RSI}, 159 {codeview::RegisterId::RDI, X86::RDI}, 160 {codeview::RegisterId::RBP, X86::RBP}, 161 {codeview::RegisterId::RSP, X86::RSP}, 162 {codeview::RegisterId::R8, X86::R8}, 163 {codeview::RegisterId::R9, X86::R9}, 164 {codeview::RegisterId::R10, X86::R10}, 165 {codeview::RegisterId::R11, X86::R11}, 166 {codeview::RegisterId::R12, X86::R12}, 167 {codeview::RegisterId::R13, X86::R13}, 168 {codeview::RegisterId::R14, X86::R14}, 169 {codeview::RegisterId::R15, X86::R15}, 170 {codeview::RegisterId::R8B, X86::R8B}, 171 {codeview::RegisterId::R9B, X86::R9B}, 172 {codeview::RegisterId::R10B, X86::R10B}, 173 {codeview::RegisterId::R11B, X86::R11B}, 174 {codeview::RegisterId::R12B, X86::R12B}, 175 {codeview::RegisterId::R13B, X86::R13B}, 176 {codeview::RegisterId::R14B, X86::R14B}, 177 {codeview::RegisterId::R15B, X86::R15B}, 178 {codeview::RegisterId::R8W, X86::R8W}, 179 {codeview::RegisterId::R9W, X86::R9W}, 180 {codeview::RegisterId::R10W, X86::R10W}, 181 {codeview::RegisterId::R11W, X86::R11W}, 182 {codeview::RegisterId::R12W, X86::R12W}, 183 {codeview::RegisterId::R13W, X86::R13W}, 184 {codeview::RegisterId::R14W, X86::R14W}, 185 {codeview::RegisterId::R15W, X86::R15W}, 186 {codeview::RegisterId::R8D, X86::R8D}, 187 {codeview::RegisterId::R9D, X86::R9D}, 188 {codeview::RegisterId::R10D, X86::R10D}, 189 {codeview::RegisterId::R11D, X86::R11D}, 190 {codeview::RegisterId::R12D, X86::R12D}, 191 {codeview::RegisterId::R13D, X86::R13D}, 192 {codeview::RegisterId::R14D, X86::R14D}, 193 {codeview::RegisterId::R15D, X86::R15D}, 194 {codeview::RegisterId::AMD64_YMM0, X86::YMM0}, 195 {codeview::RegisterId::AMD64_YMM1, X86::YMM1}, 196 {codeview::RegisterId::AMD64_YMM2, X86::YMM2}, 197 {codeview::RegisterId::AMD64_YMM3, X86::YMM3}, 198 {codeview::RegisterId::AMD64_YMM4, X86::YMM4}, 199 {codeview::RegisterId::AMD64_YMM5, X86::YMM5}, 200 {codeview::RegisterId::AMD64_YMM6, X86::YMM6}, 201 {codeview::RegisterId::AMD64_YMM7, X86::YMM7}, 202 {codeview::RegisterId::AMD64_YMM8, X86::YMM8}, 203 {codeview::RegisterId::AMD64_YMM9, X86::YMM9}, 204 {codeview::RegisterId::AMD64_YMM10, X86::YMM10}, 205 {codeview::RegisterId::AMD64_YMM11, X86::YMM11}, 206 {codeview::RegisterId::AMD64_YMM12, X86::YMM12}, 207 {codeview::RegisterId::AMD64_YMM13, X86::YMM13}, 208 {codeview::RegisterId::AMD64_YMM14, X86::YMM14}, 209 {codeview::RegisterId::AMD64_YMM15, X86::YMM15}, 210 {codeview::RegisterId::AMD64_YMM16, X86::YMM16}, 211 {codeview::RegisterId::AMD64_YMM17, X86::YMM17}, 212 {codeview::RegisterId::AMD64_YMM18, X86::YMM18}, 213 {codeview::RegisterId::AMD64_YMM19, X86::YMM19}, 214 {codeview::RegisterId::AMD64_YMM20, X86::YMM20}, 215 {codeview::RegisterId::AMD64_YMM21, X86::YMM21}, 216 {codeview::RegisterId::AMD64_YMM22, X86::YMM22}, 217 {codeview::RegisterId::AMD64_YMM23, X86::YMM23}, 218 {codeview::RegisterId::AMD64_YMM24, X86::YMM24}, 219 {codeview::RegisterId::AMD64_YMM25, X86::YMM25}, 220 {codeview::RegisterId::AMD64_YMM26, X86::YMM26}, 221 {codeview::RegisterId::AMD64_YMM27, X86::YMM27}, 222 {codeview::RegisterId::AMD64_YMM28, X86::YMM28}, 223 {codeview::RegisterId::AMD64_YMM29, X86::YMM29}, 224 {codeview::RegisterId::AMD64_YMM30, X86::YMM30}, 225 {codeview::RegisterId::AMD64_YMM31, X86::YMM31}, 226 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0}, 227 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1}, 228 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2}, 229 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3}, 230 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4}, 231 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5}, 232 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6}, 233 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7}, 234 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8}, 235 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9}, 236 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10}, 237 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11}, 238 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12}, 239 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13}, 240 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14}, 241 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15}, 242 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16}, 243 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17}, 244 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18}, 245 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19}, 246 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20}, 247 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21}, 248 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22}, 249 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23}, 250 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24}, 251 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25}, 252 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26}, 253 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27}, 254 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28}, 255 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29}, 256 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30}, 257 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31}, 258 {codeview::RegisterId::AMD64_K0, X86::K0}, 259 {codeview::RegisterId::AMD64_K1, X86::K1}, 260 {codeview::RegisterId::AMD64_K2, X86::K2}, 261 {codeview::RegisterId::AMD64_K3, X86::K3}, 262 {codeview::RegisterId::AMD64_K4, X86::K4}, 263 {codeview::RegisterId::AMD64_K5, X86::K5}, 264 {codeview::RegisterId::AMD64_K6, X86::K6}, 265 {codeview::RegisterId::AMD64_K7, X86::K7}, 266 {codeview::RegisterId::AMD64_XMM16, X86::XMM16}, 267 {codeview::RegisterId::AMD64_XMM17, X86::XMM17}, 268 {codeview::RegisterId::AMD64_XMM18, X86::XMM18}, 269 {codeview::RegisterId::AMD64_XMM19, X86::XMM19}, 270 {codeview::RegisterId::AMD64_XMM20, X86::XMM20}, 271 {codeview::RegisterId::AMD64_XMM21, X86::XMM21}, 272 {codeview::RegisterId::AMD64_XMM22, X86::XMM22}, 273 {codeview::RegisterId::AMD64_XMM23, X86::XMM23}, 274 {codeview::RegisterId::AMD64_XMM24, X86::XMM24}, 275 {codeview::RegisterId::AMD64_XMM25, X86::XMM25}, 276 {codeview::RegisterId::AMD64_XMM26, X86::XMM26}, 277 {codeview::RegisterId::AMD64_XMM27, X86::XMM27}, 278 {codeview::RegisterId::AMD64_XMM28, X86::XMM28}, 279 {codeview::RegisterId::AMD64_XMM29, X86::XMM29}, 280 {codeview::RegisterId::AMD64_XMM30, X86::XMM30}, 281 {codeview::RegisterId::AMD64_XMM31, X86::XMM31}, 282 283 }; 284 for (unsigned I = 0; I < array_lengthof(RegMap); ++I) 285 MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg)); 286 } 287 288 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 289 StringRef CPU, StringRef FS) { 290 std::string ArchFS = X86_MC::ParseX86Triple(TT); 291 assert(!ArchFS.empty() && "Failed to parse X86 triple"); 292 if (!FS.empty()) 293 ArchFS = (Twine(ArchFS) + "," + FS).str(); 294 295 if (CPU.empty()) 296 CPU = "generic"; 297 298 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS); 299 } 300 301 static MCInstrInfo *createX86MCInstrInfo() { 302 MCInstrInfo *X = new MCInstrInfo(); 303 InitX86MCInstrInfo(X); 304 return X; 305 } 306 307 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 308 unsigned RA = (TT.getArch() == Triple::x86_64) 309 ? X86::RIP // Should have dwarf #16. 310 : X86::EIP; // Should have dwarf #8. 311 312 MCRegisterInfo *X = new MCRegisterInfo(); 313 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 314 X86_MC::getDwarfRegFlavour(TT, true), RA); 315 X86_MC::initLLVMToSEHAndCVRegMapping(X); 316 return X; 317 } 318 319 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 320 const Triple &TheTriple, 321 const MCTargetOptions &Options) { 322 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 323 324 MCAsmInfo *MAI; 325 if (TheTriple.isOSBinFormatMachO()) { 326 if (is64Bit) 327 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 328 else 329 MAI = new X86MCAsmInfoDarwin(TheTriple); 330 } else if (TheTriple.isOSBinFormatELF()) { 331 // Force the use of an ELF container. 332 MAI = new X86ELFMCAsmInfo(TheTriple); 333 } else if (TheTriple.isWindowsMSVCEnvironment() || 334 TheTriple.isWindowsCoreCLREnvironment()) { 335 if (Options.getAssemblyLanguage().equals_insensitive("masm")) 336 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple); 337 else 338 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 339 } else if (TheTriple.isOSCygMing() || 340 TheTriple.isWindowsItaniumEnvironment()) { 341 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 342 } else { 343 // The default is ELF. 344 MAI = new X86ELFMCAsmInfo(TheTriple); 345 } 346 347 // Initialize initial frame state. 348 // Calculate amount of bytes used for return address storing 349 int stackGrowth = is64Bit ? -8 : -4; 350 351 // Initial state of the frame pointer is esp+stackGrowth. 352 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 353 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( 354 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 355 MAI->addInitialFrameState(Inst); 356 357 // Add return address to move list 358 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 359 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 360 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 361 MAI->addInitialFrameState(Inst2); 362 363 return MAI; 364 } 365 366 static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 367 unsigned SyntaxVariant, 368 const MCAsmInfo &MAI, 369 const MCInstrInfo &MII, 370 const MCRegisterInfo &MRI) { 371 if (SyntaxVariant == 0) 372 return new X86ATTInstPrinter(MAI, MII, MRI); 373 if (SyntaxVariant == 1) 374 return new X86IntelInstPrinter(MAI, MII, MRI); 375 return nullptr; 376 } 377 378 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 379 MCContext &Ctx) { 380 // Default to the stock relocation info. 381 return llvm::createMCRelocationInfo(TheTriple, Ctx); 382 } 383 384 namespace llvm { 385 namespace X86_MC { 386 387 class X86MCInstrAnalysis : public MCInstrAnalysis { 388 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete; 389 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete; 390 virtual ~X86MCInstrAnalysis() = default; 391 392 public: 393 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {} 394 395 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 396 #include "X86GenSubtargetInfo.inc" 397 398 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, 399 APInt &Mask) const override; 400 std::vector<std::pair<uint64_t, uint64_t>> 401 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 402 uint64_t GotSectionVA, 403 const Triple &TargetTriple) const override; 404 405 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 406 uint64_t &Target) const override; 407 Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst, 408 uint64_t Addr, 409 uint64_t Size) const override; 410 }; 411 412 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 413 #include "X86GenSubtargetInfo.inc" 414 415 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, 416 const MCInst &Inst, 417 APInt &Mask) const { 418 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 419 unsigned NumDefs = Desc.getNumDefs(); 420 unsigned NumImplicitDefs = Desc.getNumImplicitDefs(); 421 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs && 422 "Unexpected number of bits in the mask!"); 423 424 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX; 425 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; 426 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP; 427 428 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); 429 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); 430 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); 431 432 auto ClearsSuperReg = [=](unsigned RegID) { 433 // On X86-64, a general purpose integer register is viewed as a 64-bit 434 // register internal to the processor. 435 // An update to the lower 32 bits of a 64 bit integer register is 436 // architecturally defined to zero extend the upper 32 bits. 437 if (GR32RC.contains(RegID)) 438 return true; 439 440 // Early exit if this instruction has no vex/evex/xop prefix. 441 if (!HasEVEX && !HasVEX && !HasXOP) 442 return false; 443 444 // All VEX and EVEX encoded instructions are defined to zero the high bits 445 // of the destination register up to VLMAX (i.e. the maximum vector register 446 // width pertaining to the instruction). 447 // We assume the same behavior for XOP instructions too. 448 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); 449 }; 450 451 Mask.clearAllBits(); 452 for (unsigned I = 0, E = NumDefs; I < E; ++I) { 453 const MCOperand &Op = Inst.getOperand(I); 454 if (ClearsSuperReg(Op.getReg())) 455 Mask.setBit(I); 456 } 457 458 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) { 459 const MCPhysReg Reg = Desc.getImplicitDefs()[I]; 460 if (ClearsSuperReg(Reg)) 461 Mask.setBit(NumDefs + I); 462 } 463 464 return Mask.getBoolValue(); 465 } 466 467 static std::vector<std::pair<uint64_t, uint64_t>> 468 findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 469 uint64_t GotPltSectionVA) { 470 // Do a lightweight parsing of PLT entries. 471 std::vector<std::pair<uint64_t, uint64_t>> Result; 472 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 473 // Recognize a jmp. 474 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) { 475 // The jmp instruction at the beginning of each PLT entry jumps to the 476 // address of the base of the .got.plt section plus the immediate. 477 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 478 Result.push_back( 479 std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm)); 480 Byte += 6; 481 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 482 // The jmp instruction at the beginning of each PLT entry jumps to the 483 // immediate. 484 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 485 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 486 Byte += 6; 487 } else 488 Byte++; 489 } 490 return Result; 491 } 492 493 static std::vector<std::pair<uint64_t, uint64_t>> 494 findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) { 495 // Do a lightweight parsing of PLT entries. 496 std::vector<std::pair<uint64_t, uint64_t>> Result; 497 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 498 // Recognize a jmp. 499 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 500 // The jmp instruction at the beginning of each PLT entry jumps to the 501 // address of the next instruction plus the immediate. 502 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 503 Result.push_back( 504 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm)); 505 Byte += 6; 506 } else 507 Byte++; 508 } 509 return Result; 510 } 511 512 std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries( 513 uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 514 uint64_t GotPltSectionVA, const Triple &TargetTriple) const { 515 switch (TargetTriple.getArch()) { 516 case Triple::x86: 517 return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA); 518 case Triple::x86_64: 519 return findX86_64PltEntries(PltSectionVA, PltContents); 520 default: 521 return {}; 522 } 523 } 524 525 bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, 526 uint64_t Size, uint64_t &Target) const { 527 if (Inst.getNumOperands() == 0 || 528 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 529 return false; 530 Target = Addr + Size + Inst.getOperand(0).getImm(); 531 return true; 532 } 533 534 Optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress( 535 const MCInst &Inst, uint64_t Addr, uint64_t Size) const { 536 const MCInstrDesc &MCID = Info->get(Inst.getOpcode()); 537 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags); 538 if (MemOpStart == -1) 539 return None; 540 MemOpStart += X86II::getOperandBias(MCID); 541 542 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); 543 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); 544 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); 545 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); 546 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); 547 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || 548 !Disp.isImm()) 549 return None; 550 551 // RIP-relative addressing. 552 if (BaseReg.getReg() == X86::RIP) 553 return Addr + Size + Disp.getImm(); 554 555 return None; 556 } 557 558 } // end of namespace X86_MC 559 560 } // end of namespace llvm 561 562 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 563 return new X86_MC::X86MCInstrAnalysis(Info); 564 } 565 566 // Force static initialization. 567 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC() { 568 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) { 569 // Register the MC asm info. 570 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 571 572 // Register the MC instruction info. 573 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 574 575 // Register the MC register info. 576 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 577 578 // Register the MC subtarget info. 579 TargetRegistry::RegisterMCSubtargetInfo(*T, 580 X86_MC::createX86MCSubtargetInfo); 581 582 // Register the MC instruction analyzer. 583 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 584 585 // Register the code emitter. 586 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 587 588 // Register the obj target streamer. 589 TargetRegistry::RegisterObjectTargetStreamer(*T, 590 createX86ObjectTargetStreamer); 591 592 // Register the asm target streamer. 593 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer); 594 595 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 596 597 // Register the MCInstPrinter. 598 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 599 600 // Register the MC relocation info. 601 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 602 } 603 604 // Register the asm backend. 605 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(), 606 createX86_32AsmBackend); 607 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(), 608 createX86_64AsmBackend); 609 } 610 611 MCRegister llvm::getX86SubSuperRegisterOrZero(MCRegister Reg, unsigned Size, 612 bool High) { 613 switch (Size) { 614 default: return X86::NoRegister; 615 case 8: 616 if (High) { 617 switch (Reg.id()) { 618 default: return getX86SubSuperRegisterOrZero(Reg, 64); 619 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 620 return X86::SI; 621 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 622 return X86::DI; 623 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 624 return X86::BP; 625 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 626 return X86::SP; 627 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 628 return X86::AH; 629 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 630 return X86::DH; 631 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 632 return X86::CH; 633 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 634 return X86::BH; 635 } 636 } else { 637 switch (Reg.id()) { 638 default: return X86::NoRegister; 639 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 640 return X86::AL; 641 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 642 return X86::DL; 643 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 644 return X86::CL; 645 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 646 return X86::BL; 647 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 648 return X86::SIL; 649 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 650 return X86::DIL; 651 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 652 return X86::BPL; 653 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 654 return X86::SPL; 655 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 656 return X86::R8B; 657 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 658 return X86::R9B; 659 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 660 return X86::R10B; 661 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 662 return X86::R11B; 663 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 664 return X86::R12B; 665 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 666 return X86::R13B; 667 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 668 return X86::R14B; 669 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 670 return X86::R15B; 671 } 672 } 673 case 16: 674 switch (Reg.id()) { 675 default: return X86::NoRegister; 676 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 677 return X86::AX; 678 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 679 return X86::DX; 680 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 681 return X86::CX; 682 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 683 return X86::BX; 684 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 685 return X86::SI; 686 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 687 return X86::DI; 688 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 689 return X86::BP; 690 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 691 return X86::SP; 692 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 693 return X86::R8W; 694 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 695 return X86::R9W; 696 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 697 return X86::R10W; 698 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 699 return X86::R11W; 700 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 701 return X86::R12W; 702 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 703 return X86::R13W; 704 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 705 return X86::R14W; 706 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 707 return X86::R15W; 708 } 709 case 32: 710 switch (Reg.id()) { 711 default: return X86::NoRegister; 712 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 713 return X86::EAX; 714 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 715 return X86::EDX; 716 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 717 return X86::ECX; 718 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 719 return X86::EBX; 720 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 721 return X86::ESI; 722 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 723 return X86::EDI; 724 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 725 return X86::EBP; 726 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 727 return X86::ESP; 728 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 729 return X86::R8D; 730 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 731 return X86::R9D; 732 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 733 return X86::R10D; 734 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 735 return X86::R11D; 736 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 737 return X86::R12D; 738 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 739 return X86::R13D; 740 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 741 return X86::R14D; 742 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 743 return X86::R15D; 744 } 745 case 64: 746 switch (Reg.id()) { 747 default: return 0; 748 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 749 return X86::RAX; 750 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 751 return X86::RDX; 752 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 753 return X86::RCX; 754 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 755 return X86::RBX; 756 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 757 return X86::RSI; 758 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 759 return X86::RDI; 760 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 761 return X86::RBP; 762 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 763 return X86::RSP; 764 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 765 return X86::R8; 766 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 767 return X86::R9; 768 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 769 return X86::R10; 770 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 771 return X86::R11; 772 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 773 return X86::R12; 774 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 775 return X86::R13; 776 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 777 return X86::R14; 778 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 779 return X86::R15; 780 } 781 } 782 } 783 784 MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High) { 785 MCRegister Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 786 assert(Res != X86::NoRegister && "Unexpected register or VT"); 787 return Res; 788 } 789 790 791