1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is a target description file for the Intel i386 architecture, referred 10// to here as the "X86" architecture. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing... 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// X86 Subtarget state 20// 21// disregarding specific ABI / programming model 22def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true", 23 "64-bit mode (x86_64)">; 24def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true", 25 "32-bit mode (80386)">; 26def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true", 27 "16-bit mode (i8086)">; 28 29//===----------------------------------------------------------------------===// 30// X86 Subtarget ISA features 31//===----------------------------------------------------------------------===// 32 33def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", 34 "Enable X87 float instructions">; 35 36def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", 37 "Enable NOPL instruction (generally pentium pro+)">; 38 39def FeatureCMOV : SubtargetFeature<"cmov","HasCMOV", "true", 40 "Enable conditional move instructions">; 41 42def FeatureCX8 : SubtargetFeature<"cx8", "HasCX8", "true", 43 "Support CMPXCHG8B instructions">; 44 45def FeatureCRC32 : SubtargetFeature<"crc32", "HasCRC32", "true", 46 "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">; 47 48def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 49 "Support POPCNT instruction">; 50 51def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", 52 "Support fxsave/fxrestore instructions">; 53 54def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", 55 "Support xsave instructions">; 56 57def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", 58 "Support xsaveopt instructions", 59 [FeatureXSAVE]>; 60 61def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", 62 "Support xsavec instructions", 63 [FeatureXSAVE]>; 64 65def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", 66 "Support xsaves instructions", 67 [FeatureXSAVE]>; 68 69def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 70 "Enable SSE instructions">; 71def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 72 "Enable SSE2 instructions", 73 [FeatureSSE1]>; 74def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 75 "Enable SSE3 instructions", 76 [FeatureSSE2]>; 77def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 78 "Enable SSSE3 instructions", 79 [FeatureSSE3]>; 80def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", 81 "Enable SSE 4.1 instructions", 82 [FeatureSSSE3]>; 83def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", 84 "Enable SSE 4.2 instructions", 85 [FeatureSSE41]>; 86// The MMX subtarget feature is separate from the rest of the SSE features 87// because it's important (for odd compatibility reasons) to be able to 88// turn it off explicitly while allowing SSE+ to be on. 89def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", 90 "Enable MMX instructions">; 91def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 92 "Enable 3DNow! instructions", 93 [FeatureMMX]>; 94def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 95 "Enable 3DNow! Athlon instructions", 96 [Feature3DNow]>; 97// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 98// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 99// without disabling 64-bit mode. Nothing should imply this feature bit. It 100// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode. 101def FeatureX86_64 : SubtargetFeature<"64bit", "HasX86_64", "true", 102 "Support 64-bit instructions">; 103def FeatureCX16 : SubtargetFeature<"cx16", "HasCX16", "true", 104 "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)", 105 [FeatureCX8]>; 106def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 107 "Support SSE 4a instructions", 108 [FeatureSSE3]>; 109 110def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", 111 "Enable AVX instructions", 112 [FeatureSSE42]>; 113def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", 114 "Enable AVX2 instructions", 115 [FeatureAVX]>; 116def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", 117 "Enable three-operand fused multiple-add", 118 [FeatureAVX]>; 119def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", 120 "Support 16-bit floating point conversion instructions", 121 [FeatureAVX]>; 122def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512", 123 "Enable AVX-512 instructions", 124 [FeatureAVX2, FeatureFMA, FeatureF16C]>; 125def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", 126 "Enable AVX-512 Exponential and Reciprocal Instructions", 127 [FeatureAVX512]>; 128def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", 129 "Enable AVX-512 Conflict Detection Instructions", 130 [FeatureAVX512]>; 131def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", 132 "true", "Enable AVX-512 Population Count Instructions", 133 [FeatureAVX512]>; 134def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", 135 "Enable AVX-512 PreFetch Instructions", 136 [FeatureAVX512]>; 137def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", 138 "true", 139 "Prefetch with Intent to Write and T1 Hint">; 140def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", 141 "Enable AVX-512 Doubleword and Quadword Instructions", 142 [FeatureAVX512]>; 143def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", 144 "Enable AVX-512 Byte and Word Instructions", 145 [FeatureAVX512]>; 146def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", 147 "Enable AVX-512 Vector Length eXtensions", 148 [FeatureAVX512]>; 149def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", 150 "Enable AVX-512 Vector Byte Manipulation Instructions", 151 [FeatureBWI]>; 152def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", 153 "Enable AVX-512 further Vector Byte Manipulation Instructions", 154 [FeatureBWI]>; 155def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", 156 "Enable AVX-512 Integer Fused Multiple-Add", 157 [FeatureAVX512]>; 158def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", 159 "Enable protection keys">; 160def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", 161 "Enable AVX-512 Vector Neural Network Instructions", 162 [FeatureAVX512]>; 163def FeatureAVXVNNI : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true", 164 "Support AVX_VNNI encoding", 165 [FeatureAVX2]>; 166def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true", 167 "Support bfloat16 floating point", 168 [FeatureBWI]>; 169def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", 170 "Enable AVX-512 Bit Algorithms", 171 [FeatureBWI]>; 172def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect", 173 "HasVP2INTERSECT", "true", 174 "Enable AVX-512 vp2intersect", 175 [FeatureAVX512]>; 176// FIXME: FP16 scalar intrinsics use the type v8f16, which is supposed to be 177// guarded under condition hasVLX. So we imply it in FeatureFP16 currently. 178// FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is 179// supposed to be guarded under condition hasDQI. So we imply it in FeatureFP16 180// currently. 181def FeatureFP16 : SubtargetFeature<"avx512fp16", "HasFP16", "true", 182 "Support 16-bit floating point", 183 [FeatureBWI, FeatureVLX, FeatureDQI]>; 184def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", 185 "Enable packed carry-less multiplication instructions", 186 [FeatureSSE2]>; 187def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", 188 "Enable Galois Field Arithmetic Instructions", 189 [FeatureSSE2]>; 190def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", 191 "Enable vpclmulqdq instructions", 192 [FeatureAVX, FeaturePCLMUL]>; 193def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 194 "Enable four-operand fused multiple-add", 195 [FeatureAVX, FeatureSSE4A]>; 196def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", 197 "Enable XOP instructions", 198 [FeatureFMA4]>; 199def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", 200 "HasSSEUnalignedMem", "true", 201 "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">; 202def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 203 "Enable AES instructions", 204 [FeatureSSE2]>; 205def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", 206 "Promote selected AES instructions to AVX512/AVX registers", 207 [FeatureAVX, FeatureAES]>; 208def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", 209 "Enable TBM instructions">; 210def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", 211 "Enable LWP instructions">; 212def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", 213 "Support MOVBE instruction">; 214def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", 215 "Support RDRAND instruction">; 216def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", 217 "Support FS/GS Base instructions">; 218def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", 219 "Support LZCNT instruction">; 220def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", 221 "Support BMI instructions">; 222def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", 223 "Support BMI2 instructions">; 224def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", 225 "Support RTM instructions">; 226def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", 227 "Support ADX instructions">; 228def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", 229 "Enable SHA instructions", 230 [FeatureSSE2]>; 231// Processor supports CET SHSTK - Control-Flow Enforcement Technology 232// using Shadow Stack 233def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", 234 "Support CET Shadow-Stack instructions">; 235def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", 236 "Support PRFCHW instructions">; 237def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", 238 "Support RDSEED instruction">; 239def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true", 240 "Support LAHF and SAHF instructions in 64-bit mode">; 241def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", 242 "Enable MONITORX/MWAITX timer functionality">; 243def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", 244 "Enable Cache Line Zero">; 245def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", 246 "Enable Cache Line Demote">; 247def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", 248 "Support ptwrite instruction">; 249def FeatureAMXTILE : SubtargetFeature<"amx-tile", "HasAMXTILE", "true", 250 "Support AMX-TILE instructions">; 251def FeatureAMXINT8 : SubtargetFeature<"amx-int8", "HasAMXINT8", "true", 252 "Support AMX-INT8 instructions", 253 [FeatureAMXTILE]>; 254def FeatureAMXBF16 : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true", 255 "Support AMX-BF16 instructions", 256 [FeatureAMXTILE]>; 257def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", 258 "Invalidate Process-Context Identifier">; 259def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", 260 "Enable Software Guard Extensions">; 261def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", 262 "Flush A Cache Line Optimized">; 263def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", 264 "Cache Line Write Back">; 265def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", 266 "Write Back No Invalidate">; 267def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", 268 "Support RDPID instructions">; 269def FeatureRDPRU : SubtargetFeature<"rdpru", "HasRDPRU", "true", 270 "Support RDPRU instructions">; 271def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", 272 "Wait and pause enhancements">; 273def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true", 274 "Has ENQCMD instructions">; 275def FeatureKL : SubtargetFeature<"kl", "HasKL", "true", 276 "Support Key Locker kl Instructions", 277 [FeatureSSE2]>; 278def FeatureWIDEKL : SubtargetFeature<"widekl", "HasWIDEKL", "true", 279 "Support Key Locker wide Instructions", 280 [FeatureKL]>; 281def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true", 282 "Has hreset instruction">; 283def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true", 284 "Has serialize instruction">; 285def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true", 286 "Support TSXLDTRK instructions">; 287def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true", 288 "Has UINTR Instructions">; 289def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", 290 "platform configuration instruction">; 291def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", 292 "Support movdiri instruction (direct store integer)">; 293def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", 294 "Support movdir64b instruction (direct store 64 bytes)">; 295 296// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka 297// "string operations"). See "REP String Enhancement" in the Intel Software 298// Development Manual. This feature essentially means that REP MOVSB will copy 299// using the largest available size instead of copying bytes one by one, making 300// it at least as fast as REPMOVS{W,D,Q}. 301def FeatureERMSB 302 : SubtargetFeature< 303 "ermsb", "HasERMSB", "true", 304 "REP MOVS/STOS are fast">; 305 306// Icelake and newer processors have Fast Short REP MOV. 307def FeatureFSRM 308 : SubtargetFeature< 309 "fsrm", "HasFSRM", "true", 310 "REP MOVSB of short lengths is faster">; 311 312def FeatureSoftFloat 313 : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 314 "Use software floating point features">; 315 316//===----------------------------------------------------------------------===// 317// X86 Subtarget Security Mitigation features 318//===----------------------------------------------------------------------===// 319 320// Lower indirect calls using a special construct called a `retpoline` to 321// mitigate potential Spectre v2 attacks against them. 322def FeatureRetpolineIndirectCalls 323 : SubtargetFeature< 324 "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true", 325 "Remove speculation of indirect calls from the generated code">; 326 327// Lower indirect branches and switches either using conditional branch trees 328// or using a special construct called a `retpoline` to mitigate potential 329// Spectre v2 attacks against them. 330def FeatureRetpolineIndirectBranches 331 : SubtargetFeature< 332 "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true", 333 "Remove speculation of indirect branches from the generated code">; 334 335// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and 336// `retpoline-indirect-branches` above. 337def FeatureRetpoline 338 : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true", 339 "Remove speculation of indirect branches from the " 340 "generated code, either by avoiding them entirely or " 341 "lowering them with a speculation blocking construct", 342 [FeatureRetpolineIndirectCalls, 343 FeatureRetpolineIndirectBranches]>; 344 345// Rely on external thunks for the emitted retpoline calls. This allows users 346// to provide their own custom thunk definitions in highly specialized 347// environments such as a kernel that does boot-time hot patching. 348def FeatureRetpolineExternalThunk 349 : SubtargetFeature< 350 "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", 351 "When lowering an indirect call or branch using a `retpoline`, rely " 352 "on the specified user provided thunk rather than emitting one " 353 "ourselves. Only has effect when combined with some other retpoline " 354 "feature", [FeatureRetpolineIndirectCalls]>; 355 356// Mitigate LVI attacks against indirect calls/branches and call returns 357def FeatureLVIControlFlowIntegrity 358 : SubtargetFeature< 359 "lvi-cfi", "UseLVIControlFlowIntegrity", "true", 360 "Prevent indirect calls/branches from using a memory operand, and " 361 "precede all indirect calls/branches from a register with an " 362 "LFENCE instruction to serialize control flow. Also decompose RET " 363 "instructions into a POP+LFENCE+JMP sequence.">; 364 365// Enable SESES to mitigate speculative execution attacks 366def FeatureSpeculativeExecutionSideEffectSuppression 367 : SubtargetFeature< 368 "seses", "UseSpeculativeExecutionSideEffectSuppression", "true", 369 "Prevent speculative execution side channel timing attacks by " 370 "inserting a speculation barrier before memory reads, memory writes, " 371 "and conditional branches. Implies LVI Control Flow integrity.", 372 [FeatureLVIControlFlowIntegrity]>; 373 374// Mitigate LVI attacks against data loads 375def FeatureLVILoadHardening 376 : SubtargetFeature< 377 "lvi-load-hardening", "UseLVILoadHardening", "true", 378 "Insert LFENCE instructions to prevent data speculatively injected " 379 "into loads from being used maliciously.">; 380 381def FeatureTaggedGlobals 382 : SubtargetFeature< 383 "tagged-globals", "AllowTaggedGlobals", "true", 384 "Use an instruction sequence for taking the address of a global " 385 "that allows a memory tag in the upper address bits.">; 386 387// Control codegen mitigation against Straight Line Speculation vulnerability. 388def FeatureHardenSlsRet 389 : SubtargetFeature< 390 "harden-sls-ret", "HardenSlsRet", "true", 391 "Harden against straight line speculation across RET instructions.">; 392 393def FeatureHardenSlsIJmp 394 : SubtargetFeature< 395 "harden-sls-ijmp", "HardenSlsIJmp", "true", 396 "Harden against straight line speculation across indirect JMP instructions.">; 397 398//===----------------------------------------------------------------------===// 399// X86 Subtarget Tuning features 400//===----------------------------------------------------------------------===// 401 402def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", 403 "SHLD instruction is slow">; 404 405def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", 406 "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)">; 407 408def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow", 409 "true", 410 "PMADDWD is slower than PMULLD">; 411 412// FIXME: This should not apply to CPUs that do not have SSE. 413def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", 414 "IsUnalignedMem16Slow", "true", 415 "Slow unaligned 16-byte memory access">; 416 417def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", 418 "IsUnalignedMem32Slow", "true", 419 "Slow unaligned 32-byte memory access">; 420 421def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", 422 "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">; 423 424// True if 8-bit divisions are significantly faster than 425// 32-bit divisions and should be used when possible. 426def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb", 427 "HasSlowDivide32", "true", 428 "Use 8-bit divide for positive values less than 256">; 429 430// True if 32-bit divides are significantly faster than 431// 64-bit divisions and should be used when possible. 432def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl", 433 "HasSlowDivide64", "true", 434 "Use 32-bit divide for positive values less than 2^32">; 435 436def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions", 437 "PadShortFunctions", "true", 438 "Pad short functions (to prevent a stall when returning too early)">; 439 440// On some processors, instructions that implicitly take two memory operands are 441// slow. In practice, this means that CALL, PUSH, and POP with memory operands 442// should be avoided in favor of a MOV + register CALL/PUSH/POP. 443def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", 444 "SlowTwoMemOps", "true", 445 "Two memory operand instructions are slow">; 446 447// True if the LEA instruction inputs have to be ready at address generation 448// (AG) time. 449def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true", 450 "LEA instruction needs inputs at AG stage">; 451 452def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", 453 "LEA instruction with certain arguments is slow">; 454 455// True if the LEA instruction has all three source operands: base, index, 456// and offset or if the LEA instruction uses base and index registers where 457// the base is EBP, RBP,or R13 458def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", 459 "LEA instruction with 3 ops or certain registers is slow">; 460 461// True if INC and DEC instructions are slow when writing to flags 462def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", 463 "INC and DEC instructions are slower than ADD and SUB">; 464 465def TuningPOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", 466 "HasPOPCNTFalseDeps", "true", 467 "POPCNT has a false dependency on dest register">; 468 469def TuningLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", 470 "HasLZCNTFalseDeps", "true", 471 "LZCNT/TZCNT have a false dependency on dest register">; 472 473def TuningMULCFalseDeps : SubtargetFeature<"false-deps-mulc", 474 "HasMULCFalseDeps", "true", 475 "VF[C]MULCPH/SH has a false dependency on dest register">; 476 477def TuningPERMFalseDeps : SubtargetFeature<"false-deps-perm", 478 "HasPERMFalseDeps", "true", 479 "VPERMD/Q/PS/PD has a false dependency on dest register">; 480 481def TuningRANGEFalseDeps : SubtargetFeature<"false-deps-range", 482 "HasRANGEFalseDeps", "true", 483 "VRANGEPD/PS/SD/SS has a false dependency on dest register">; 484 485def TuningGETMANTFalseDeps : SubtargetFeature<"false-deps-getmant", 486 "HasGETMANTFalseDeps", "true", 487 "VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a" 488 " false dependency on dest register">; 489 490def TuningMULLQFalseDeps : SubtargetFeature<"false-deps-mullq", 491 "HasMULLQFalseDeps", "true", 492 "VPMULLQ has a false dependency on dest register">; 493 494def TuningSBBDepBreaking : SubtargetFeature<"sbb-dep-breaking", 495 "HasSBBDepBreaking", "true", 496 "SBB with same register has no source dependency">; 497 498// On recent X86 (port bound) processors, its preferable to combine to a single shuffle 499// using a variable mask over multiple fixed shuffles. 500def TuningFastVariableCrossLaneShuffle 501 : SubtargetFeature<"fast-variable-crosslane-shuffle", 502 "HasFastVariableCrossLaneShuffle", 503 "true", "Cross-lane shuffles with variable masks are fast">; 504def TuningFastVariablePerLaneShuffle 505 : SubtargetFeature<"fast-variable-perlane-shuffle", 506 "HasFastVariablePerLaneShuffle", 507 "true", "Per-lane shuffles with variable masks are fast">; 508 509// On some X86 processors, a vzeroupper instruction should be inserted after 510// using ymm/zmm registers before executing code that may use SSE instructions. 511def TuningInsertVZEROUPPER 512 : SubtargetFeature<"vzeroupper", 513 "InsertVZEROUPPER", 514 "true", "Should insert vzeroupper instructions">; 515 516// TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency 517// than the corresponding NR code. TuningFastVectorFSQRT should be enabled if 518// vector FSQRT has higher throughput than the corresponding NR code. 519// The idea is that throughput bound code is likely to be vectorized, so for 520// vectorized code we should care about the throughput of SQRT operations. 521// But if the code is scalar that probably means that the code has some kind of 522// dependency and we should care more about reducing the latency. 523 524// True if hardware SQRTSS instruction is at least as fast (latency) as 525// RSQRTSS followed by a Newton-Raphson iteration. 526def TuningFastScalarFSQRT 527 : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", 528 "true", "Scalar SQRT is fast (disable Newton-Raphson)">; 529// True if hardware SQRTPS/VSQRTPS instructions are at least as fast 530// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. 531def TuningFastVectorFSQRT 532 : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", 533 "true", "Vector SQRT is fast (disable Newton-Raphson)">; 534 535// If lzcnt has equivalent latency/throughput to most simple integer ops, it can 536// be used to replace test/set sequences. 537def TuningFastLZCNT 538 : SubtargetFeature< 539 "fast-lzcnt", "HasFastLZCNT", "true", 540 "LZCNT instructions are as fast as most simple integer ops">; 541 542// If the target can efficiently decode NOPs upto 7-bytes in length. 543def TuningFast7ByteNOP 544 : SubtargetFeature< 545 "fast-7bytenop", "HasFast7ByteNOP", "true", 546 "Target can quickly decode up to 7 byte NOPs">; 547 548// If the target can efficiently decode NOPs upto 11-bytes in length. 549def TuningFast11ByteNOP 550 : SubtargetFeature< 551 "fast-11bytenop", "HasFast11ByteNOP", "true", 552 "Target can quickly decode up to 11 byte NOPs">; 553 554// If the target can efficiently decode NOPs upto 15-bytes in length. 555def TuningFast15ByteNOP 556 : SubtargetFeature< 557 "fast-15bytenop", "HasFast15ByteNOP", "true", 558 "Target can quickly decode up to 15 byte NOPs">; 559 560// Sandy Bridge and newer processors can use SHLD with the same source on both 561// inputs to implement rotate to avoid the partial flag update of the normal 562// rotate instructions. 563def TuningFastSHLDRotate 564 : SubtargetFeature< 565 "fast-shld-rotate", "HasFastSHLDRotate", "true", 566 "SHLD can be used as a faster rotate">; 567 568// Bulldozer and newer processors can merge CMP/TEST (but not other 569// instructions) with conditional branches. 570def TuningBranchFusion 571 : SubtargetFeature<"branchfusion", "HasBranchFusion", "true", 572 "CMP/TEST can be fused with conditional branches">; 573 574// Sandy Bridge and newer processors have many instructions that can be 575// fused with conditional branches and pass through the CPU as a single 576// operation. 577def TuningMacroFusion 578 : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", 579 "Various instructions can be fused with conditional branches">; 580 581// Gather is available since Haswell (AVX2 set). So technically, we can 582// generate Gathers on all AVX2 processors. But the overhead on HSW is high. 583// Skylake Client processor has faster Gathers than HSW and performance is 584// similar to Skylake Server (AVX-512). 585def TuningFastGather 586 : SubtargetFeature<"fast-gather", "HasFastGather", "true", 587 "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">; 588 589def TuningPrefer128Bit 590 : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true", 591 "Prefer 128-bit AVX instructions">; 592 593def TuningPrefer256Bit 594 : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", 595 "Prefer 256-bit AVX instructions">; 596 597def TuningPreferMaskRegisters 598 : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true", 599 "Prefer AVX512 mask registers over PTEST/MOVMSK">; 600 601def TuningFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true", 602 "Indicates that the BEXTR instruction is implemented as a single uop " 603 "with good throughput">; 604 605// Combine vector math operations with shuffles into horizontal math 606// instructions if a CPU implements horizontal operations (introduced with 607// SSE3) with better latency/throughput than the alternative sequence. 608def TuningFastHorizontalOps 609 : SubtargetFeature< 610 "fast-hops", "HasFastHorizontalOps", "true", 611 "Prefer horizontal vector math instructions (haddp, phsub, etc.) over " 612 "normal vector instructions with shuffles">; 613 614def TuningFastScalarShiftMasks 615 : SubtargetFeature< 616 "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true", 617 "Prefer a left/right scalar logical shift pair over a shift+and pair">; 618 619def TuningFastVectorShiftMasks 620 : SubtargetFeature< 621 "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true", 622 "Prefer a left/right vector logical shift pair over a shift+and pair">; 623 624def TuningFastMOVBE 625 : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true", 626 "Prefer a movbe over a single-use load + bswap / single-use bswap + store">; 627 628def TuningUseSLMArithCosts 629 : SubtargetFeature<"use-slm-arith-costs", "UseSLMArithCosts", "true", 630 "Use Silvermont specific arithmetic costs">; 631 632def TuningUseGLMDivSqrtCosts 633 : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true", 634 "Use Goldmont specific floating point div/sqrt costs">; 635 636//===----------------------------------------------------------------------===// 637// X86 CPU Families 638// TODO: Remove these - use general tuning features to determine codegen. 639//===----------------------------------------------------------------------===// 640 641// Bonnell 642def ProcIntelAtom : SubtargetFeature<"", "IsAtom", "true", "Is Intel Atom processor">; 643 644//===----------------------------------------------------------------------===// 645// Register File Description 646//===----------------------------------------------------------------------===// 647 648include "X86RegisterInfo.td" 649include "X86RegisterBanks.td" 650 651//===----------------------------------------------------------------------===// 652// Instruction Descriptions 653//===----------------------------------------------------------------------===// 654 655include "X86Schedule.td" 656include "X86InstrInfo.td" 657include "X86SchedPredicates.td" 658 659def X86InstrInfo : InstrInfo; 660 661//===----------------------------------------------------------------------===// 662// X86 Scheduler Models 663//===----------------------------------------------------------------------===// 664 665include "X86ScheduleAtom.td" 666include "X86SchedSandyBridge.td" 667include "X86SchedHaswell.td" 668include "X86SchedBroadwell.td" 669include "X86ScheduleSLM.td" 670include "X86ScheduleZnver1.td" 671include "X86ScheduleZnver2.td" 672include "X86ScheduleZnver3.td" 673include "X86ScheduleBdVer2.td" 674include "X86ScheduleBtVer2.td" 675include "X86SchedSkylakeClient.td" 676include "X86SchedSkylakeServer.td" 677include "X86SchedIceLake.td" 678 679//===----------------------------------------------------------------------===// 680// X86 Processor Feature Lists 681//===----------------------------------------------------------------------===// 682 683def ProcessorFeatures { 684 // x86-64 and x86-64-v[234] 685 list<SubtargetFeature> X86_64V1Features = [ 686 FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX, FeatureSSE2, 687 FeatureFXSR, FeatureNOPL, FeatureX86_64, 688 ]; 689 list<SubtargetFeature> X86_64V2Features = !listconcat(X86_64V1Features, [ 690 FeatureCX16, FeatureLAHFSAHF64, FeatureCRC32, FeaturePOPCNT, 691 FeatureSSE42 692 ]); 693 list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [ 694 FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT, 695 FeatureMOVBE, FeatureXSAVE 696 ]); 697 list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [ 698 FeatureBWI, 699 FeatureCDI, 700 FeatureDQI, 701 FeatureVLX, 702 ]); 703 704 // Nehalem 705 list<SubtargetFeature> NHMFeatures = X86_64V2Features; 706 list<SubtargetFeature> NHMTuning = [TuningMacroFusion, 707 TuningInsertVZEROUPPER]; 708 709 // Westmere 710 list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL]; 711 list<SubtargetFeature> WSMTuning = NHMTuning; 712 list<SubtargetFeature> WSMFeatures = 713 !listconcat(NHMFeatures, WSMAdditionalFeatures); 714 715 // Sandybridge 716 list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX, 717 FeatureXSAVE, 718 FeatureXSAVEOPT]; 719 list<SubtargetFeature> SNBTuning = [TuningMacroFusion, 720 TuningSlow3OpsLEA, 721 TuningSlowDivide64, 722 TuningSlowUAMem32, 723 TuningFastScalarFSQRT, 724 TuningFastSHLDRotate, 725 TuningFast15ByteNOP, 726 TuningPOPCNTFalseDeps, 727 TuningInsertVZEROUPPER]; 728 list<SubtargetFeature> SNBFeatures = 729 !listconcat(WSMFeatures, SNBAdditionalFeatures); 730 731 // Ivybridge 732 list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND, 733 FeatureF16C, 734 FeatureFSGSBase]; 735 list<SubtargetFeature> IVBTuning = SNBTuning; 736 list<SubtargetFeature> IVBFeatures = 737 !listconcat(SNBFeatures, IVBAdditionalFeatures); 738 739 // Haswell 740 list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2, 741 FeatureBMI, 742 FeatureBMI2, 743 FeatureERMSB, 744 FeatureFMA, 745 FeatureINVPCID, 746 FeatureLZCNT, 747 FeatureMOVBE]; 748 list<SubtargetFeature> HSWTuning = [TuningMacroFusion, 749 TuningSlow3OpsLEA, 750 TuningSlowDivide64, 751 TuningFastScalarFSQRT, 752 TuningFastSHLDRotate, 753 TuningFast15ByteNOP, 754 TuningFastVariableCrossLaneShuffle, 755 TuningFastVariablePerLaneShuffle, 756 TuningPOPCNTFalseDeps, 757 TuningLZCNTFalseDeps, 758 TuningInsertVZEROUPPER]; 759 list<SubtargetFeature> HSWFeatures = 760 !listconcat(IVBFeatures, HSWAdditionalFeatures); 761 762 // Broadwell 763 list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX, 764 FeatureRDSEED, 765 FeaturePRFCHW]; 766 list<SubtargetFeature> BDWTuning = HSWTuning; 767 list<SubtargetFeature> BDWFeatures = 768 !listconcat(HSWFeatures, BDWAdditionalFeatures); 769 770 // Skylake 771 list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES, 772 FeatureXSAVEC, 773 FeatureXSAVES, 774 FeatureCLFLUSHOPT]; 775 list<SubtargetFeature> SKLTuning = [TuningFastGather, 776 TuningMacroFusion, 777 TuningSlow3OpsLEA, 778 TuningSlowDivide64, 779 TuningFastScalarFSQRT, 780 TuningFastVectorFSQRT, 781 TuningFastSHLDRotate, 782 TuningFast15ByteNOP, 783 TuningFastVariableCrossLaneShuffle, 784 TuningFastVariablePerLaneShuffle, 785 TuningPOPCNTFalseDeps, 786 TuningInsertVZEROUPPER]; 787 list<SubtargetFeature> SKLFeatures = 788 !listconcat(BDWFeatures, SKLAdditionalFeatures); 789 790 // Skylake-AVX512 791 list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES, 792 FeatureXSAVEC, 793 FeatureXSAVES, 794 FeatureCLFLUSHOPT, 795 FeatureAVX512, 796 FeatureCDI, 797 FeatureDQI, 798 FeatureBWI, 799 FeatureVLX, 800 FeaturePKU, 801 FeatureCLWB]; 802 list<SubtargetFeature> SKXTuning = [TuningFastGather, 803 TuningMacroFusion, 804 TuningSlow3OpsLEA, 805 TuningSlowDivide64, 806 TuningFastScalarFSQRT, 807 TuningFastVectorFSQRT, 808 TuningFastSHLDRotate, 809 TuningFast15ByteNOP, 810 TuningFastVariableCrossLaneShuffle, 811 TuningFastVariablePerLaneShuffle, 812 TuningPrefer256Bit, 813 TuningPOPCNTFalseDeps, 814 TuningInsertVZEROUPPER]; 815 list<SubtargetFeature> SKXFeatures = 816 !listconcat(BDWFeatures, SKXAdditionalFeatures); 817 818 // Cascadelake 819 list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI]; 820 list<SubtargetFeature> CLXTuning = SKXTuning; 821 list<SubtargetFeature> CLXFeatures = 822 !listconcat(SKXFeatures, CLXAdditionalFeatures); 823 824 // Cooperlake 825 list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16]; 826 list<SubtargetFeature> CPXTuning = SKXTuning; 827 list<SubtargetFeature> CPXFeatures = 828 !listconcat(CLXFeatures, CPXAdditionalFeatures); 829 830 // Cannonlake 831 list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512, 832 FeatureCDI, 833 FeatureDQI, 834 FeatureBWI, 835 FeatureVLX, 836 FeaturePKU, 837 FeatureVBMI, 838 FeatureIFMA, 839 FeatureSHA]; 840 list<SubtargetFeature> CNLTuning = [TuningFastGather, 841 TuningMacroFusion, 842 TuningSlow3OpsLEA, 843 TuningSlowDivide64, 844 TuningFastScalarFSQRT, 845 TuningFastVectorFSQRT, 846 TuningFastSHLDRotate, 847 TuningFast15ByteNOP, 848 TuningFastVariableCrossLaneShuffle, 849 TuningFastVariablePerLaneShuffle, 850 TuningPrefer256Bit, 851 TuningInsertVZEROUPPER]; 852 list<SubtargetFeature> CNLFeatures = 853 !listconcat(SKLFeatures, CNLAdditionalFeatures); 854 855 // Icelake 856 list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG, 857 FeatureVAES, 858 FeatureVBMI2, 859 FeatureVNNI, 860 FeatureVPCLMULQDQ, 861 FeatureVPOPCNTDQ, 862 FeatureGFNI, 863 FeatureRDPID, 864 FeatureFSRM]; 865 list<SubtargetFeature> ICLTuning = [TuningFastGather, 866 TuningMacroFusion, 867 TuningSlow3OpsLEA, 868 TuningSlowDivide64, 869 TuningFastScalarFSQRT, 870 TuningFastVectorFSQRT, 871 TuningFastSHLDRotate, 872 TuningFast15ByteNOP, 873 TuningFastVariableCrossLaneShuffle, 874 TuningFastVariablePerLaneShuffle, 875 TuningPrefer256Bit, 876 TuningInsertVZEROUPPER]; 877 list<SubtargetFeature> ICLFeatures = 878 !listconcat(CNLFeatures, ICLAdditionalFeatures); 879 880 // Icelake Server 881 list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG, 882 FeatureCLWB, 883 FeatureWBNOINVD]; 884 list<SubtargetFeature> ICXTuning = ICLTuning; 885 list<SubtargetFeature> ICXFeatures = 886 !listconcat(ICLFeatures, ICXAdditionalFeatures); 887 888 // Tigerlake 889 list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT, 890 FeatureCLWB, 891 FeatureMOVDIRI, 892 FeatureMOVDIR64B, 893 FeatureSHSTK]; 894 list<SubtargetFeature> TGLTuning = ICLTuning; 895 list<SubtargetFeature> TGLFeatures = 896 !listconcat(ICLFeatures, TGLAdditionalFeatures ); 897 898 // Sapphirerapids 899 list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE, 900 FeatureAMXINT8, 901 FeatureAMXBF16, 902 FeatureBF16, 903 FeatureSERIALIZE, 904 FeatureCLDEMOTE, 905 FeatureWAITPKG, 906 FeaturePTWRITE, 907 FeatureFP16, 908 FeatureAVXVNNI, 909 FeatureTSXLDTRK, 910 FeatureENQCMD, 911 FeatureSHSTK, 912 FeatureVP2INTERSECT, 913 FeatureMOVDIRI, 914 FeatureMOVDIR64B, 915 FeatureUINTR]; 916 list<SubtargetFeature> SPRAdditionalTuning = [TuningMULCFalseDeps, 917 TuningPERMFalseDeps, 918 TuningRANGEFalseDeps, 919 TuningGETMANTFalseDeps, 920 TuningMULLQFalseDeps]; 921 list<SubtargetFeature> SPRTuning = !listconcat(ICXTuning, SPRAdditionalTuning); 922 list<SubtargetFeature> SPRFeatures = 923 !listconcat(ICXFeatures, SPRAdditionalFeatures); 924 925 // Atom 926 list<SubtargetFeature> AtomFeatures = [FeatureX87, 927 FeatureCX8, 928 FeatureCMOV, 929 FeatureMMX, 930 FeatureSSSE3, 931 FeatureFXSR, 932 FeatureNOPL, 933 FeatureX86_64, 934 FeatureCX16, 935 FeatureMOVBE, 936 FeatureLAHFSAHF64]; 937 list<SubtargetFeature> AtomTuning = [ProcIntelAtom, 938 TuningSlowUAMem16, 939 TuningLEAForSP, 940 TuningSlowDivide32, 941 TuningSlowDivide64, 942 TuningSlowTwoMemOps, 943 TuningLEAUsesAG, 944 TuningPadShortFunctions, 945 TuningInsertVZEROUPPER]; 946 947 // Silvermont 948 list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42, 949 FeatureCRC32, 950 FeaturePOPCNT, 951 FeaturePCLMUL, 952 FeaturePRFCHW, 953 FeatureRDRAND]; 954 list<SubtargetFeature> SLMTuning = [TuningUseSLMArithCosts, 955 TuningSlowTwoMemOps, 956 TuningSlowLEA, 957 TuningSlowIncDec, 958 TuningSlowDivide64, 959 TuningSlowPMULLD, 960 TuningFast7ByteNOP, 961 TuningFastMOVBE, 962 TuningPOPCNTFalseDeps, 963 TuningInsertVZEROUPPER]; 964 list<SubtargetFeature> SLMFeatures = 965 !listconcat(AtomFeatures, SLMAdditionalFeatures); 966 967 // Goldmont 968 list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES, 969 FeatureSHA, 970 FeatureRDSEED, 971 FeatureXSAVE, 972 FeatureXSAVEOPT, 973 FeatureXSAVEC, 974 FeatureXSAVES, 975 FeatureCLFLUSHOPT, 976 FeatureFSGSBase]; 977 list<SubtargetFeature> GLMTuning = [TuningUseGLMDivSqrtCosts, 978 TuningSlowTwoMemOps, 979 TuningSlowLEA, 980 TuningSlowIncDec, 981 TuningFastMOVBE, 982 TuningPOPCNTFalseDeps, 983 TuningInsertVZEROUPPER]; 984 list<SubtargetFeature> GLMFeatures = 985 !listconcat(SLMFeatures, GLMAdditionalFeatures); 986 987 // Goldmont Plus 988 list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE, 989 FeatureRDPID]; 990 list<SubtargetFeature> GLPTuning = [TuningUseGLMDivSqrtCosts, 991 TuningSlowTwoMemOps, 992 TuningSlowLEA, 993 TuningSlowIncDec, 994 TuningFastMOVBE, 995 TuningInsertVZEROUPPER]; 996 list<SubtargetFeature> GLPFeatures = 997 !listconcat(GLMFeatures, GLPAdditionalFeatures); 998 999 // Tremont 1000 list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB, 1001 FeatureGFNI]; 1002 list<SubtargetFeature> TRMTuning = GLPTuning; 1003 list<SubtargetFeature> TRMFeatures = 1004 !listconcat(GLPFeatures, TRMAdditionalFeatures); 1005 1006 // Alderlake 1007 list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE, 1008 FeaturePCONFIG, 1009 FeatureSHSTK, 1010 FeatureWIDEKL, 1011 FeatureINVPCID, 1012 FeatureADX, 1013 FeatureFMA, 1014 FeatureVAES, 1015 FeatureVPCLMULQDQ, 1016 FeatureF16C, 1017 FeatureBMI, 1018 FeatureBMI2, 1019 FeatureLZCNT, 1020 FeatureAVXVNNI, 1021 FeaturePKU, 1022 FeatureHRESET, 1023 FeatureCLDEMOTE, 1024 FeatureMOVDIRI, 1025 FeatureMOVDIR64B, 1026 FeatureWAITPKG]; 1027 list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps]; 1028 list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning); 1029 list<SubtargetFeature> ADLFeatures = 1030 !listconcat(TRMFeatures, ADLAdditionalFeatures); 1031 1032 // Knights Landing 1033 list<SubtargetFeature> KNLFeatures = [FeatureX87, 1034 FeatureCX8, 1035 FeatureCMOV, 1036 FeatureMMX, 1037 FeatureFXSR, 1038 FeatureNOPL, 1039 FeatureX86_64, 1040 FeatureCX16, 1041 FeatureCRC32, 1042 FeaturePOPCNT, 1043 FeaturePCLMUL, 1044 FeatureXSAVE, 1045 FeatureXSAVEOPT, 1046 FeatureLAHFSAHF64, 1047 FeatureAES, 1048 FeatureRDRAND, 1049 FeatureF16C, 1050 FeatureFSGSBase, 1051 FeatureAVX512, 1052 FeatureERI, 1053 FeatureCDI, 1054 FeaturePFI, 1055 FeaturePREFETCHWT1, 1056 FeatureADX, 1057 FeatureRDSEED, 1058 FeatureMOVBE, 1059 FeatureLZCNT, 1060 FeatureBMI, 1061 FeatureBMI2, 1062 FeatureFMA, 1063 FeaturePRFCHW]; 1064 list<SubtargetFeature> KNLTuning = [TuningSlowDivide64, 1065 TuningSlow3OpsLEA, 1066 TuningSlowIncDec, 1067 TuningSlowTwoMemOps, 1068 TuningPreferMaskRegisters, 1069 TuningFastGather, 1070 TuningFastMOVBE, 1071 TuningSlowPMADDWD]; 1072 // TODO Add AVX5124FMAPS/AVX5124VNNIW features 1073 list<SubtargetFeature> KNMFeatures = 1074 !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); 1075 1076 // Barcelona 1077 list<SubtargetFeature> BarcelonaFeatures = [FeatureX87, 1078 FeatureCX8, 1079 FeatureSSE4A, 1080 Feature3DNowA, 1081 FeatureFXSR, 1082 FeatureNOPL, 1083 FeatureCX16, 1084 FeaturePRFCHW, 1085 FeatureLZCNT, 1086 FeaturePOPCNT, 1087 FeatureLAHFSAHF64, 1088 FeatureCMOV, 1089 FeatureX86_64]; 1090 list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks, 1091 TuningSlowSHLD, 1092 TuningSBBDepBreaking, 1093 TuningInsertVZEROUPPER]; 1094 1095 // Bobcat 1096 list<SubtargetFeature> BtVer1Features = [FeatureX87, 1097 FeatureCX8, 1098 FeatureCMOV, 1099 FeatureMMX, 1100 FeatureSSSE3, 1101 FeatureSSE4A, 1102 FeatureFXSR, 1103 FeatureNOPL, 1104 FeatureX86_64, 1105 FeatureCX16, 1106 FeaturePRFCHW, 1107 FeatureLZCNT, 1108 FeaturePOPCNT, 1109 FeatureLAHFSAHF64]; 1110 list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP, 1111 TuningFastScalarShiftMasks, 1112 TuningFastVectorShiftMasks, 1113 TuningSlowSHLD, 1114 TuningSBBDepBreaking, 1115 TuningInsertVZEROUPPER]; 1116 1117 // Jaguar 1118 list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX, 1119 FeatureAES, 1120 FeatureCRC32, 1121 FeaturePCLMUL, 1122 FeatureBMI, 1123 FeatureF16C, 1124 FeatureMOVBE, 1125 FeatureXSAVE, 1126 FeatureXSAVEOPT]; 1127 list<SubtargetFeature> BtVer2Tuning = [TuningFastLZCNT, 1128 TuningFastBEXTR, 1129 TuningFastHorizontalOps, 1130 TuningFast15ByteNOP, 1131 TuningFastScalarShiftMasks, 1132 TuningFastVectorShiftMasks, 1133 TuningFastMOVBE, 1134 TuningSBBDepBreaking, 1135 TuningSlowSHLD]; 1136 list<SubtargetFeature> BtVer2Features = 1137 !listconcat(BtVer1Features, BtVer2AdditionalFeatures); 1138 1139 // Bulldozer 1140 list<SubtargetFeature> BdVer1Features = [FeatureX87, 1141 FeatureCX8, 1142 FeatureCMOV, 1143 FeatureXOP, 1144 FeatureX86_64, 1145 FeatureCX16, 1146 FeatureAES, 1147 FeatureCRC32, 1148 FeaturePRFCHW, 1149 FeaturePCLMUL, 1150 FeatureMMX, 1151 FeatureFXSR, 1152 FeatureNOPL, 1153 FeatureLZCNT, 1154 FeaturePOPCNT, 1155 FeatureXSAVE, 1156 FeatureLWP, 1157 FeatureLAHFSAHF64]; 1158 list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD, 1159 TuningFast11ByteNOP, 1160 TuningFastScalarShiftMasks, 1161 TuningBranchFusion, 1162 TuningSBBDepBreaking, 1163 TuningInsertVZEROUPPER]; 1164 1165 // PileDriver 1166 list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C, 1167 FeatureBMI, 1168 FeatureTBM, 1169 FeatureFMA]; 1170 list<SubtargetFeature> BdVer2AdditionalTuning = [TuningFastBEXTR, 1171 TuningFastMOVBE]; 1172 list<SubtargetFeature> BdVer2Tuning = 1173 !listconcat(BdVer1Tuning, BdVer2AdditionalTuning); 1174 list<SubtargetFeature> BdVer2Features = 1175 !listconcat(BdVer1Features, BdVer2AdditionalFeatures); 1176 1177 // Steamroller 1178 list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT, 1179 FeatureFSGSBase]; 1180 list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning; 1181 list<SubtargetFeature> BdVer3Features = 1182 !listconcat(BdVer2Features, BdVer3AdditionalFeatures); 1183 1184 // Excavator 1185 list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2, 1186 FeatureBMI2, 1187 FeatureMOVBE, 1188 FeatureRDRAND, 1189 FeatureMWAITX]; 1190 list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning; 1191 list<SubtargetFeature> BdVer4Features = 1192 !listconcat(BdVer3Features, BdVer4AdditionalFeatures); 1193 1194 1195 // AMD Zen Processors common ISAs 1196 list<SubtargetFeature> ZNFeatures = [FeatureADX, 1197 FeatureAES, 1198 FeatureAVX2, 1199 FeatureBMI, 1200 FeatureBMI2, 1201 FeatureCLFLUSHOPT, 1202 FeatureCLZERO, 1203 FeatureCMOV, 1204 FeatureX86_64, 1205 FeatureCX16, 1206 FeatureCRC32, 1207 FeatureF16C, 1208 FeatureFMA, 1209 FeatureFSGSBase, 1210 FeatureFXSR, 1211 FeatureNOPL, 1212 FeatureLAHFSAHF64, 1213 FeatureLZCNT, 1214 FeatureMMX, 1215 FeatureMOVBE, 1216 FeatureMWAITX, 1217 FeaturePCLMUL, 1218 FeaturePOPCNT, 1219 FeaturePRFCHW, 1220 FeatureRDRAND, 1221 FeatureRDSEED, 1222 FeatureSHA, 1223 FeatureSSE4A, 1224 FeatureX87, 1225 FeatureXSAVE, 1226 FeatureXSAVEC, 1227 FeatureXSAVEOPT, 1228 FeatureXSAVES]; 1229 list<SubtargetFeature> ZNTuning = [TuningFastLZCNT, 1230 TuningFastBEXTR, 1231 TuningFast15ByteNOP, 1232 TuningBranchFusion, 1233 TuningFastScalarFSQRT, 1234 TuningFastVectorFSQRT, 1235 TuningFastScalarShiftMasks, 1236 TuningFastVariablePerLaneShuffle, 1237 TuningFastMOVBE, 1238 TuningSlowSHLD, 1239 TuningSBBDepBreaking, 1240 TuningInsertVZEROUPPER]; 1241 list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB, 1242 FeatureRDPID, 1243 FeatureRDPRU, 1244 FeatureWBNOINVD]; 1245 list<SubtargetFeature> ZN2Tuning = ZNTuning; 1246 list<SubtargetFeature> ZN2Features = 1247 !listconcat(ZNFeatures, ZN2AdditionalFeatures); 1248 list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM, 1249 FeatureINVPCID, 1250 FeaturePKU, 1251 FeatureVAES, 1252 FeatureVPCLMULQDQ]; 1253 list<SubtargetFeature> ZN3AdditionalTuning = [TuningMacroFusion]; 1254 list<SubtargetFeature> ZN3Tuning = 1255 !listconcat(ZN2Tuning, ZN3AdditionalTuning); 1256 list<SubtargetFeature> ZN3Features = 1257 !listconcat(ZN2Features, ZN3AdditionalFeatures); 1258} 1259 1260//===----------------------------------------------------------------------===// 1261// X86 processors supported. 1262//===----------------------------------------------------------------------===// 1263 1264class Proc<string Name, list<SubtargetFeature> Features, 1265 list<SubtargetFeature> TuneFeatures> 1266 : ProcessorModel<Name, GenericModel, Features, TuneFeatures>; 1267 1268class ProcModel<string Name, SchedMachineModel Model, 1269 list<SubtargetFeature> Features, 1270 list<SubtargetFeature> TuneFeatures> 1271 : ProcessorModel<Name, Model, Features, TuneFeatures>; 1272 1273// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled 1274// if i386/i486 is specifically requested. 1275// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget 1276// constructor checks that any CPU used in 64-bit mode has FeatureX86_64 1277// enabled. It has no effect on code generation. 1278// NOTE: As a default tuning, "generic" aims to produce code optimized for the 1279// most common X86 processors. The tunings might be changed over time. It is 1280// recommended to use "tune-cpu"="x86-64" in function attribute for consistency. 1281def : ProcModel<"generic", SandyBridgeModel, 1282 [FeatureX87, FeatureCX8, FeatureX86_64], 1283 [TuningSlow3OpsLEA, 1284 TuningSlowDivide64, 1285 TuningMacroFusion, 1286 TuningFastScalarFSQRT, 1287 TuningFast15ByteNOP, 1288 TuningInsertVZEROUPPER]>; 1289 1290def : Proc<"i386", [FeatureX87], 1291 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1292def : Proc<"i486", [FeatureX87], 1293 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1294def : Proc<"i586", [FeatureX87, FeatureCX8], 1295 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1296def : Proc<"pentium", [FeatureX87, FeatureCX8], 1297 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1298def : Proc<"pentium-mmx", [FeatureX87, FeatureCX8, FeatureMMX], 1299 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1300 1301def : Proc<"i686", [FeatureX87, FeatureCX8, FeatureCMOV], 1302 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1303def : Proc<"pentiumpro", [FeatureX87, FeatureCX8, FeatureCMOV, 1304 FeatureNOPL], 1305 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1306 1307def : Proc<"pentium2", [FeatureX87, FeatureCX8, FeatureMMX, FeatureCMOV, 1308 FeatureFXSR, FeatureNOPL], 1309 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1310 1311foreach P = ["pentium3", "pentium3m"] in { 1312 def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX, 1313 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV], 1314 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1315} 1316 1317// Enable the PostRAScheduler for SSE2 and SSE3 class cpus. 1318// The intent is to enable it for pentium4 which is the current default 1319// processor in a vanilla 32-bit clang compilation when no specific 1320// architecture is specified. This generally gives a nice performance 1321// increase on silvermont, with largely neutral behavior on other 1322// contemporary large core processors. 1323// pentium-m, pentium4m, prescott and nocona are included as a preventative 1324// measure to avoid performance surprises, in case clang's default cpu 1325// changes slightly. 1326 1327def : ProcModel<"pentium-m", GenericPostRAModel, 1328 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2, 1329 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1330 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1331 1332foreach P = ["pentium4", "pentium4m"] in { 1333 def : ProcModel<P, GenericPostRAModel, 1334 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2, 1335 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1336 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1337} 1338 1339// Intel Quark. 1340def : Proc<"lakemont", [FeatureCX8], 1341 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1342 1343// Intel Core Duo. 1344def : ProcModel<"yonah", SandyBridgeModel, 1345 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3, 1346 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1347 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1348 1349// NetBurst. 1350def : ProcModel<"prescott", GenericPostRAModel, 1351 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3, 1352 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1353 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1354def : ProcModel<"nocona", GenericPostRAModel, [ 1355 FeatureX87, 1356 FeatureCX8, 1357 FeatureCMOV, 1358 FeatureMMX, 1359 FeatureSSE3, 1360 FeatureFXSR, 1361 FeatureNOPL, 1362 FeatureX86_64, 1363 FeatureCX16, 1364], 1365[ 1366 TuningSlowUAMem16, 1367 TuningInsertVZEROUPPER 1368]>; 1369 1370// Intel Core 2 Solo/Duo. 1371def : ProcModel<"core2", SandyBridgeModel, [ 1372 FeatureX87, 1373 FeatureCX8, 1374 FeatureCMOV, 1375 FeatureMMX, 1376 FeatureSSSE3, 1377 FeatureFXSR, 1378 FeatureNOPL, 1379 FeatureX86_64, 1380 FeatureCX16, 1381 FeatureLAHFSAHF64 1382], 1383[ 1384 TuningMacroFusion, 1385 TuningSlowUAMem16, 1386 TuningInsertVZEROUPPER 1387]>; 1388def : ProcModel<"penryn", SandyBridgeModel, [ 1389 FeatureX87, 1390 FeatureCX8, 1391 FeatureCMOV, 1392 FeatureMMX, 1393 FeatureSSE41, 1394 FeatureFXSR, 1395 FeatureNOPL, 1396 FeatureX86_64, 1397 FeatureCX16, 1398 FeatureLAHFSAHF64 1399], 1400[ 1401 TuningMacroFusion, 1402 TuningSlowUAMem16, 1403 TuningInsertVZEROUPPER 1404]>; 1405 1406// Atom CPUs. 1407foreach P = ["bonnell", "atom"] in { 1408 def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures, 1409 ProcessorFeatures.AtomTuning>; 1410} 1411 1412foreach P = ["silvermont", "slm"] in { 1413 def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures, 1414 ProcessorFeatures.SLMTuning>; 1415} 1416 1417def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures, 1418 ProcessorFeatures.GLMTuning>; 1419def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures, 1420 ProcessorFeatures.GLPTuning>; 1421def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures, 1422 ProcessorFeatures.TRMTuning>; 1423 1424// "Arrandale" along with corei3 and corei5 1425foreach P = ["nehalem", "corei7"] in { 1426 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures, 1427 ProcessorFeatures.NHMTuning>; 1428} 1429 1430// Westmere is the corei3/i5/i7 path from nehalem to sandybridge 1431def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures, 1432 ProcessorFeatures.WSMTuning>; 1433 1434foreach P = ["sandybridge", "corei7-avx"] in { 1435 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures, 1436 ProcessorFeatures.SNBTuning>; 1437} 1438 1439foreach P = ["ivybridge", "core-avx-i"] in { 1440 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures, 1441 ProcessorFeatures.IVBTuning>; 1442} 1443 1444foreach P = ["haswell", "core-avx2"] in { 1445 def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures, 1446 ProcessorFeatures.HSWTuning>; 1447} 1448 1449def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures, 1450 ProcessorFeatures.BDWTuning>; 1451 1452def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures, 1453 ProcessorFeatures.SKLTuning>; 1454 1455// FIXME: define KNL scheduler model 1456def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures, 1457 ProcessorFeatures.KNLTuning>; 1458def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures, 1459 ProcessorFeatures.KNLTuning>; 1460 1461foreach P = ["skylake-avx512", "skx"] in { 1462 def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures, 1463 ProcessorFeatures.SKXTuning>; 1464} 1465 1466def : ProcModel<"cascadelake", SkylakeServerModel, 1467 ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>; 1468def : ProcModel<"cooperlake", SkylakeServerModel, 1469 ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>; 1470def : ProcModel<"cannonlake", SkylakeServerModel, 1471 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>; 1472def : ProcModel<"icelake-client", IceLakeModel, 1473 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; 1474def : ProcModel<"rocketlake", IceLakeModel, 1475 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; 1476def : ProcModel<"icelake-server", IceLakeModel, 1477 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>; 1478def : ProcModel<"tigerlake", IceLakeModel, 1479 ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>; 1480def : ProcModel<"sapphirerapids", SkylakeServerModel, 1481 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>; 1482def : ProcModel<"alderlake", SkylakeClientModel, 1483 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>; 1484 1485// AMD CPUs. 1486 1487def : Proc<"k6", [FeatureX87, FeatureCX8, FeatureMMX], 1488 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1489def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow], 1490 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1491def : Proc<"k6-3", [FeatureX87, FeatureCX8, Feature3DNow], 1492 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1493 1494foreach P = ["athlon", "athlon-tbird"] in { 1495 def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, Feature3DNowA, 1496 FeatureNOPL], 1497 [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1498} 1499 1500foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { 1501 def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, 1502 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL], 1503 [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1504} 1505 1506foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { 1507 def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2, Feature3DNowA, 1508 FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV], 1509 [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16, 1510 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>; 1511} 1512 1513foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { 1514 def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3, Feature3DNowA, 1515 FeatureFXSR, FeatureNOPL, FeatureCX16, FeatureCMOV, 1516 FeatureX86_64], 1517 [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16, 1518 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>; 1519} 1520 1521foreach P = ["amdfam10", "barcelona"] in { 1522 def : Proc<P, ProcessorFeatures.BarcelonaFeatures, 1523 ProcessorFeatures.BarcelonaTuning>; 1524} 1525 1526// Bobcat 1527def : Proc<"btver1", ProcessorFeatures.BtVer1Features, 1528 ProcessorFeatures.BtVer1Tuning>; 1529// Jaguar 1530def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features, 1531 ProcessorFeatures.BtVer2Tuning>; 1532 1533// Bulldozer 1534def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features, 1535 ProcessorFeatures.BdVer1Tuning>; 1536// Piledriver 1537def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features, 1538 ProcessorFeatures.BdVer2Tuning>; 1539// Steamroller 1540def : Proc<"bdver3", ProcessorFeatures.BdVer3Features, 1541 ProcessorFeatures.BdVer3Tuning>; 1542// Excavator 1543def : Proc<"bdver4", ProcessorFeatures.BdVer4Features, 1544 ProcessorFeatures.BdVer4Tuning>; 1545 1546def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures, 1547 ProcessorFeatures.ZNTuning>; 1548def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features, 1549 ProcessorFeatures.ZN2Tuning>; 1550def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features, 1551 ProcessorFeatures.ZN3Tuning>; 1552 1553def : Proc<"geode", [FeatureX87, FeatureCX8, Feature3DNowA], 1554 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1555 1556def : Proc<"winchip-c6", [FeatureX87, FeatureMMX], 1557 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1558def : Proc<"winchip2", [FeatureX87, Feature3DNow], 1559 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1560def : Proc<"c3", [FeatureX87, Feature3DNow], 1561 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1562def : Proc<"c3-2", [FeatureX87, FeatureCX8, FeatureMMX, 1563 FeatureSSE1, FeatureFXSR, FeatureCMOV], 1564 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; 1565 1566// We also provide a generic 64-bit specific x86 processor model which tries to 1567// be good for modern chips without enabling instruction set encodings past the 1568// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and 1569// modern 64-bit x86 chip, and enables features that are generally beneficial. 1570// 1571// We currently use the Sandy Bridge model as the default scheduling model as 1572// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which 1573// covers a huge swath of x86 processors. If there are specific scheduling 1574// knobs which need to be tuned differently for AMD chips, we might consider 1575// forming a common base for them. 1576def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features, 1577[ 1578 TuningSlow3OpsLEA, 1579 TuningSlowDivide64, 1580 TuningSlowIncDec, 1581 TuningMacroFusion, 1582 TuningInsertVZEROUPPER 1583]>; 1584 1585// x86-64 micro-architecture levels. 1586def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features, 1587 ProcessorFeatures.SNBTuning>; 1588// Close to Haswell. 1589def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features, 1590 ProcessorFeatures.HSWTuning>; 1591// Close to the AVX-512 level implemented by Xeon Scalable Processors. 1592def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features, 1593 ProcessorFeatures.SKXTuning>; 1594 1595//===----------------------------------------------------------------------===// 1596// Calling Conventions 1597//===----------------------------------------------------------------------===// 1598 1599include "X86CallingConv.td" 1600 1601 1602//===----------------------------------------------------------------------===// 1603// Assembly Parser 1604//===----------------------------------------------------------------------===// 1605 1606def ATTAsmParserVariant : AsmParserVariant { 1607 int Variant = 0; 1608 1609 // Variant name. 1610 string Name = "att"; 1611 1612 // Discard comments in assembly strings. 1613 string CommentDelimiter = "#"; 1614 1615 // Recognize hard coded registers. 1616 string RegisterPrefix = "%"; 1617} 1618 1619def IntelAsmParserVariant : AsmParserVariant { 1620 int Variant = 1; 1621 1622 // Variant name. 1623 string Name = "intel"; 1624 1625 // Discard comments in assembly strings. 1626 string CommentDelimiter = ";"; 1627 1628 // Recognize hard coded registers. 1629 string RegisterPrefix = ""; 1630} 1631 1632//===----------------------------------------------------------------------===// 1633// Assembly Printers 1634//===----------------------------------------------------------------------===// 1635 1636// The X86 target supports two different syntaxes for emitting machine code. 1637// This is controlled by the -x86-asm-syntax={att|intel} 1638def ATTAsmWriter : AsmWriter { 1639 string AsmWriterClassName = "ATTInstPrinter"; 1640 int Variant = 0; 1641} 1642def IntelAsmWriter : AsmWriter { 1643 string AsmWriterClassName = "IntelInstPrinter"; 1644 int Variant = 1; 1645} 1646 1647def X86 : Target { 1648 // Information about the instructions... 1649 let InstructionSet = X86InstrInfo; 1650 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; 1651 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 1652 let AllowRegisterRenaming = 1; 1653} 1654 1655//===----------------------------------------------------------------------===// 1656// Pfm Counters 1657//===----------------------------------------------------------------------===// 1658 1659include "X86PfmCounters.td" 1660