1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the X86-32 and X86-64 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 17 "(State.getMachineFunction().getSubtarget()).", F), 18 A>; 19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const X86Subtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", F), 24 A>; 25 26// Register classes for RegCall 27class RC_X86_RegCall { 28 list<Register> GPR_8 = []; 29 list<Register> GPR_16 = []; 30 list<Register> GPR_32 = []; 31 list<Register> GPR_64 = []; 32 list<Register> FP_CALL = [FP0]; 33 list<Register> FP_RET = [FP0, FP1]; 34 list<Register> XMM = []; 35 list<Register> YMM = []; 36 list<Register> ZMM = []; 37} 38 39// RegCall register classes for 32 bits 40def RC_X86_32_RegCall : RC_X86_RegCall { 41 let GPR_8 = [AL, CL, DL, DIL, SIL]; 42 let GPR_16 = [AX, CX, DX, DI, SI]; 43 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 44 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 45 ///< \todo Fix AssignToReg to enable empty lists 46 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 47 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 48 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 49} 50 51class RC_X86_64_RegCall : RC_X86_RegCall { 52 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 53 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; 54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, 55 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; 56 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, 57 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; 58} 59 60def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { 61 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; 62 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; 63 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; 65} 66 67def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { 68 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; 69 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; 70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; 72} 73 74// X86-64 Intel regcall calling convention. 75multiclass X86_RegCall_base<RC_X86_RegCall RC> { 76def CC_#NAME : CallingConv<[ 77 // Handles byval parameters. 78 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>, 79 CCIfByVal<CCPassByVal<4, 4>>, 80 81 // Promote i1/i8/i16/v1i1 arguments to i32. 82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 83 84 // Promote v8i1/v16i1/v32i1 arguments to i32. 85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>, 86 87 // bool, char, int, enum, long, pointer --> GPR 88 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 89 90 // long long, __int64 --> GPR 91 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 92 93 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 94 CCIfType<[v64i1], CCPromoteToType<i64>>, 95 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 96 CCAssignToReg<RC.GPR_64>>>, 97 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 98 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 99 100 // float, double, float128 --> XMM 101 // In the case of SSE disabled --> save to stack 102 CCIfType<[f32, f64, f128], 103 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 104 105 // long double --> FP 106 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>, 107 108 // __m128, __m128i, __m128d --> XMM 109 // In the case of SSE disabled --> save to stack 110 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 111 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 112 113 // __m256, __m256i, __m256d --> YMM 114 // In the case of SSE disabled --> save to stack 115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 116 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 117 118 // __m512, __m512i, __m512d --> ZMM 119 // In the case of SSE disabled --> save to stack 120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 121 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>, 122 123 // If no register was found -> assign to stack 124 125 // In 64 bit, assign 64/32 bit values to 8 byte stack 126 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 127 CCAssignToStack<8, 8>>>, 128 129 // In 32 bit, assign 64/32 bit values to 8/4 byte stack 130 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 131 CCIfType<[i64, f64], CCAssignToStack<8, 4>>, 132 133 // MMX type gets 8 byte slot in stack , while alignment depends on target 134 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, 135 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 136 137 // float 128 get stack slots whose size and alignment depends 138 // on the subtarget. 139 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 140 141 // Vectors get 16-byte stack slots that are 16-byte aligned. 142 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 143 CCAssignToStack<16, 16>>, 144 145 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 147 CCAssignToStack<32, 32>>, 148 149 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 151 CCAssignToStack<64, 64>> 152]>; 153 154def RetCC_#NAME : CallingConv<[ 155 // Promote i1, v1i1, v8i1 arguments to i8. 156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>, 157 158 // Promote v16i1 arguments to i16. 159 CCIfType<[v16i1], CCPromoteToType<i16>>, 160 161 // Promote v32i1 arguments to i32. 162 CCIfType<[v32i1], CCPromoteToType<i32>>, 163 164 // bool, char, int, enum, long, pointer --> GPR 165 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>, 166 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>, 167 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 168 169 // long long, __int64 --> GPR 170 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 171 172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 173 CCIfType<[v64i1], CCPromoteToType<i64>>, 174 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 175 CCAssignToReg<RC.GPR_64>>>, 176 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 177 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 178 179 // long double --> FP 180 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>, 181 182 // float, double, float128 --> XMM 183 CCIfType<[f32, f64, f128], 184 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 185 186 // __m128, __m128i, __m128d --> XMM 187 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 188 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 189 190 // __m256, __m256i, __m256d --> YMM 191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 192 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 193 194 // __m512, __m512i, __m512d --> ZMM 195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 196 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>> 197]>; 198} 199 200//===----------------------------------------------------------------------===// 201// Return Value Calling Conventions 202//===----------------------------------------------------------------------===// 203 204// Return-value conventions common to all X86 CC's. 205def RetCC_X86Common : CallingConv<[ 206 // Scalar values are returned in AX first, then DX. For i8, the ABI 207 // requires the values to be in AL and AH, however this code uses AL and DL 208 // instead. This is because using AH for the second register conflicts with 209 // the way LLVM does multiple return values -- a return of {i16,i8} would end 210 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 211 // for functions that return two i8 values are currently expected to pack the 212 // values into an i16 (which uses AX, and thus AL:AH). 213 // 214 // For code that doesn't care about the ABI, we allow returning more than two 215 // integer values in registers. 216 CCIfType<[v1i1], CCPromoteToType<i8>>, 217 CCIfType<[i1], CCPromoteToType<i8>>, 218 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 219 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 220 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 222 223 // Boolean vectors of AVX-512 are returned in SIMD registers. 224 // The call from AVX to AVX-512 function should work, 225 // since the boolean types in AVX/AVX2 are promoted by default. 226 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 227 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 228 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 229 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 230 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 231 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 232 233 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 234 // can only be used by ABI non-compliant code. If the target doesn't have XMM 235 // registers, it won't have vector types. 236 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 237 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 238 239 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 240 // can only be used by ABI non-compliant code. This vector type is only 241 // supported while using the AVX target feature. 242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 243 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 244 245 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 246 // can only be used by ABI non-compliant code. This vector type is only 247 // supported while using the AVX-512 target feature. 248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 249 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 250 251 // MMX vector types are always returned in MM0. If the target doesn't have 252 // MM0, it doesn't support these vector types. 253 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 254 255 // Long double types are always returned in FP0 (even with SSE), 256 // except on Win64. 257 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> 258]>; 259 260// X86-32 C return-value convention. 261def RetCC_X86_32_C : CallingConv<[ 262 // The X86-32 calling convention returns FP values in FP0, unless marked 263 // with "inreg" (used here to distinguish one kind of reg from another, 264 // weirdly; this is really the sse-regparm calling convention) in which 265 // case they use XMM0, otherwise it is the same as the common X86 calling 266 // conv. 267 CCIfInReg<CCIfSubtarget<"hasSSE2()", 268 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 269 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>, 270 CCDelegateTo<RetCC_X86Common> 271]>; 272 273// X86-32 FastCC return-value convention. 274def RetCC_X86_32_Fast : CallingConv<[ 275 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 276 // SSE2. 277 // This can happen when a float, 2 x float, or 3 x float vector is split by 278 // target lowering, and is returned in 1-3 sse regs. 279 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 280 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 281 282 // For integers, ECX can be used as an extra return register 283 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 284 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 285 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 286 287 // Otherwise, it is the same as the common X86 calling convention. 288 CCDelegateTo<RetCC_X86Common> 289]>; 290 291// Intel_OCL_BI return-value convention. 292def RetCC_Intel_OCL_BI : CallingConv<[ 293 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 294 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 295 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 296 297 // 256-bit FP vectors 298 // No more than 4 registers 299 CCIfType<[v8f32, v4f64, v8i32, v4i64], 300 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 301 302 // 512-bit FP vectors 303 CCIfType<[v16f32, v8f64, v16i32, v8i64], 304 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 305 306 // i32, i64 in the standard way 307 CCDelegateTo<RetCC_X86Common> 308]>; 309 310// X86-32 HiPE return-value convention. 311def RetCC_X86_32_HiPE : CallingConv<[ 312 // Promote all types to i32 313 CCIfType<[i8, i16], CCPromoteToType<i32>>, 314 315 // Return: HP, P, VAL1, VAL2 316 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 317]>; 318 319// X86-32 Vectorcall return-value convention. 320def RetCC_X86_32_VectorCall : CallingConv<[ 321 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. 322 CCIfType<[f32, f64, f128], 323 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 324 325 // Return integers in the standard way. 326 CCDelegateTo<RetCC_X86Common> 327]>; 328 329// X86-64 C return-value convention. 330def RetCC_X86_64_C : CallingConv<[ 331 // The X86-64 calling convention always returns FP values in XMM0. 332 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 333 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 334 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 335 336 // MMX vector types are always returned in XMM0. 337 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 338 339 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 340 341 CCDelegateTo<RetCC_X86Common> 342]>; 343 344// X86-Win64 C return-value convention. 345def RetCC_X86_Win64_C : CallingConv<[ 346 // The X86-Win64 calling convention always returns __m64 values in RAX. 347 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 348 349 // GCC returns FP values in RAX on Win64. 350 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 351 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 352 353 // Otherwise, everything is the same as 'normal' X86-64 C CC. 354 CCDelegateTo<RetCC_X86_64_C> 355]>; 356 357// X86-64 vectorcall return-value convention. 358def RetCC_X86_64_Vectorcall : CallingConv<[ 359 // Vectorcall calling convention always returns FP values in XMMs. 360 CCIfType<[f32, f64, f128], 361 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 362 363 // Otherwise, everything is the same as Windows X86-64 C CC. 364 CCDelegateTo<RetCC_X86_Win64_C> 365]>; 366 367// X86-64 HiPE return-value convention. 368def RetCC_X86_64_HiPE : CallingConv<[ 369 // Promote all types to i64 370 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 371 372 // Return: HP, P, VAL1, VAL2 373 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 374]>; 375 376// X86-64 WebKit_JS return-value convention. 377def RetCC_X86_64_WebKit_JS : CallingConv<[ 378 // Promote all types to i64 379 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 380 381 // Return: RAX 382 CCIfType<[i64], CCAssignToReg<[RAX]>> 383]>; 384 385def RetCC_X86_64_Swift : CallingConv<[ 386 387 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 388 389 // For integers, ECX, R8D can be used as extra return registers. 390 CCIfType<[v1i1], CCPromoteToType<i8>>, 391 CCIfType<[i1], CCPromoteToType<i8>>, 392 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, 393 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, 394 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 395 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 396 397 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. 398 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 399 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 400 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 401 402 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. 403 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 404 CCDelegateTo<RetCC_X86Common> 405]>; 406 407// X86-64 AnyReg return-value convention. No explicit register is specified for 408// the return-value. The register allocator is allowed and expected to choose 409// any free register. 410// 411// This calling convention is currently only supported by the stackmap and 412// patchpoint intrinsics. All other uses will result in an assert on Debug 413// builds. On Release builds we fallback to the X86 C calling convention. 414def RetCC_X86_64_AnyReg : CallingConv<[ 415 CCCustom<"CC_X86_AnyReg_Error"> 416]>; 417 418// X86-64 HHVM return-value convention. 419def RetCC_X86_64_HHVM: CallingConv<[ 420 // Promote all types to i64 421 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 422 423 // Return: could return in any GP register save RSP and R12. 424 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, 425 RAX, R10, R11, R13, R14, R15]>> 426]>; 427 428 429defm X86_32_RegCall : 430 X86_RegCall_base<RC_X86_32_RegCall>; 431defm X86_Win64_RegCall : 432 X86_RegCall_base<RC_X86_64_RegCall_Win>; 433defm X86_SysV64_RegCall : 434 X86_RegCall_base<RC_X86_64_RegCall_SysV>; 435 436// This is the root return-value convention for the X86-32 backend. 437def RetCC_X86_32 : CallingConv<[ 438 // If FastCC, use RetCC_X86_32_Fast. 439 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 440 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>, 441 // CFGuard_Check never returns a value so does not need a RetCC. 442 // If HiPE, use RetCC_X86_32_HiPE. 443 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 444 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 445 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>, 446 447 // Otherwise, use RetCC_X86_32_C. 448 CCDelegateTo<RetCC_X86_32_C> 449]>; 450 451// This is the root return-value convention for the X86-64 backend. 452def RetCC_X86_64 : CallingConv<[ 453 // HiPE uses RetCC_X86_64_HiPE 454 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 455 456 // Handle JavaScript calls. 457 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>, 458 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 459 460 // Handle Swift calls. 461 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>, 462 463 // Handle explicit CC selection 464 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 465 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 466 467 // Handle Vectorcall CC 468 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>, 469 470 // Handle HHVM calls. 471 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>, 472 473 CCIfCC<"CallingConv::X86_RegCall", 474 CCIfSubtarget<"isTargetWin64()", 475 CCDelegateTo<RetCC_X86_Win64_RegCall>>>, 476 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>, 477 478 // Mingw64 and native Win64 use Win64 CC 479 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 480 481 // Otherwise, drop to normal X86-64 CC 482 CCDelegateTo<RetCC_X86_64_C> 483]>; 484 485// This is the return-value convention used for the entire X86 backend. 486let Entry = 1 in 487def RetCC_X86 : CallingConv<[ 488 489 // Check if this is the Intel OpenCL built-ins calling convention 490 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 491 492 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 493 CCDelegateTo<RetCC_X86_32> 494]>; 495 496//===----------------------------------------------------------------------===// 497// X86-64 Argument Calling Conventions 498//===----------------------------------------------------------------------===// 499 500def CC_X86_64_C : CallingConv<[ 501 // Handles byval parameters. 502 CCIfByVal<CCPassByVal<8, 8>>, 503 504 // Promote i1/i8/i16/v1i1 arguments to i32. 505 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 506 507 // The 'nest' parameter, if any, is passed in R10. 508 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 509 CCIfNest<CCAssignToReg<[R10]>>, 510 511 // Pass SwiftSelf in a callee saved register. 512 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 513 514 // A SwiftError is passed in R12. 515 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 516 517 // For Swift Calling Convention, pass sret in %rax. 518 CCIfCC<"CallingConv::Swift", 519 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 520 521 // The first 6 integer arguments are passed in integer registers. 522 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 523 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 524 525 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 526 CCIfType<[x86mmx], 527 CCIfSubtarget<"isTargetDarwin()", 528 CCIfSubtarget<"hasSSE2()", 529 CCPromoteToType<v2i64>>>>, 530 531 // Boolean vectors of AVX-512 are passed in SIMD registers. 532 // The call from AVX to AVX-512 function should work, 533 // since the boolean types in AVX/AVX2 are promoted by default. 534 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 535 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 536 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 537 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 538 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 539 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 540 541 // The first 8 FP/Vector arguments are passed in XMM registers. 542 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 543 CCIfSubtarget<"hasSSE1()", 544 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 545 546 // The first 8 256-bit vector arguments are passed in YMM registers, unless 547 // this is a vararg function. 548 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 549 // fixed arguments to vararg functions are supposed to be passed in 550 // registers. Actually modeling that would be a lot of work, though. 551 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 552 CCIfSubtarget<"hasAVX()", 553 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 554 YMM4, YMM5, YMM6, YMM7]>>>>, 555 556 // The first 8 512-bit vector arguments are passed in ZMM registers. 557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 558 CCIfSubtarget<"hasAVX512()", 559 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 560 561 // Integer/FP values get stored in stack slots that are 8 bytes in size and 562 // 8-byte aligned if there are no more registers to hold them. 563 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, 564 565 // Long doubles get stack slots whose size and alignment depends on the 566 // subtarget. 567 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 568 569 // Vectors get 16-byte stack slots that are 16-byte aligned. 570 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 571 572 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 573 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 574 CCAssignToStack<32, 32>>, 575 576 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 578 CCAssignToStack<64, 64>> 579]>; 580 581// Calling convention for X86-64 HHVM. 582def CC_X86_64_HHVM : CallingConv<[ 583 // Use all/any GP registers for args, except RSP. 584 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15, 585 RDI, RSI, RDX, RCX, R8, R9, 586 RAX, R10, R11, R13, R14]>> 587]>; 588 589// Calling convention for helper functions in HHVM. 590def CC_X86_64_HHVM_C : CallingConv<[ 591 // Pass the first argument in RBP. 592 CCIfType<[i64], CCAssignToReg<[RBP]>>, 593 594 // Otherwise it's the same as the regular C calling convention. 595 CCDelegateTo<CC_X86_64_C> 596]>; 597 598// Calling convention used on Win64 599def CC_X86_Win64_C : CallingConv<[ 600 // FIXME: Handle varargs. 601 602 // Byval aggregates are passed by pointer 603 CCIfByVal<CCPassIndirect<i64>>, 604 605 // Promote i1/v1i1 arguments to i8. 606 CCIfType<[i1, v1i1], CCPromoteToType<i8>>, 607 608 // The 'nest' parameter, if any, is passed in R10. 609 CCIfNest<CCAssignToReg<[R10]>>, 610 611 // A SwiftError is passed in R12. 612 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 613 614 // The 'CFGuardTarget' parameter, if any, is passed in RAX. 615 CCIfCFGuardTarget<CCAssignToReg<[RAX]>>, 616 617 // 128 bit vectors are passed by pointer 618 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>, 619 620 // 256 bit vectors are passed by pointer 621 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>, 622 623 // 512 bit vectors are passed by pointer 624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 625 626 // Long doubles are passed by pointer 627 CCIfType<[f80], CCPassIndirect<i64>>, 628 629 // The first 4 MMX vector arguments are passed in GPRs. 630 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 631 632 // If SSE was disabled, pass FP values smaller than 64-bits as integers in 633 // GPRs or on the stack. 634 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 635 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 636 637 // The first 4 FP/Vector arguments are passed in XMM registers. 638 CCIfType<[f32, f64], 639 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 640 [RCX , RDX , R8 , R9 ]>>, 641 642 // The first 4 integer arguments are passed in integer registers. 643 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], 644 [XMM0, XMM1, XMM2, XMM3]>>, 645 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], 646 [XMM0, XMM1, XMM2, XMM3]>>, 647 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 648 [XMM0, XMM1, XMM2, XMM3]>>, 649 650 // Do not pass the sret argument in RCX, the Win64 thiscall calling 651 // convention requires "this" to be passed in RCX. 652 CCIfCC<"CallingConv::X86_ThisCall", 653 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 654 [XMM1, XMM2, XMM3]>>>>, 655 656 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 657 [XMM0, XMM1, XMM2, XMM3]>>, 658 659 // Integer/FP values get stored in stack slots that are 8 bytes in size and 660 // 8-byte aligned if there are no more registers to hold them. 661 CCIfType<[i8, i16, i32, i64, f32, f64], CCAssignToStack<8, 8>> 662]>; 663 664def CC_X86_Win64_VectorCall : CallingConv<[ 665 CCCustom<"CC_X86_64_VectorCall">, 666 667 // Delegate to fastcall to handle integer types. 668 CCDelegateTo<CC_X86_Win64_C> 669]>; 670 671 672def CC_X86_64_GHC : CallingConv<[ 673 // Promote i8/i16/i32 arguments to i64. 674 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 675 676 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 677 CCIfType<[i64], 678 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 679 680 // Pass in STG registers: F1, F2, F3, F4, D1, D2 681 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 682 CCIfSubtarget<"hasSSE1()", 683 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, 684 // AVX 685 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 686 CCIfSubtarget<"hasAVX()", 687 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, 688 // AVX-512 689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 690 CCIfSubtarget<"hasAVX512()", 691 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> 692]>; 693 694def CC_X86_64_HiPE : CallingConv<[ 695 // Promote i8/i16/i32 arguments to i64. 696 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 697 698 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 699 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 700 701 // Integer/FP values get stored in stack slots that are 8 bytes in size and 702 // 8-byte aligned if there are no more registers to hold them. 703 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 704]>; 705 706def CC_X86_64_WebKit_JS : CallingConv<[ 707 // Promote i8/i16 arguments to i32. 708 CCIfType<[i8, i16], CCPromoteToType<i32>>, 709 710 // Only the first integer argument is passed in register. 711 CCIfType<[i32], CCAssignToReg<[EAX]>>, 712 CCIfType<[i64], CCAssignToReg<[RAX]>>, 713 714 // The remaining integer arguments are passed on the stack. 32bit integer and 715 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. 716 // 64bit integer and floating-point arguments are aligned to 8 byte and stored 717 // in 8 byte stack slots. 718 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 719 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 720]>; 721 722// No explicit register is specified for the AnyReg calling convention. The 723// register allocator may assign the arguments to any free register. 724// 725// This calling convention is currently only supported by the stackmap and 726// patchpoint intrinsics. All other uses will result in an assert on Debug 727// builds. On Release builds we fallback to the X86 C calling convention. 728def CC_X86_64_AnyReg : CallingConv<[ 729 CCCustom<"CC_X86_AnyReg_Error"> 730]>; 731 732//===----------------------------------------------------------------------===// 733// X86 C Calling Convention 734//===----------------------------------------------------------------------===// 735 736/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 737/// values are spilled on the stack. 738def CC_X86_32_Vector_Common : CallingConv<[ 739 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 740 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 741 742 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 743 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 744 CCAssignToStack<32, 32>>, 745 746 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 747 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 748 CCAssignToStack<64, 64>> 749]>; 750 751// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 752// vector registers 753def CC_X86_32_Vector_Standard : CallingConv<[ 754 // SSE vector arguments are passed in XMM registers. 755 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 756 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 757 758 // AVX 256-bit vector arguments are passed in YMM registers. 759 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 760 CCIfSubtarget<"hasAVX()", 761 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 762 763 // AVX 512-bit vector arguments are passed in ZMM registers. 764 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 765 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 766 767 CCDelegateTo<CC_X86_32_Vector_Common> 768]>; 769 770// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 771// vector registers. 772def CC_X86_32_Vector_Darwin : CallingConv<[ 773 // SSE vector arguments are passed in XMM registers. 774 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 775 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 776 777 // AVX 256-bit vector arguments are passed in YMM registers. 778 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 779 CCIfSubtarget<"hasAVX()", 780 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 781 782 // AVX 512-bit vector arguments are passed in ZMM registers. 783 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 784 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 785 786 CCDelegateTo<CC_X86_32_Vector_Common> 787]>; 788 789/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 790/// values are spilled on the stack. 791def CC_X86_32_Common : CallingConv<[ 792 // Handles byval parameters. 793 CCIfByVal<CCPassByVal<4, 4>>, 794 795 // The first 3 float or double arguments, if marked 'inreg' and if the call 796 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 797 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 798 CCIfSubtarget<"hasSSE2()", 799 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 800 801 // The first 3 __m64 vector arguments are passed in mmx registers if the 802 // call is not a vararg call. 803 CCIfNotVarArg<CCIfType<[x86mmx], 804 CCAssignToReg<[MM0, MM1, MM2]>>>, 805 806 // Integer/Float values get stored in stack slots that are 4 bytes in 807 // size and 4-byte aligned. 808 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 809 810 // Doubles get 8-byte slots that are 4-byte aligned. 811 CCIfType<[f64], CCAssignToStack<8, 4>>, 812 813 // Long doubles get slots whose size depends on the subtarget. 814 CCIfType<[f80], CCAssignToStack<0, 4>>, 815 816 // Boolean vectors of AVX-512 are passed in SIMD registers. 817 // The call from AVX to AVX-512 function should work, 818 // since the boolean types in AVX/AVX2 are promoted by default. 819 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 820 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 821 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 822 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 823 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 824 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 825 826 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 827 // passed in the parameter area. 828 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 829 830 // Darwin passes vectors in a form that differs from the i386 psABI 831 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 832 833 // Otherwise, drop to 'normal' X86-32 CC 834 CCDelegateTo<CC_X86_32_Vector_Standard> 835]>; 836 837def CC_X86_32_C : CallingConv<[ 838 // Promote i1/i8/i16/v1i1 arguments to i32. 839 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 840 841 // The 'nest' parameter, if any, is passed in ECX. 842 CCIfNest<CCAssignToReg<[ECX]>>, 843 844 // The first 3 integer arguments, if marked 'inreg' and if the call is not 845 // a vararg call, are passed in integer registers. 846 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 847 848 // Otherwise, same as everything else. 849 CCDelegateTo<CC_X86_32_Common> 850]>; 851 852def CC_X86_32_MCU : CallingConv<[ 853 // Handles byval parameters. Note that, like FastCC, we can't rely on 854 // the delegation to CC_X86_32_Common because that happens after code that 855 // puts arguments in registers. 856 CCIfByVal<CCPassByVal<4, 4>>, 857 858 // Promote i1/i8/i16/v1i1 arguments to i32. 859 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 860 861 // If the call is not a vararg call, some arguments may be passed 862 // in integer registers. 863 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>, 864 865 // Otherwise, same as everything else. 866 CCDelegateTo<CC_X86_32_Common> 867]>; 868 869def CC_X86_32_FastCall : CallingConv<[ 870 // Promote i1 to i8. 871 CCIfType<[i1], CCPromoteToType<i8>>, 872 873 // The 'nest' parameter, if any, is passed in EAX. 874 CCIfNest<CCAssignToReg<[EAX]>>, 875 876 // The first 2 integer arguments are passed in ECX/EDX 877 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, 878 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, 879 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 880 881 // Otherwise, same as everything else. 882 CCDelegateTo<CC_X86_32_Common> 883]>; 884 885def CC_X86_Win32_VectorCall : CallingConv<[ 886 // Pass floating point in XMMs 887 CCCustom<"CC_X86_32_VectorCall">, 888 889 // Delegate to fastcall to handle integer types. 890 CCDelegateTo<CC_X86_32_FastCall> 891]>; 892 893def CC_X86_32_ThisCall_Common : CallingConv<[ 894 // The first integer argument is passed in ECX 895 CCIfType<[i32], CCAssignToReg<[ECX]>>, 896 897 // Otherwise, same as everything else. 898 CCDelegateTo<CC_X86_32_Common> 899]>; 900 901def CC_X86_32_ThisCall_Mingw : CallingConv<[ 902 // Promote i1/i8/i16/v1i1 arguments to i32. 903 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 904 905 CCDelegateTo<CC_X86_32_ThisCall_Common> 906]>; 907 908def CC_X86_32_ThisCall_Win : CallingConv<[ 909 // Promote i1/i8/i16/v1i1 arguments to i32. 910 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 911 912 // Pass sret arguments indirectly through stack. 913 CCIfSRet<CCAssignToStack<4, 4>>, 914 915 CCDelegateTo<CC_X86_32_ThisCall_Common> 916]>; 917 918def CC_X86_32_ThisCall : CallingConv<[ 919 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 920 CCDelegateTo<CC_X86_32_ThisCall_Win> 921]>; 922 923def CC_X86_32_FastCC : CallingConv<[ 924 // Handles byval parameters. Note that we can't rely on the delegation 925 // to CC_X86_32_Common for this because that happens after code that 926 // puts arguments in registers. 927 CCIfByVal<CCPassByVal<4, 4>>, 928 929 // Promote i1/i8/i16/v1i1 arguments to i32. 930 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 931 932 // The 'nest' parameter, if any, is passed in EAX. 933 CCIfNest<CCAssignToReg<[EAX]>>, 934 935 // The first 2 integer arguments are passed in ECX/EDX 936 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 937 938 // The first 3 float or double arguments, if the call is not a vararg 939 // call and if SSE2 is available, are passed in SSE registers. 940 CCIfNotVarArg<CCIfType<[f32,f64], 941 CCIfSubtarget<"hasSSE2()", 942 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 943 944 // Doubles get 8-byte slots that are 8-byte aligned. 945 CCIfType<[f64], CCAssignToStack<8, 8>>, 946 947 // Otherwise, same as everything else. 948 CCDelegateTo<CC_X86_32_Common> 949]>; 950 951def CC_X86_Win32_CFGuard_Check : CallingConv<[ 952 // The CFGuard check call takes exactly one integer argument 953 // (i.e. the target function address), which is passed in ECX. 954 CCIfType<[i32], CCAssignToReg<[ECX]>> 955]>; 956 957def CC_X86_32_GHC : CallingConv<[ 958 // Promote i8/i16 arguments to i32. 959 CCIfType<[i8, i16], CCPromoteToType<i32>>, 960 961 // Pass in STG registers: Base, Sp, Hp, R1 962 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 963]>; 964 965def CC_X86_32_HiPE : CallingConv<[ 966 // Promote i8/i16 arguments to i32. 967 CCIfType<[i8, i16], CCPromoteToType<i32>>, 968 969 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 970 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 971 972 // Integer/Float values get stored in stack slots that are 4 bytes in 973 // size and 4-byte aligned. 974 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 975]>; 976 977// X86-64 Intel OpenCL built-ins calling convention. 978def CC_Intel_OCL_BI : CallingConv<[ 979 980 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 981 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 982 983 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 984 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 985 986 CCIfType<[i32], CCAssignToStack<4, 4>>, 987 988 // The SSE vector arguments are passed in XMM registers. 989 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 990 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 991 992 // The 256-bit vector arguments are passed in YMM registers. 993 CCIfType<[v8f32, v4f64, v8i32, v4i64], 994 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 995 996 // The 512-bit vector arguments are passed in ZMM registers. 997 CCIfType<[v16f32, v8f64, v16i32, v8i64], 998 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 999 1000 // Pass masks in mask registers 1001 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 1002 1003 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1004 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 1005 CCDelegateTo<CC_X86_32_C> 1006]>; 1007 1008//===----------------------------------------------------------------------===// 1009// X86 Root Argument Calling Conventions 1010//===----------------------------------------------------------------------===// 1011 1012// This is the root argument convention for the X86-32 backend. 1013def CC_X86_32 : CallingConv<[ 1014 // X86_INTR calling convention is valid in MCU target and should override the 1015 // MCU calling convention. Thus, this should be checked before isTargetMCU(). 1016 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1017 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>, 1018 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 1019 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>, 1020 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 1021 CCIfCC<"CallingConv::CFGuard_Check", CCDelegateTo<CC_X86_Win32_CFGuard_Check>>, 1022 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 1023 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>, 1024 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 1025 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 1026 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>, 1027 1028 // Otherwise, drop to normal X86-32 CC 1029 CCDelegateTo<CC_X86_32_C> 1030]>; 1031 1032// This is the root argument convention for the X86-64 backend. 1033def CC_X86_64 : CallingConv<[ 1034 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 1035 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 1036 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>, 1037 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 1038 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>, 1039 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 1040 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 1041 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>, 1042 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>, 1043 CCIfCC<"CallingConv::X86_RegCall", 1044 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>, 1045 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>, 1046 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1047 1048 // Mingw64 and native Win64 use Win64 CC 1049 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1050 1051 // Otherwise, drop to normal X86-64 CC 1052 CCDelegateTo<CC_X86_64_C> 1053]>; 1054 1055// This is the argument convention used for the entire X86 backend. 1056let Entry = 1 in 1057def CC_X86 : CallingConv<[ 1058 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 1059 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 1060 CCDelegateTo<CC_X86_32> 1061]>; 1062 1063//===----------------------------------------------------------------------===// 1064// Callee-saved Registers. 1065//===----------------------------------------------------------------------===// 1066 1067def CSR_NoRegs : CalleeSavedRegs<(add)>; 1068 1069def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1070def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 1071 1072def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; 1073 1074def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 1075def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 1076 1077def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; 1078 1079def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, 1080 (sequence "XMM%u", 6, 15))>; 1081 1082def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; 1083 1084// The function used by Darwin to obtain the address of a thread-local variable 1085// uses rdi to pass a single parameter and rax for the return value. All other 1086// GPRs are preserved. 1087def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 1088 R8, R9, R10, R11)>; 1089 1090// CSRs that are handled by prologue, epilogue. 1091def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; 1092 1093// CSRs that are handled explicitly via copies. 1094def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; 1095 1096// All GPRs - except r11 1097def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 1098 R8, R9, R10, RSP)>; 1099 1100// All registers - except r11 1101def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1102 (sequence "XMM%u", 0, 15))>; 1103def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1104 (sequence "YMM%u", 0, 15))>; 1105 1106def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 1107 R11, R12, R13, R14, R15, RBP, 1108 (sequence "XMM%u", 0, 15))>; 1109 1110def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 1111 EDI)>; 1112def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 1113 (sequence "XMM%u", 0, 7))>; 1114def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, 1115 (sequence "YMM%u", 0, 7))>; 1116def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, 1117 (sequence "ZMM%u", 0, 7), 1118 (sequence "K%u", 0, 7))>; 1119 1120def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; 1121def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, 1122 R10, R11, R12, R13, R14, R15, RBP)>; 1123def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1124 (sequence "YMM%u", 0, 15)), 1125 (sequence "XMM%u", 0, 15))>; 1126def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1127 (sequence "ZMM%u", 0, 31), 1128 (sequence "K%u", 0, 7)), 1129 (sequence "XMM%u", 0, 15))>; 1130 1131// Standard C + YMM6-15 1132def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 1133 R13, R14, R15, 1134 (sequence "YMM%u", 6, 15))>; 1135 1136def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 1137 R12, R13, R14, R15, 1138 (sequence "ZMM%u", 6, 21), 1139 K4, K5, K6, K7)>; 1140//Standard C + XMM 8-15 1141def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 1142 (sequence "XMM%u", 8, 15))>; 1143 1144//Standard C + YMM 8-15 1145def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 1146 (sequence "YMM%u", 8, 15))>; 1147 1148def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15, 1149 (sequence "ZMM%u", 16, 31), 1150 K4, K5, K6, K7)>; 1151 1152// Only R12 is preserved for PHP calls in HHVM. 1153def CSR_64_HHVM : CalleeSavedRegs<(add R12)>; 1154 1155// Register calling convention preserves few GPR and XMM8-15 1156def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>; 1157def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 1158 (sequence "XMM%u", 4, 7))>; 1159def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, ECX)>; 1160def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>; 1161def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, 1162 (sequence "R%u", 10, 15))>; 1163def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1164 (sequence "XMM%u", 8, 15))>; 1165def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, 1166 (sequence "R%u", 12, 15))>; 1167def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1168 (sequence "XMM%u", 8, 15))>; 1169 1170