1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the X86-32 and X86-64 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 17 "(State.getMachineFunction().getSubtarget()).", F), 18 A>; 19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const X86Subtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", F), 24 A>; 25 26/// CCIfRegCallv4 - Match if RegCall ABIv4 is respected. 27class CCIfRegCallv4<CCAction A> 28 : CCIf<"State.getMachineFunction().getFunction().getParent()->getModuleFlag(\"RegCallv4\")!=nullptr", 29 A>; 30 31/// CCIfIsVarArgOnWin - Match if isVarArg on Windows 32bits. 32class CCIfIsVarArgOnWin<CCAction A> 33 : CCIf<"State.isVarArg() && " 34 "State.getMachineFunction().getSubtarget().getTargetTriple()." 35 "isWindowsMSVCEnvironment()", 36 A>; 37 38// Register classes for RegCall 39class RC_X86_RegCall { 40 list<Register> GPR_8 = []; 41 list<Register> GPR_16 = []; 42 list<Register> GPR_32 = []; 43 list<Register> GPR_64 = []; 44 list<Register> FP_CALL = [FP0]; 45 list<Register> FP_RET = [FP0, FP1]; 46 list<Register> XMM = []; 47 list<Register> YMM = []; 48 list<Register> ZMM = []; 49} 50 51// RegCall register classes for 32 bits 52def RC_X86_32_RegCall : RC_X86_RegCall { 53 let GPR_8 = [AL, CL, DL, DIL, SIL]; 54 let GPR_16 = [AX, CX, DX, DI, SI]; 55 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 56 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 57 ///< \todo Fix AssignToReg to enable empty lists 58 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 59 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 60 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 61} 62 63// RegCall register classes for 32 bits if it respect regcall ABI v.4 64// Change in __regcall ABI v.4: don't use EAX as a spare register is 65// needed to code virtual call thunk, 66def RC_X86_32_RegCallv4_Win : RC_X86_RegCall { 67 let GPR_8 = [CL, DL, DIL, SIL]; 68 let GPR_16 = [CX, DX, DI, SI]; 69 let GPR_32 = [ECX, EDX, EDI, ESI]; 70 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 71 ///< \todo Fix AssignToReg to enable empty lists 72 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 73 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 74 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 75} 76 77class RC_X86_64_RegCall : RC_X86_RegCall { 78 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 79 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; 80 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, 81 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; 82 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, 83 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; 84} 85 86def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { 87 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; 88 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; 89 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; 91} 92 93// On Windows 64 we don't want to use R13 - it is reserved for 94// largely aligned stack. 95// Change in __regcall ABI v.4: additionally don't use R10 as a 96// a spare register is needed to code virtual call thunk. 97// 98def RC_X86_64_RegCallv4_Win : RC_X86_64_RegCall { 99 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R11B, R12B, R14B, R15B]; 100 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R11W, R12W, R14W, R15W]; 101 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R11D, R12D, R14D, R15D]; 102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15]; 103} 104 105def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { 106 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; 107 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; 108 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; 110} 111 112// X86-64 Intel regcall calling convention. 113multiclass X86_RegCall_base<RC_X86_RegCall RC> { 114def CC_#NAME : CallingConv<[ 115 // Handles byval parameters. 116 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>, 117 CCIfByVal<CCPassByVal<4, 4>>, 118 119 // Promote i1/i8/i16/v1i1 arguments to i32. 120 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 121 122 // Promote v8i1/v16i1/v32i1 arguments to i32. 123 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>, 124 125 // bool, char, int, enum, long, pointer --> GPR 126 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 127 128 // long long, __int64 --> GPR 129 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 130 131 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 132 CCIfType<[v64i1], CCPromoteToType<i64>>, 133 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 134 CCAssignToReg<RC.GPR_64>>>, 135 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 136 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 137 138 // float, double, float128 --> XMM 139 // In the case of SSE disabled --> save to stack 140 CCIfType<[f32, f64, f128], 141 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 142 143 // long double --> FP 144 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>, 145 146 // __m128, __m128i, __m128d --> XMM 147 // In the case of SSE disabled --> save to stack 148 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 149 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 150 151 // __m256, __m256i, __m256d --> YMM 152 // In the case of SSE disabled --> save to stack 153 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 154 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 155 156 // __m512, __m512i, __m512d --> ZMM 157 // In the case of SSE disabled --> save to stack 158 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 159 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>, 160 161 // If no register was found -> assign to stack 162 163 // In 64 bit, assign 64/32 bit values to 8 byte stack 164 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 165 CCAssignToStack<8, 8>>>, 166 167 // In 32 bit, assign 64/32 bit values to 8/4 byte stack 168 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 169 CCIfType<[i64, f64], CCAssignToStack<8, 4>>, 170 171 // MMX type gets 8 byte slot in stack , while alignment depends on target 172 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, 173 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 174 175 // float 128 get stack slots whose size and alignment depends 176 // on the subtarget. 177 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 178 179 // Vectors get 16-byte stack slots that are 16-byte aligned. 180 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 181 CCAssignToStack<16, 16>>, 182 183 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 184 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 185 CCAssignToStack<32, 32>>, 186 187 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 188 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 189 CCAssignToStack<64, 64>> 190]>; 191 192def RetCC_#NAME : CallingConv<[ 193 // Promote i1, v1i1, v8i1 arguments to i8. 194 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>, 195 196 // Promote v16i1 arguments to i16. 197 CCIfType<[v16i1], CCPromoteToType<i16>>, 198 199 // Promote v32i1 arguments to i32. 200 CCIfType<[v32i1], CCPromoteToType<i32>>, 201 202 // bool, char, int, enum, long, pointer --> GPR 203 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>, 204 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>, 205 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 206 207 // long long, __int64 --> GPR 208 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 209 210 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 211 CCIfType<[v64i1], CCPromoteToType<i64>>, 212 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 213 CCAssignToReg<RC.GPR_64>>>, 214 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 215 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 216 217 // long double --> FP 218 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>, 219 220 // float, double, float128 --> XMM 221 CCIfType<[f32, f64, f128], 222 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 223 224 // __m128, __m128i, __m128d --> XMM 225 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 226 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 227 228 // __m256, __m256i, __m256d --> YMM 229 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 230 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 231 232 // __m512, __m512i, __m512d --> ZMM 233 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 234 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>> 235]>; 236} 237 238//===----------------------------------------------------------------------===// 239// Return Value Calling Conventions 240//===----------------------------------------------------------------------===// 241 242// Return-value conventions common to all X86 CC's. 243def RetCC_X86Common : CallingConv<[ 244 // Scalar values are returned in AX first, then DX. For i8, the ABI 245 // requires the values to be in AL and AH, however this code uses AL and DL 246 // instead. This is because using AH for the second register conflicts with 247 // the way LLVM does multiple return values -- a return of {i16,i8} would end 248 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 249 // for functions that return two i8 values are currently expected to pack the 250 // values into an i16 (which uses AX, and thus AL:AH). 251 // 252 // For code that doesn't care about the ABI, we allow returning more than two 253 // integer values in registers. 254 CCIfType<[v1i1], CCPromoteToType<i8>>, 255 CCIfType<[i1], CCPromoteToType<i8>>, 256 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 257 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 258 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 259 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 260 261 // Boolean vectors of AVX-512 are returned in SIMD registers. 262 // The call from AVX to AVX-512 function should work, 263 // since the boolean types in AVX/AVX2 are promoted by default. 264 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 265 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 266 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 267 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 268 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 269 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 270 271 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 272 // can only be used by ABI non-compliant code. If the target doesn't have XMM 273 // registers, it won't have vector types. 274 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 275 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 276 277 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 278 // can only be used by ABI non-compliant code. This vector type is only 279 // supported while using the AVX target feature. 280 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 281 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 282 283 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 284 // can only be used by ABI non-compliant code. This vector type is only 285 // supported while using the AVX-512 target feature. 286 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 287 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 288 289 // MMX vector types are always returned in MM0. If the target doesn't have 290 // MM0, it doesn't support these vector types. 291 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 292 293 // Long double types are always returned in FP0 (even with SSE), 294 // except on Win64. 295 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> 296]>; 297 298// X86-32 C return-value convention. 299def RetCC_X86_32_C : CallingConv<[ 300 // The X86-32 calling convention returns FP values in FP0, unless marked 301 // with "inreg" (used here to distinguish one kind of reg from another, 302 // weirdly; this is really the sse-regparm calling convention) in which 303 // case they use XMM0, otherwise it is the same as the common X86 calling 304 // conv. 305 CCIfInReg<CCIfSubtarget<"hasSSE2()", 306 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 307 CCIfSubtarget<"hasX87()", 308 CCIfType<[f32, f64], CCAssignToReg<[FP0, FP1]>>>, 309 CCIfNotSubtarget<"hasX87()", 310 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>, 311 CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>, 312 CCDelegateTo<RetCC_X86Common> 313]>; 314 315// X86-32 FastCC return-value convention. 316def RetCC_X86_32_Fast : CallingConv<[ 317 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 318 // SSE2. 319 // This can happen when a float, 2 x float, or 3 x float vector is split by 320 // target lowering, and is returned in 1-3 sse regs. 321 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 322 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 323 324 // For integers, ECX can be used as an extra return register 325 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 326 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 327 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 328 329 // Otherwise, it is the same as the common X86 calling convention. 330 CCDelegateTo<RetCC_X86Common> 331]>; 332 333// Intel_OCL_BI return-value convention. 334def RetCC_Intel_OCL_BI : CallingConv<[ 335 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 336 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 337 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 338 339 // 256-bit FP vectors 340 // No more than 4 registers 341 CCIfType<[v8f32, v4f64, v8i32, v4i64], 342 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 343 344 // 512-bit FP vectors 345 CCIfType<[v16f32, v8f64, v16i32, v8i64], 346 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 347 348 // i32, i64 in the standard way 349 CCDelegateTo<RetCC_X86Common> 350]>; 351 352// X86-32 HiPE return-value convention. 353def RetCC_X86_32_HiPE : CallingConv<[ 354 // Promote all types to i32 355 CCIfType<[i8, i16], CCPromoteToType<i32>>, 356 357 // Return: HP, P, VAL1, VAL2 358 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 359]>; 360 361// X86-32 Vectorcall return-value convention. 362def RetCC_X86_32_VectorCall : CallingConv<[ 363 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. 364 CCIfType<[f32, f64, f128], 365 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 366 367 // Return integers in the standard way. 368 CCDelegateTo<RetCC_X86Common> 369]>; 370 371// X86-64 C return-value convention. 372def RetCC_X86_64_C : CallingConv<[ 373 // The X86-64 calling convention always returns FP values in XMM0. 374 CCIfType<[f16], CCAssignToReg<[XMM0, XMM1]>>, 375 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 376 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 377 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 378 379 // MMX vector types are always returned in XMM0. 380 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 381 382 // Pointers are always returned in full 64-bit registers. 383 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 384 385 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 386 387 CCDelegateTo<RetCC_X86Common> 388]>; 389 390// X86-Win64 C return-value convention. 391def RetCC_X86_Win64_C : CallingConv<[ 392 // The X86-Win64 calling convention always returns __m64 values in RAX. 393 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 394 395 // GCC returns FP values in RAX on Win64. 396 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 397 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 398 399 // Otherwise, everything is the same as 'normal' X86-64 C CC. 400 CCDelegateTo<RetCC_X86_64_C> 401]>; 402 403// X86-64 vectorcall return-value convention. 404def RetCC_X86_64_Vectorcall : CallingConv<[ 405 // Vectorcall calling convention always returns FP values in XMMs. 406 CCIfType<[f32, f64, f128], 407 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 408 409 // Otherwise, everything is the same as Windows X86-64 C CC. 410 CCDelegateTo<RetCC_X86_Win64_C> 411]>; 412 413// X86-64 HiPE return-value convention. 414def RetCC_X86_64_HiPE : CallingConv<[ 415 // Promote all types to i64 416 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 417 418 // Return: HP, P, VAL1, VAL2 419 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 420]>; 421 422def RetCC_X86_64_Swift : CallingConv<[ 423 424 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 425 426 // For integers, ECX, R8D can be used as extra return registers. 427 CCIfType<[v1i1], CCPromoteToType<i8>>, 428 CCIfType<[i1], CCPromoteToType<i8>>, 429 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, 430 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, 431 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 432 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 433 434 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. 435 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 436 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 437 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 438 439 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. 440 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 441 CCDelegateTo<RetCC_X86Common> 442]>; 443 444// X86-64 AnyReg return-value convention. No explicit register is specified for 445// the return-value. The register allocator is allowed and expected to choose 446// any free register. 447// 448// This calling convention is currently only supported by the stackmap and 449// patchpoint intrinsics. All other uses will result in an assert on Debug 450// builds. On Release builds we fallback to the X86 C calling convention. 451def RetCC_X86_64_AnyReg : CallingConv<[ 452 CCCustom<"CC_X86_AnyReg_Error"> 453]>; 454 455 456defm X86_32_RegCall : 457 X86_RegCall_base<RC_X86_32_RegCall>; 458defm X86_32_RegCallv4_Win : 459 X86_RegCall_base<RC_X86_32_RegCallv4_Win>; 460defm X86_Win64_RegCall : 461 X86_RegCall_base<RC_X86_64_RegCall_Win>; 462defm X86_Win64_RegCallv4 : 463 X86_RegCall_base<RC_X86_64_RegCallv4_Win>; 464defm X86_SysV64_RegCall : 465 X86_RegCall_base<RC_X86_64_RegCall_SysV>; 466 467// This is the root return-value convention for the X86-32 backend. 468def RetCC_X86_32 : CallingConv<[ 469 // If FastCC, use RetCC_X86_32_Fast. 470 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 471 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>, 472 // CFGuard_Check never returns a value so does not need a RetCC. 473 // If HiPE, use RetCC_X86_32_HiPE. 474 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 475 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 476 CCIfCC<"CallingConv::X86_RegCall", 477 CCIfSubtarget<"isTargetWin32()", CCIfRegCallv4<CCDelegateTo<RetCC_X86_32_RegCallv4_Win>>>>, 478 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>, 479 480 // Otherwise, use RetCC_X86_32_C. 481 CCDelegateTo<RetCC_X86_32_C> 482]>; 483 484// This is the root return-value convention for the X86-64 backend. 485def RetCC_X86_64 : CallingConv<[ 486 // HiPE uses RetCC_X86_64_HiPE 487 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 488 489 // Handle AnyReg calls. 490 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 491 492 // Handle Swift calls. 493 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>, 494 CCIfCC<"CallingConv::SwiftTail", CCDelegateTo<RetCC_X86_64_Swift>>, 495 496 // Handle explicit CC selection 497 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 498 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 499 500 // Handle Vectorcall CC 501 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>, 502 503 CCIfCC<"CallingConv::X86_RegCall", 504 CCIfSubtarget<"isTargetWin64()", CCIfRegCallv4<CCDelegateTo<RetCC_X86_Win64_RegCallv4>>>>, 505 506 CCIfCC<"CallingConv::X86_RegCall", 507 CCIfSubtarget<"isTargetWin64()", 508 CCDelegateTo<RetCC_X86_Win64_RegCall>>>, 509 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>, 510 511 // Mingw64 and native Win64 use Win64 CC 512 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 513 514 // Otherwise, drop to normal X86-64 CC 515 CCDelegateTo<RetCC_X86_64_C> 516]>; 517 518// This is the return-value convention used for the entire X86 backend. 519let Entry = 1 in 520def RetCC_X86 : CallingConv<[ 521 522 // Check if this is the Intel OpenCL built-ins calling convention 523 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 524 525 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 526 CCDelegateTo<RetCC_X86_32> 527]>; 528 529//===----------------------------------------------------------------------===// 530// X86-64 Argument Calling Conventions 531//===----------------------------------------------------------------------===// 532 533def CC_X86_64_C : CallingConv<[ 534 // Handles byval parameters. 535 CCIfByVal<CCPassByVal<8, 8>>, 536 537 // Promote i1/i8/i16/v1i1 arguments to i32. 538 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 539 540 // The 'nest' parameter, if any, is passed in R10. 541 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 542 CCIfNest<CCAssignToReg<[R10]>>, 543 544 // Pass SwiftSelf in a callee saved register. 545 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 546 547 // A SwiftError is passed in R12. 548 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 549 550 // Pass SwiftAsync in an otherwise callee saved register so that calls to 551 // normal functions don't need to save it somewhere. 552 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 553 554 // For Swift Calling Conventions, pass sret in %rax. 555 CCIfCC<"CallingConv::Swift", 556 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 557 CCIfCC<"CallingConv::SwiftTail", 558 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 559 560 // Pointers are always passed in full 64-bit registers. 561 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 562 563 // The first 6 integer arguments are passed in integer registers. 564 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 565 566 // i128 can be either passed in two i64 registers, or on the stack, but 567 // not split across register and stack. As such, do not allow using R9 568 // for a split i64. 569 CCIfType<[i64], 570 CCIfSplit<CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>, 571 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [R9]>>>, 572 573 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 574 575 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 576 CCIfType<[x86mmx], 577 CCIfSubtarget<"isTargetDarwin()", 578 CCIfSubtarget<"hasSSE2()", 579 CCPromoteToType<v2i64>>>>, 580 581 // Boolean vectors of AVX-512 are passed in SIMD registers. 582 // The call from AVX to AVX-512 function should work, 583 // since the boolean types in AVX/AVX2 are promoted by default. 584 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 585 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 586 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 587 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 588 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 589 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 590 591 // The first 8 FP/Vector arguments are passed in XMM registers. 592 CCIfType<[f16, f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 593 CCIfSubtarget<"hasSSE1()", 594 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 595 596 // The first 8 256-bit vector arguments are passed in YMM registers, unless 597 // this is a vararg function. 598 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 599 // fixed arguments to vararg functions are supposed to be passed in 600 // registers. Actually modeling that would be a lot of work, though. 601 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 602 CCIfSubtarget<"hasAVX()", 603 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 604 YMM4, YMM5, YMM6, YMM7]>>>>, 605 606 // The first 8 512-bit vector arguments are passed in ZMM registers. 607 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 608 CCIfSubtarget<"hasAVX512()", 609 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 610 611 // Integer/FP values get stored in stack slots that are 8 bytes in size and 612 // 8-byte aligned if there are no more registers to hold them. 613 CCIfType<[i32, i64, f16, f32, f64], CCAssignToStack<8, 8>>, 614 615 // Long doubles get stack slots whose size and alignment depends on the 616 // subtarget. 617 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 618 619 // Vectors get 16-byte stack slots that are 16-byte aligned. 620 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCAssignToStack<16, 16>>, 621 622 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 623 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 624 CCAssignToStack<32, 32>>, 625 626 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 627 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 628 CCAssignToStack<64, 64>> 629]>; 630 631// Calling convention used on Win64 632def CC_X86_Win64_C : CallingConv<[ 633 // FIXME: Handle varargs. 634 635 // Byval aggregates are passed by pointer 636 CCIfByVal<CCPassIndirect<i64>>, 637 638 // Promote i1/v1i1 arguments to i8. 639 CCIfType<[i1, v1i1], CCPromoteToType<i8>>, 640 641 // The 'nest' parameter, if any, is passed in R10. 642 CCIfNest<CCAssignToReg<[R10]>>, 643 644 // A SwiftError is passed in R12. 645 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 646 647 // Pass SwiftSelf in a callee saved register. 648 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 649 650 // Pass SwiftAsync in an otherwise callee saved register so that calls to 651 // normal functions don't need to save it somewhere. 652 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 653 654 // The 'CFGuardTarget' parameter, if any, is passed in RAX. 655 CCIfCFGuardTarget<CCAssignToReg<[RAX]>>, 656 657 // 128 bit vectors are passed by pointer 658 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>, 659 660 // 256 bit vectors are passed by pointer 661 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>, 662 663 // 512 bit vectors are passed by pointer 664 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 665 666 // Long doubles are passed by pointer 667 CCIfType<[f80], CCPassIndirect<i64>>, 668 669 // The first 4 MMX vector arguments are passed in GPRs. 670 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 671 672 // If SSE was disabled, pass FP values smaller than 64-bits as integers in 673 // GPRs or on the stack. 674 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 675 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 676 677 // The first 4 FP/Vector arguments are passed in XMM registers. 678 CCIfType<[f16, f32, f64], 679 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 680 [RCX , RDX , R8 , R9 ]>>, 681 682 // The first 4 integer arguments are passed in integer registers. 683 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], 684 [XMM0, XMM1, XMM2, XMM3]>>, 685 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], 686 [XMM0, XMM1, XMM2, XMM3]>>, 687 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 688 [XMM0, XMM1, XMM2, XMM3]>>, 689 690 // Do not pass the sret argument in RCX, the Win64 thiscall calling 691 // convention requires "this" to be passed in RCX. 692 CCIfCC<"CallingConv::X86_ThisCall", 693 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 694 [XMM1, XMM2, XMM3]>>>>, 695 696 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 697 [XMM0, XMM1, XMM2, XMM3]>>, 698 699 // Integer/FP values get stored in stack slots that are 8 bytes in size and 700 // 8-byte aligned if there are no more registers to hold them. 701 CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>> 702]>; 703 704def CC_X86_Win64_VectorCall : CallingConv<[ 705 CCCustom<"CC_X86_64_VectorCall">, 706 707 // Delegate to fastcall to handle integer types. 708 CCDelegateTo<CC_X86_Win64_C> 709]>; 710 711 712def CC_X86_64_GHC : CallingConv<[ 713 // Promote i8/i16/i32 arguments to i64. 714 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 715 716 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 717 CCIfType<[i64], 718 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 719 720 // Pass in STG registers: F1, F2, F3, F4, D1, D2 721 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 722 CCIfSubtarget<"hasSSE1()", 723 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, 724 // AVX 725 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 726 CCIfSubtarget<"hasAVX()", 727 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, 728 // AVX-512 729 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 730 CCIfSubtarget<"hasAVX512()", 731 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> 732]>; 733 734def CC_X86_64_HiPE : CallingConv<[ 735 // Promote i8/i16/i32 arguments to i64. 736 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 737 738 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 739 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 740 741 // Integer/FP values get stored in stack slots that are 8 bytes in size and 742 // 8-byte aligned if there are no more registers to hold them. 743 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 744]>; 745 746// No explicit register is specified for the AnyReg calling convention. The 747// register allocator may assign the arguments to any free register. 748// 749// This calling convention is currently only supported by the stackmap and 750// patchpoint intrinsics. All other uses will result in an assert on Debug 751// builds. On Release builds we fallback to the X86 C calling convention. 752def CC_X86_64_AnyReg : CallingConv<[ 753 CCCustom<"CC_X86_AnyReg_Error"> 754]>; 755 756//===----------------------------------------------------------------------===// 757// X86 C Calling Convention 758//===----------------------------------------------------------------------===// 759 760/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 761/// values are spilled on the stack. 762def CC_X86_32_Vector_Common : CallingConv<[ 763 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 764 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 765 CCAssignToStack<16, 16>>, 766 767 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 768 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 769 CCAssignToStack<32, 32>>, 770 771 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 772 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 773 CCAssignToStack<64, 64>> 774]>; 775 776/// CC_X86_Win32_Vector - In X86 Win32 calling conventions, extra vector 777/// values are spilled on the stack. 778def CC_X86_Win32_Vector : CallingConv<[ 779 // Other SSE vectors get 16-byte stack slots that are 4-byte aligned. 780 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 781 CCAssignToStack<16, 4>>, 782 783 // 256-bit AVX vectors get 32-byte stack slots that are 4-byte aligned. 784 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 785 CCAssignToStack<32, 4>>, 786 787 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 4-byte aligned. 788 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 789 CCAssignToStack<64, 4>> 790]>; 791 792// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 793// vector registers 794def CC_X86_32_Vector_Standard : CallingConv<[ 795 // SSE vector arguments are passed in XMM registers. 796 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 797 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 798 799 // AVX 256-bit vector arguments are passed in YMM registers. 800 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 801 CCIfSubtarget<"hasAVX()", 802 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 803 804 // AVX 512-bit vector arguments are passed in ZMM registers. 805 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 806 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 807 808 CCIfIsVarArgOnWin<CCDelegateTo<CC_X86_Win32_Vector>>, 809 CCDelegateTo<CC_X86_32_Vector_Common> 810]>; 811 812// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 813// vector registers. 814def CC_X86_32_Vector_Darwin : CallingConv<[ 815 // SSE vector arguments are passed in XMM registers. 816 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 817 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 818 819 // AVX 256-bit vector arguments are passed in YMM registers. 820 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 821 CCIfSubtarget<"hasAVX()", 822 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 823 824 // AVX 512-bit vector arguments are passed in ZMM registers. 825 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 826 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 827 828 CCDelegateTo<CC_X86_32_Vector_Common> 829]>; 830 831/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 832/// values are spilled on the stack. 833def CC_X86_32_Common : CallingConv<[ 834 // Handles byval/preallocated parameters. 835 CCIfByVal<CCPassByVal<4, 4>>, 836 CCIfPreallocated<CCPassByVal<4, 4>>, 837 838 // The first 3 float or double arguments, if marked 'inreg' and if the call 839 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 840 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 841 CCIfSubtarget<"hasSSE2()", 842 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 843 844 CCIfNotVarArg<CCIfInReg<CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 845 846 // The first 3 __m64 vector arguments are passed in mmx registers if the 847 // call is not a vararg call. 848 CCIfNotVarArg<CCIfType<[x86mmx], 849 CCAssignToReg<[MM0, MM1, MM2]>>>, 850 851 CCIfType<[f16], CCAssignToStack<4, 4>>, 852 853 // Integer/Float values get stored in stack slots that are 4 bytes in 854 // size and 4-byte aligned. 855 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 856 857 // Doubles get 8-byte slots that are 4-byte aligned. 858 CCIfType<[f64], CCAssignToStack<8, 4>>, 859 860 // Long doubles get slots whose size and alignment depends on the subtarget. 861 CCIfType<[f80], CCAssignToStack<0, 0>>, 862 863 // Boolean vectors of AVX-512 are passed in SIMD registers. 864 // The call from AVX to AVX-512 function should work, 865 // since the boolean types in AVX/AVX2 are promoted by default. 866 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 867 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 868 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 869 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 870 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 871 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 872 873 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 874 // passed in the parameter area. 875 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 876 877 // Darwin passes vectors in a form that differs from the i386 psABI 878 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 879 880 // Otherwise, drop to 'normal' X86-32 CC 881 CCDelegateTo<CC_X86_32_Vector_Standard> 882]>; 883 884def CC_X86_32_C : CallingConv<[ 885 // Promote i1/i8/i16/v1i1 arguments to i32. 886 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 887 888 // The 'nest' parameter, if any, is passed in ECX. 889 CCIfNest<CCAssignToReg<[ECX]>>, 890 891 // On swifttailcc pass swiftself in ECX. 892 CCIfCC<"CallingConv::SwiftTail", 893 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[ECX]>>>>, 894 895 // The first 3 integer arguments, if marked 'inreg' and if the call is not 896 // a vararg call, are passed in integer registers. 897 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 898 899 // Otherwise, same as everything else. 900 CCDelegateTo<CC_X86_32_Common> 901]>; 902 903def CC_X86_32_MCU : CallingConv<[ 904 // Handles byval parameters. Note that, like FastCC, we can't rely on 905 // the delegation to CC_X86_32_Common because that happens after code that 906 // puts arguments in registers. 907 CCIfByVal<CCPassByVal<4, 4>>, 908 909 // Promote i1/i8/i16/v1i1 arguments to i32. 910 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 911 912 // If the call is not a vararg call, some arguments may be passed 913 // in integer registers. 914 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>, 915 916 // Otherwise, same as everything else. 917 CCDelegateTo<CC_X86_32_Common> 918]>; 919 920def CC_X86_32_FastCall : CallingConv<[ 921 // Promote i1 to i8. 922 CCIfType<[i1], CCPromoteToType<i8>>, 923 924 // The 'nest' parameter, if any, is passed in EAX. 925 CCIfNest<CCAssignToReg<[EAX]>>, 926 927 // The first 2 integer arguments are passed in ECX/EDX 928 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, 929 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, 930 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 931 932 // Otherwise, same as everything else. 933 CCDelegateTo<CC_X86_32_Common> 934]>; 935 936def CC_X86_Win32_VectorCall : CallingConv<[ 937 // Pass floating point in XMMs 938 CCCustom<"CC_X86_32_VectorCall">, 939 940 // Delegate to fastcall to handle integer types. 941 CCDelegateTo<CC_X86_32_FastCall> 942]>; 943 944def CC_X86_32_ThisCall_Common : CallingConv<[ 945 // The first integer argument is passed in ECX 946 CCIfType<[i32], CCAssignToReg<[ECX]>>, 947 948 // Otherwise, same as everything else. 949 CCDelegateTo<CC_X86_32_Common> 950]>; 951 952def CC_X86_32_ThisCall_Mingw : CallingConv<[ 953 // Promote i1/i8/i16/v1i1 arguments to i32. 954 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 955 956 CCDelegateTo<CC_X86_32_ThisCall_Common> 957]>; 958 959def CC_X86_32_ThisCall_Win : CallingConv<[ 960 // Promote i1/i8/i16/v1i1 arguments to i32. 961 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 962 963 // Pass sret arguments indirectly through stack. 964 CCIfSRet<CCAssignToStack<4, 4>>, 965 966 CCDelegateTo<CC_X86_32_ThisCall_Common> 967]>; 968 969def CC_X86_32_ThisCall : CallingConv<[ 970 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 971 CCDelegateTo<CC_X86_32_ThisCall_Win> 972]>; 973 974def CC_X86_32_FastCC : CallingConv<[ 975 // Handles byval parameters. Note that we can't rely on the delegation 976 // to CC_X86_32_Common for this because that happens after code that 977 // puts arguments in registers. 978 CCIfByVal<CCPassByVal<4, 4>>, 979 980 // Promote i1/i8/i16/v1i1 arguments to i32. 981 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 982 983 // The 'nest' parameter, if any, is passed in EAX. 984 CCIfNest<CCAssignToReg<[EAX]>>, 985 986 // The first 2 integer arguments are passed in ECX/EDX 987 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 988 989 // The first 3 float or double arguments, if the call is not a vararg 990 // call and if SSE2 is available, are passed in SSE registers. 991 CCIfNotVarArg<CCIfType<[f32,f64], 992 CCIfSubtarget<"hasSSE2()", 993 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 994 995 // Doubles get 8-byte slots that are 8-byte aligned. 996 CCIfType<[f64], CCAssignToStack<8, 8>>, 997 998 // Otherwise, same as everything else. 999 CCDelegateTo<CC_X86_32_Common> 1000]>; 1001 1002def CC_X86_Win32_CFGuard_Check : CallingConv<[ 1003 // The CFGuard check call takes exactly one integer argument 1004 // (i.e. the target function address), which is passed in ECX. 1005 CCIfType<[i32], CCAssignToReg<[ECX]>> 1006]>; 1007 1008def CC_X86_32_GHC : CallingConv<[ 1009 // Promote i8/i16 arguments to i32. 1010 CCIfType<[i8, i16], CCPromoteToType<i32>>, 1011 1012 // Pass in STG registers: Base, Sp, Hp, R1 1013 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 1014]>; 1015 1016def CC_X86_32_HiPE : CallingConv<[ 1017 // Promote i8/i16 arguments to i32. 1018 CCIfType<[i8, i16], CCPromoteToType<i32>>, 1019 1020 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 1021 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 1022 1023 // Integer/Float values get stored in stack slots that are 4 bytes in 1024 // size and 4-byte aligned. 1025 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 1026]>; 1027 1028// X86-64 Intel OpenCL built-ins calling convention. 1029def CC_Intel_OCL_BI : CallingConv<[ 1030 1031 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 1032 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 1033 1034 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 1035 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 1036 1037 CCIfType<[i32], CCAssignToStack<4, 4>>, 1038 1039 // The SSE vector arguments are passed in XMM registers. 1040 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 1041 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 1042 1043 // The 256-bit vector arguments are passed in YMM registers. 1044 CCIfType<[v8f32, v4f64, v8i32, v4i64], 1045 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 1046 1047 // The 512-bit vector arguments are passed in ZMM registers. 1048 CCIfType<[v16f32, v8f64, v16i32, v8i64], 1049 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 1050 1051 // Pass masks in mask registers 1052 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 1053 1054 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1055 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 1056 CCDelegateTo<CC_X86_32_C> 1057]>; 1058 1059//===----------------------------------------------------------------------===// 1060// X86 Root Argument Calling Conventions 1061//===----------------------------------------------------------------------===// 1062 1063// This is the root argument convention for the X86-32 backend. 1064def CC_X86_32 : CallingConv<[ 1065 // X86_INTR calling convention is valid in MCU target and should override the 1066 // MCU calling convention. Thus, this should be checked before isTargetMCU(). 1067 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1068 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>, 1069 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 1070 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>, 1071 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 1072 CCIfCC<"CallingConv::CFGuard_Check", CCDelegateTo<CC_X86_Win32_CFGuard_Check>>, 1073 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 1074 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>, 1075 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 1076 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 1077 CCIfCC<"CallingConv::X86_RegCall", 1078 CCIfSubtarget<"isTargetWin32()", CCIfRegCallv4<CCDelegateTo<CC_X86_32_RegCallv4_Win>>>>, 1079 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>, 1080 1081 // Otherwise, drop to normal X86-32 CC 1082 CCDelegateTo<CC_X86_32_C> 1083]>; 1084 1085// This is the root argument convention for the X86-64 backend. 1086def CC_X86_64 : CallingConv<[ 1087 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 1088 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 1089 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 1090 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>, 1091 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 1092 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 1093 CCIfCC<"CallingConv::X86_RegCall", 1094 CCIfSubtarget<"isTargetWin64()", CCIfRegCallv4<CCDelegateTo<CC_X86_Win64_RegCallv4>>>>, 1095 CCIfCC<"CallingConv::X86_RegCall", 1096 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>, 1097 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>, 1098 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1099 1100 // Mingw64 and native Win64 use Win64 CC 1101 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1102 1103 // Otherwise, drop to normal X86-64 CC 1104 CCDelegateTo<CC_X86_64_C> 1105]>; 1106 1107// This is the argument convention used for the entire X86 backend. 1108let Entry = 1 in 1109def CC_X86 : CallingConv<[ 1110 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 1111 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 1112 CCDelegateTo<CC_X86_32> 1113]>; 1114 1115//===----------------------------------------------------------------------===// 1116// Callee-saved Registers. 1117//===----------------------------------------------------------------------===// 1118 1119def CSR_NoRegs : CalleeSavedRegs<(add)>; 1120 1121def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1122def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 1123 1124def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; 1125def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>; 1126 1127def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 1128def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 1129 1130def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; 1131 1132def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, 1133 (sequence "XMM%u", 6, 15))>; 1134 1135def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; 1136def CSR_Win64_SwiftTail : CalleeSavedRegs<(sub CSR_Win64, R13, R14)>; 1137 1138// The function used by Darwin to obtain the address of a thread-local variable 1139// uses rdi to pass a single parameter and rax for the return value. All other 1140// GPRs are preserved. 1141def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 1142 R8, R9, R10, R11)>; 1143 1144// CSRs that are handled by prologue, epilogue. 1145def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; 1146 1147// CSRs that are handled explicitly via copies. 1148def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; 1149 1150// All GPRs - except r11 and return registers. 1151def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 1152 R8, R9, R10)>; 1153 1154def CSR_Win64_RT_MostRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1155 (sequence "XMM%u", 6, 15))>; 1156 1157// All registers - except r11 and return registers. 1158def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1159 (sequence "XMM%u", 0, 15))>; 1160def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1161 (sequence "YMM%u", 0, 15))>; 1162 1163def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 1164 R11, R12, R13, R14, R15, RBP, 1165 (sequence "XMM%u", 0, 15))>; 1166 1167def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 1168 EDI)>; 1169def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 1170 (sequence "XMM%u", 0, 7))>; 1171def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, 1172 (sequence "YMM%u", 0, 7))>; 1173def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, 1174 (sequence "ZMM%u", 0, 7), 1175 (sequence "K%u", 0, 7))>; 1176 1177def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; 1178def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, 1179 R10, R11, R12, R13, R14, R15, RBP)>; 1180def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1181 (sequence "YMM%u", 0, 15)), 1182 (sequence "XMM%u", 0, 15))>; 1183def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1184 (sequence "ZMM%u", 0, 31), 1185 (sequence "K%u", 0, 7)), 1186 (sequence "XMM%u", 0, 15))>; 1187 1188// Standard C + YMM6-15 1189def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 1190 R13, R14, R15, 1191 (sequence "YMM%u", 6, 15))>; 1192 1193def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 1194 R12, R13, R14, R15, 1195 (sequence "ZMM%u", 6, 21), 1196 K4, K5, K6, K7)>; 1197//Standard C + XMM 8-15 1198def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 1199 (sequence "XMM%u", 8, 15))>; 1200 1201//Standard C + YMM 8-15 1202def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 1203 (sequence "YMM%u", 8, 15))>; 1204 1205def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15, 1206 (sequence "ZMM%u", 16, 31), 1207 K4, K5, K6, K7)>; 1208 1209// Register calling convention preserves few GPR and XMM8-15 1210def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1211def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 1212 (sequence "XMM%u", 4, 7))>; 1213def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, ECX)>; 1214def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>; 1215def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1216 (sequence "R%u", 10, 15))>; 1217def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1218 (sequence "XMM%u", 8, 15))>; 1219def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1220 (sequence "R%u", 12, 15))>; 1221def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1222 (sequence "XMM%u", 8, 15))>; 1223