1//===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// \file 9/// This file defines all the static objects used by X86RegisterBankInfo. 10/// \todo This should be generated by TableGen. 11//===----------------------------------------------------------------------===// 12 13#ifdef GET_TARGET_REGBANK_INFO_IMPL 14RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{ 15 /* StartIdx, Length, RegBank */ 16 // GPR value 17 {0, 8, X86::GPRRegBank}, // :0 18 {0, 16, X86::GPRRegBank}, // :1 19 {0, 32, X86::GPRRegBank}, // :2 20 {0, 64, X86::GPRRegBank}, // :3 21 // FR32/64 , xmm registers 22 {0, 32, X86::VECRRegBank}, // :4 23 {0, 64, X86::VECRRegBank}, // :5 24 // VR128/256/512 25 {0, 128, X86::VECRRegBank}, // :6 26 {0, 256, X86::VECRRegBank}, // :7 27 {0, 512, X86::VECRRegBank}, // :8 28}; 29#endif // GET_TARGET_REGBANK_INFO_IMPL 30 31#ifdef GET_TARGET_REGBANK_INFO_CLASS 32enum PartialMappingIdx { 33 PMI_None = -1, 34 PMI_GPR8, 35 PMI_GPR16, 36 PMI_GPR32, 37 PMI_GPR64, 38 PMI_FP32, 39 PMI_FP64, 40 PMI_VEC128, 41 PMI_VEC256, 42 PMI_VEC512 43}; 44#endif // GET_TARGET_REGBANK_INFO_CLASS 45 46#ifdef GET_TARGET_REGBANK_INFO_IMPL 47#define INSTR_3OP(INFO) INFO, INFO, INFO, 48#define BREAKDOWN(INDEX, NUM) \ 49 { &X86GenRegisterBankInfo::PartMappings[INDEX], NUM } 50// ValueMappings. 51RegisterBankInfo::ValueMapping X86GenRegisterBankInfo::ValMappings[]{ 52 /* BreakDown, NumBreakDowns */ 53 // 3-operands instructions (all binary operations should end up with one of 54 // those mapping). 55 INSTR_3OP(BREAKDOWN(PMI_GPR8, 1)) // 0: GPR_8 56 INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16 57 INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32 58 INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64 59 INSTR_3OP(BREAKDOWN(PMI_FP32, 1)) // 12: Fp32 60 INSTR_3OP(BREAKDOWN(PMI_FP64, 1)) // 15: Fp64 61 INSTR_3OP(BREAKDOWN(PMI_VEC128, 1)) // 18: Vec128 62 INSTR_3OP(BREAKDOWN(PMI_VEC256, 1)) // 21: Vec256 63 INSTR_3OP(BREAKDOWN(PMI_VEC512, 1)) // 24: Vec512 64}; 65#undef INSTR_3OP 66#undef BREAKDOWN 67#endif // GET_TARGET_REGBANK_INFO_IMPL 68 69#ifdef GET_TARGET_REGBANK_INFO_CLASS 70enum ValueMappingIdx { 71 VMI_None = -1, 72 VMI_3OpsGpr8Idx = PMI_GPR8 * 3, 73 VMI_3OpsGpr16Idx = PMI_GPR16 * 3, 74 VMI_3OpsGpr32Idx = PMI_GPR32 * 3, 75 VMI_3OpsGpr64Idx = PMI_GPR64 * 3, 76 VMI_3OpsFp32Idx = PMI_FP32 * 3, 77 VMI_3OpsFp64Idx = PMI_FP64 * 3, 78 VMI_3OpsVec128Idx = PMI_VEC128 * 3, 79 VMI_3OpsVec256Idx = PMI_VEC256 * 3, 80 VMI_3OpsVec512Idx = PMI_VEC512 * 3, 81}; 82#undef GET_TARGET_REGBANK_INFO_CLASS 83#endif // GET_TARGET_REGBANK_INFO_CLASS 84 85#ifdef GET_TARGET_REGBANK_INFO_IMPL 86#undef GET_TARGET_REGBANK_INFO_IMPL 87const RegisterBankInfo::ValueMapping * 88X86GenRegisterBankInfo::getValueMapping(PartialMappingIdx Idx, 89 unsigned NumOperands) { 90 91 // We can use VMI_3Ops Mapping for all the cases. 92 if (NumOperands <= 3 && (Idx >= PMI_GPR8 && Idx <= PMI_VEC512)) 93 return &ValMappings[(unsigned)Idx * 3]; 94 95 llvm_unreachable("Unsupported PartialMappingIdx."); 96} 97 98#endif // GET_TARGET_REGBANK_INFO_IMPL 99 100