1//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 jump, return, call, and related instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Control Flow Instructions. 15// 16 17// Return instructions. 18// 19// The X86retflag return instructions are variadic because we may add ST0 and 20// ST1 arguments when returning values on the x87 stack. 21let isTerminator = 1, isReturn = 1, isBarrier = 1, 22 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { 23 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), 24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>; 25 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), 26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>; 27 def RETW : I <0xC3, RawFrm, (outs), (ins), 28 "ret{w}", []>, OpSize16; 29 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>; 31 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>; 33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), 34 "ret{w}\t$amt", []>, OpSize16; 35 def LRETL : I <0xCB, RawFrm, (outs), (ins), 36 "{l}ret{l|f}", []>, OpSize32; 37 def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>; 39 def LRETW : I <0xCB, RawFrm, (outs), (ins), 40 "{l}ret{w|f}", []>, OpSize16; 41 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 42 "{l}ret{l|f}\t$amt", []>, OpSize32; 43 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>; 45 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 46 "{l}ret{w|f}\t$amt", []>, OpSize16; 47 48 // The machine return from interrupt instruction, but sometimes we need to 49 // perform a post-epilogue stack adjustment. Codegen emits the pseudo form 50 // which expands to include an SP adjustment if necessary. 51 def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, 52 OpSize16; 53 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; 54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; 55 let isCodeGenOnly = 1 in 56 def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; 57 def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; 58} 59 60// Unconditional branches. 61let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 62 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 63 "jmp\t$dst", [(br bb:$dst)]>; 64 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 65 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), 66 "jmp\t$dst", []>, OpSize16; 67 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), 68 "jmp\t$dst", []>, OpSize32; 69 } 70} 71 72// Conditional Branches. 73let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump], 74 isCodeGenOnly = 1, ForceDisassemble = 1 in { 75 def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs), 76 (ins brtarget8:$dst, ccode:$cond), 77 "j${cond}\t$dst", 78 [(X86brcond bb:$dst, imm:$cond, EFLAGS)]>; 79 let hasSideEffects = 0 in { 80 def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs), 81 (ins brtarget16:$dst, ccode:$cond), 82 "j${cond}\t$dst", 83 []>, OpSize16, TB; 84 def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs), 85 (ins brtarget32:$dst, ccode:$cond), 86 "j${cond}\t$dst", 87 []>, TB, OpSize32; 88 } 89} 90 91def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>; 92def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>; 93def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>; 94def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>; 95def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>; 96def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>; 97def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>; 98def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>; 99def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>; 100def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>; 101def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>; 102def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>; 103def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>; 104def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>; 105def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>; 106def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>; 107 108// jcx/jecx/jrcx instructions. 109let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { 110 // These are the 32-bit versions of this instruction for the asmparser. In 111 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 112 // jecxz. 113 let Uses = [CX] in 114 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 115 "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>; 116 let Uses = [ECX] in 117 def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 118 "jecxz\t$dst", []>, AdSize32; 119 120 let Uses = [RCX] in 121 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 122 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>; 123} 124 125// Indirect branches 126let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 127 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", 128 [(brind GR16:$dst)]>, Requires<[Not64BitMode]>, 129 OpSize16, Sched<[WriteJump]>; 130 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", 131 [(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>, 132 OpSize16, Sched<[WriteJumpLd]>; 133 134 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 135 [(brind GR32:$dst)]>, Requires<[Not64BitMode]>, 136 OpSize32, Sched<[WriteJump]>; 137 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 138 [(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>, 139 OpSize32, Sched<[WriteJumpLd]>; 140 141 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 142 [(brind GR64:$dst)]>, Requires<[In64BitMode]>, 143 Sched<[WriteJump]>; 144 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 145 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>, 146 Sched<[WriteJumpLd]>; 147 148 // Non-tracking jumps for IBT, use with caution. 149 let isCodeGenOnly = 1 in { 150 def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst", 151 [(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>, 152 OpSize16, Sched<[WriteJump]>, NOTRACK; 153 154 def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst", 155 [(X86NoTrackBrind (loadi16 addr : $dst))]>, 156 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>, 157 NOTRACK; 158 159 def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst", 160 [(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>, 161 OpSize32, Sched<[WriteJump]>, NOTRACK; 162 def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst", 163 [(X86NoTrackBrind (loadi32 addr : $dst))]>, 164 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>, 165 NOTRACK; 166 167 def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst", 168 [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>, 169 Sched<[WriteJump]>, NOTRACK; 170 def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst", 171 [(X86NoTrackBrind(loadi64 addr : $dst))]>, 172 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK; 173 } 174 175 let Predicates = [Not64BitMode], AsmVariantName = "att" in { 176 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 177 (ins i16imm:$off, i16imm:$seg), 178 "ljmp{w}\t$seg, $off", []>, 179 OpSize16, Sched<[WriteJump]>; 180 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 181 (ins i32imm:$off, i16imm:$seg), 182 "ljmp{l}\t$seg, $off", []>, 183 OpSize32, Sched<[WriteJump]>; 184 } 185 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 186 "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>; 187 188 let AsmVariantName = "att" in 189 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 190 "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; 191 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 192 "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; 193} 194 195// Loop instructions 196let SchedRW = [WriteJump] in { 197def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; 198def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; 199def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; 200} 201 202//===----------------------------------------------------------------------===// 203// Call Instructions... 204// 205let isCall = 1 in 206 // All calls clobber the non-callee saved registers. ESP is marked as 207 // a use to prevent stack-pointer assignments that appear immediately 208 // before calls from potentially appearing dead. Uses for argument 209 // registers are added manually. 210 let Uses = [ESP, SSP] in { 211 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 212 (outs), (ins i32imm_pcrel:$dst), 213 "call{l}\t$dst", []>, OpSize32, 214 Requires<[Not64BitMode]>, Sched<[WriteJump]>; 215 let hasSideEffects = 0 in 216 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 217 (outs), (ins i16imm_pcrel:$dst), 218 "call{w}\t$dst", []>, OpSize16, 219 Sched<[WriteJump]>; 220 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), 221 "call{w}\t{*}$dst", [(X86call GR16:$dst)]>, 222 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; 223 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), 224 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>, 225 OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, 226 Sched<[WriteJumpLd]>; 227 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 228 "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32, 229 Requires<[Not64BitMode,NotUseRetpolineIndirectCalls]>, 230 Sched<[WriteJump]>; 231 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), 232 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, 233 OpSize32, 234 Requires<[Not64BitMode,FavorMemIndirectCall, 235 NotUseRetpolineIndirectCalls]>, 236 Sched<[WriteJumpLd]>; 237 238 // Non-tracking calls for IBT, use with caution. 239 let isCodeGenOnly = 1 in { 240 def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst), 241 "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>, 242 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; 243 def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst), 244 "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>, 245 OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, 246 Sched<[WriteJumpLd]>, NOTRACK; 247 def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst), 248 "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>, 249 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; 250 def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst), 251 "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>, 252 OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>, 253 Sched<[WriteJumpLd]>, NOTRACK; 254 } 255 256 let Predicates = [Not64BitMode], AsmVariantName = "att" in { 257 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 258 (ins i16imm:$off, i16imm:$seg), 259 "lcall{w}\t$seg, $off", []>, 260 OpSize16, Sched<[WriteJump]>; 261 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 262 (ins i32imm:$off, i16imm:$seg), 263 "lcall{l}\t$seg, $off", []>, 264 OpSize32, Sched<[WriteJump]>; 265 } 266 267 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 268 "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; 269 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 270 "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; 271 } 272 273 274// Tail call stuff. 275let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 276 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 277 let Uses = [ESP, SSP] in { 278 def TCRETURNdi : PseudoI<(outs), 279 (ins i32imm_pcrel:$dst, i32imm:$offset), []>, NotMemoryFoldable; 280 def TCRETURNri : PseudoI<(outs), 281 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; 282 let mayLoad = 1 in 283 def TCRETURNmi : PseudoI<(outs), 284 (ins i32mem_TC:$dst, i32imm:$offset), []>; 285 286 // FIXME: The should be pseudo instructions that are lowered when going to 287 // mcinst. 288 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), 289 (ins i32imm_pcrel:$dst), "jmp\t$dst", []>; 290 291 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 292 "", []>; // FIXME: Remove encoding when JIT is dead. 293 let mayLoad = 1 in 294 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), 295 "jmp{l}\t{*}$dst", []>; 296} 297 298// Conditional tail calls are similar to the above, but they are branches 299// rather than barriers, and they use EFLAGS. 300let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, 301 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 302 let Uses = [ESP, EFLAGS, SSP] in { 303 def TCRETURNdicc : PseudoI<(outs), 304 (ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>; 305 306 // This gets substituted to a conditional jump instruction in MC lowering. 307 def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs), 308 (ins i32imm_pcrel:$dst, i32imm:$cond), "", []>; 309} 310 311 312//===----------------------------------------------------------------------===// 313// Call Instructions... 314// 315 316// RSP is marked as a use to prevent stack-pointer assignments that appear 317// immediately before calls from potentially appearing dead. Uses for argument 318// registers are added manually. 319let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { 320 // NOTE: this pattern doesn't match "X86call imm", because we do not know 321 // that the offset between an arbitrary immediate and the call will fit in 322 // the 32-bit pcrel field that we have. 323 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 324 (outs), (ins i64i32imm_pcrel:$dst), 325 "call{q}\t$dst", []>, OpSize32, 326 Requires<[In64BitMode]>; 327 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), 328 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, 329 Requires<[In64BitMode,NotUseRetpolineIndirectCalls]>; 330 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), 331 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, 332 Requires<[In64BitMode,FavorMemIndirectCall, 333 NotUseRetpolineIndirectCalls]>; 334 335 // Non-tracking calls for IBT, use with caution. 336 let isCodeGenOnly = 1 in { 337 def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst), 338 "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>, 339 Requires<[In64BitMode]>, NOTRACK; 340 def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst), 341 "call{q}\t{*}$dst", 342 [(X86NoTrackCall(loadi64 addr : $dst))]>, 343 Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK; 344 } 345 346 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 347 "lcall{q}\t{*}$dst", []>; 348} 349 350let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 351 isCodeGenOnly = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { 352 def TCRETURNdi64 : PseudoI<(outs), 353 (ins i64i32imm_pcrel:$dst, i32imm:$offset), 354 []>; 355 def TCRETURNri64 : PseudoI<(outs), 356 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; 357 let mayLoad = 1 in 358 def TCRETURNmi64 : PseudoI<(outs), 359 (ins i64mem_TC:$dst, i32imm:$offset), []>, NotMemoryFoldable; 360 361 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), 362 "jmp\t$dst", []>; 363 364 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 365 "jmp{q}\t{*}$dst", []>; 366 367 let mayLoad = 1 in 368 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 369 "jmp{q}\t{*}$dst", []>; 370 371 // Win64 wants indirect jumps leaving the function to have a REX_W prefix. 372 let hasREX_WPrefix = 1 in { 373 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 374 "rex64 jmp{q}\t{*}$dst", []>; 375 376 let mayLoad = 1 in 377 def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 378 "rex64 jmp{q}\t{*}$dst", []>; 379 } 380} 381 382let isPseudo = 1, isCall = 1, isCodeGenOnly = 1, 383 Uses = [RSP, SSP], 384 usesCustomInserter = 1, 385 SchedRW = [WriteJump] in { 386 def RETPOLINE_CALL32 : 387 PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>, 388 Requires<[Not64BitMode,UseRetpolineIndirectCalls]>; 389 390 def RETPOLINE_CALL64 : 391 PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>, 392 Requires<[In64BitMode,UseRetpolineIndirectCalls]>; 393 394 // Retpoline variant of indirect tail calls. 395 let isTerminator = 1, isReturn = 1, isBarrier = 1 in { 396 def RETPOLINE_TCRETURN64 : 397 PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>; 398 def RETPOLINE_TCRETURN32 : 399 PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>; 400 } 401} 402 403// Conditional tail calls are similar to the above, but they are branches 404// rather than barriers, and they use EFLAGS. 405let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, 406 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 407 let Uses = [RSP, EFLAGS, SSP] in { 408 def TCRETURNdi64cc : PseudoI<(outs), 409 (ins i64i32imm_pcrel:$dst, i32imm:$offset, 410 i32imm:$cond), []>; 411 412 // This gets substituted to a conditional jump instruction in MC lowering. 413 def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs), 414 (ins i64i32imm_pcrel:$dst, i32imm:$cond), "", []>; 415} 416