1//===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// X86 Instruction Format Definitions. 11// 12 13// Format specifies the encoding used by the instruction. This is part of the 14// ad-hoc solution used to emit machine instruction encodings by our machine 15// code emitter. 16class Format<bits<7> val> { 17 bits<7> Value = val; 18} 19 20def Pseudo : Format<0>; 21def RawFrm : Format<1>; 22def AddRegFrm : Format<2>; 23def RawFrmMemOffs : Format<3>; 24def RawFrmSrc : Format<4>; 25def RawFrmDst : Format<5>; 26def RawFrmDstSrc : Format<6>; 27def RawFrmImm8 : Format<7>; 28def RawFrmImm16 : Format<8>; 29def AddCCFrm : Format<9>; 30def PrefixByte : Format<10>; 31def MRMDestMem4VOp3CC : Format<20>; 32def MRMr0 : Format<21>; 33def MRMSrcMemFSIB : Format<22>; 34def MRMDestMemFSIB : Format<23>; 35def MRMDestMem : Format<24>; 36def MRMSrcMem : Format<25>; 37def MRMSrcMem4VOp3 : Format<26>; 38def MRMSrcMemOp4 : Format<27>; 39def MRMSrcMemCC : Format<28>; 40def MRMXmCC: Format<30>; 41def MRMXm : Format<31>; 42def MRM0m : Format<32>; def MRM1m : Format<33>; def MRM2m : Format<34>; 43def MRM3m : Format<35>; def MRM4m : Format<36>; def MRM5m : Format<37>; 44def MRM6m : Format<38>; def MRM7m : Format<39>; 45def MRMDestReg : Format<40>; 46def MRMSrcReg : Format<41>; 47def MRMSrcReg4VOp3 : Format<42>; 48def MRMSrcRegOp4 : Format<43>; 49def MRMSrcRegCC : Format<44>; 50def MRMXrCC: Format<46>; 51def MRMXr : Format<47>; 52def MRM0r : Format<48>; def MRM1r : Format<49>; def MRM2r : Format<50>; 53def MRM3r : Format<51>; def MRM4r : Format<52>; def MRM5r : Format<53>; 54def MRM6r : Format<54>; def MRM7r : Format<55>; 55def MRM0X : Format<56>; def MRM1X : Format<57>; def MRM2X : Format<58>; 56def MRM3X : Format<59>; def MRM4X : Format<60>; def MRM5X : Format<61>; 57def MRM6X : Format<62>; def MRM7X : Format<63>; 58def MRM_C0 : Format<64>; def MRM_C1 : Format<65>; def MRM_C2 : Format<66>; 59def MRM_C3 : Format<67>; def MRM_C4 : Format<68>; def MRM_C5 : Format<69>; 60def MRM_C6 : Format<70>; def MRM_C7 : Format<71>; def MRM_C8 : Format<72>; 61def MRM_C9 : Format<73>; def MRM_CA : Format<74>; def MRM_CB : Format<75>; 62def MRM_CC : Format<76>; def MRM_CD : Format<77>; def MRM_CE : Format<78>; 63def MRM_CF : Format<79>; def MRM_D0 : Format<80>; def MRM_D1 : Format<81>; 64def MRM_D2 : Format<82>; def MRM_D3 : Format<83>; def MRM_D4 : Format<84>; 65def MRM_D5 : Format<85>; def MRM_D6 : Format<86>; def MRM_D7 : Format<87>; 66def MRM_D8 : Format<88>; def MRM_D9 : Format<89>; def MRM_DA : Format<90>; 67def MRM_DB : Format<91>; def MRM_DC : Format<92>; def MRM_DD : Format<93>; 68def MRM_DE : Format<94>; def MRM_DF : Format<95>; def MRM_E0 : Format<96>; 69def MRM_E1 : Format<97>; def MRM_E2 : Format<98>; def MRM_E3 : Format<99>; 70def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>; 71def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>; 72def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>; 73def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>; 74def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>; 75def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>; 76def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>; 77def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>; 78def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>; 79def MRM_FF : Format<127>; 80 81// ImmType - This specifies the immediate type used by an instruction. This is 82// part of the ad-hoc solution used to emit machine instruction encodings by our 83// machine code emitter. 84class ImmType<bits<4> val> { 85 bits<4> Value = val; 86} 87def NoImm : ImmType<0>; 88def Imm8 : ImmType<1>; 89def Imm8PCRel : ImmType<2>; 90def Imm8Reg : ImmType<3>; // Register encoded in [7:4]. 91def Imm16 : ImmType<4>; 92def Imm16PCRel : ImmType<5>; 93def Imm32 : ImmType<6>; 94def Imm32PCRel : ImmType<7>; 95def Imm32S : ImmType<8>; 96def Imm64 : ImmType<9>; 97 98// FPFormat - This specifies what form this FP instruction has. This is used by 99// the Floating-Point stackifier pass. 100class FPFormat<bits<3> val> { 101 bits<3> Value = val; 102} 103def NotFP : FPFormat<0>; 104def ZeroArgFP : FPFormat<1>; 105def OneArgFP : FPFormat<2>; 106def OneArgFPRW : FPFormat<3>; 107def TwoArgFP : FPFormat<4>; 108def CompareFP : FPFormat<5>; 109def CondMovFP : FPFormat<6>; 110def SpecialFP : FPFormat<7>; 111 112// Class specifying the SSE execution domain, used by the SSEDomainFix pass. 113// Keep in sync with tables in X86InstrInfo.cpp. 114class Domain<bits<2> val> { 115 bits<2> Value = val; 116} 117def GenericDomain : Domain<0>; 118def SSEPackedSingle : Domain<1>; 119def SSEPackedDouble : Domain<2>; 120def SSEPackedInt : Domain<3>; 121 122// Class specifying the vector form of the decompressed 123// displacement of 8-bit. 124class CD8VForm<bits<3> val> { 125 bits<3> Value = val; 126} 127def CD8VF : CD8VForm<0>; // v := VL 128def CD8VH : CD8VForm<1>; // v := VL/2 129def CD8VQ : CD8VForm<2>; // v := VL/4 130def CD8VO : CD8VForm<3>; // v := VL/8 131// The tuple (subvector) forms. 132def CD8VT1 : CD8VForm<4>; // v := 1 133def CD8VT2 : CD8VForm<5>; // v := 2 134def CD8VT4 : CD8VForm<6>; // v := 4 135def CD8VT8 : CD8VForm<7>; // v := 8 136 137// Class specifying the prefix used an opcode extension. 138class Prefix<bits<3> val> { 139 bits<3> Value = val; 140} 141def NoPrfx : Prefix<0>; 142def PD : Prefix<1>; 143def XS : Prefix<2>; 144def XD : Prefix<3>; 145def PS : Prefix<4>; // Similar to NoPrfx, but disassembler uses this to know 146 // that other instructions with this opcode use PD/XS/XD 147 // and if any of those is not supported they shouldn't 148 // decode to this instruction. e.g. ANDSS/ANDSD don't 149 // exist, but the 0xf2/0xf3 encoding shouldn't 150 // disable to ANDPS. 151 152// Class specifying the opcode map. 153class Map<bits<4> val> { 154 bits<4> Value = val; 155} 156def OB : Map<0>; 157def TB : Map<1>; 158def T8 : Map<2>; 159def TA : Map<3>; 160def XOP8 : Map<4>; 161def XOP9 : Map<5>; 162def XOPA : Map<6>; 163def ThreeDNow : Map<7>; 164def T_MAP4 : Map<8>; 165def T_MAP5 : Map<9>; 166def T_MAP6 : Map<10>; 167def T_MAP7 : Map<11>; 168 169// Class specifying the encoding 170class Encoding<bits<2> val> { 171 bits<2> Value = val; 172} 173def EncNormal : Encoding<0>; 174def EncVEX : Encoding<1>; 175def EncXOP : Encoding<2>; 176def EncEVEX : Encoding<3>; 177 178// Operand size for encodings that change based on mode. 179class OperandSize<bits<2> val> { 180 bits<2> Value = val; 181} 182def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. 183def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32/64-bit mode. 184def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. 185 186// Address size for encodings that change based on mode. 187class AddressSize<bits<2> val> { 188 bits<2> Value = val; 189} 190def AdSizeX : AddressSize<0>; // Address size determined using addr operand. 191def AdSize16 : AddressSize<1>; // Encodes a 16-bit address. 192def AdSize32 : AddressSize<2>; // Encodes a 32-bit address. 193def AdSize64 : AddressSize<3>; // Encodes a 64-bit address. 194 195// Force the instruction to use REX2/VEX/EVEX encoding. 196class ExplicitOpPrefix<bits<2> val> { 197 bits<2> Value = val; 198} 199def NoExplicitOpPrefix : ExplicitOpPrefix<0>; 200def ExplicitREX2 : ExplicitOpPrefix<1>; 201def ExplicitVEX : ExplicitOpPrefix<2>; 202def ExplicitEVEX : ExplicitOpPrefix<3>; 203 204class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, 205 string AsmStr, Domain d = GenericDomain> 206 : Instruction { 207 let Namespace = "X86"; 208 209 bits<8> Opcode = opcod; 210 Format Form = f; 211 bits<7> FormBits = Form.Value; 212 ImmType ImmT = i; 213 214 dag OutOperandList = outs; 215 dag InOperandList = ins; 216 string AsmString = AsmStr; 217 218 // If this is a pseudo instruction, mark it isCodeGenOnly. 219 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 220 221 let HasPositionOrder = 1; 222 223 // 224 // Attributes specific to X86 instructions... 225 // 226 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's 227 // isCodeGenonly. Needed to hide an ambiguous 228 // AsmString from the parser, but still disassemble. 229 230 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change 231 // based on operand size of the mode? 232 bits<2> OpSizeBits = OpSize.Value; 233 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change 234 // based on address size of the mode? 235 bits<2> AdSizeBits = AdSize.Value; 236 237 Encoding OpEnc = EncNormal; // Encoding used by this instruction 238 // Which prefix byte does this inst have? 239 Prefix OpPrefix = !if(!eq(OpEnc, EncNormal), NoPrfx, PS); 240 bits<3> OpPrefixBits = OpPrefix.Value; 241 Map OpMap = OB; // Which opcode map does this inst have? 242 bits<4> OpMapBits = OpMap.Value; 243 bit hasREX_W = 0; // Does this inst require the REX.W prefix? 244 FPFormat FPForm = NotFP; // What flavor of FP instruction is this? 245 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? 246 Domain ExeDomain = d; 247 bit hasREPPrefix = 0; // Does this inst have a REP prefix? 248 bits<2> OpEncBits = OpEnc.Value; 249 bit IgnoresW = 0; // Does this inst ignore REX_W field? 250 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? 251 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? 252 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit 253 bit hasEVEX_K = 0; // Does this inst require masking? 254 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? 255 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? 256 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? 257 bit hasEVEX_NF = 0; // Does this inst set the EVEX_NF field? 258 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width. 259 // Declare it int rather than bits<4> so that all bits are defined when 260 // assigning to bits<7>. 261 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes. 262 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. 263 bit hasNoTrackPrefix = 0; // Does this inst has 0x3E (NoTrack) prefix? 264 265 // Vector size in bytes. 266 bits<7> VectSize = !if(hasEVEX_L2, 64, !if(hasVEX_L, 32, 16)); 267 268 // The scaling factor for AVX512's compressed displacement is either 269 // - the size of a power-of-two number of elements or 270 // - the size of a single element for broadcasts or 271 // - the total vector size divided by a power-of-two number. 272 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64. 273 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value), 274 !if (CD8_Form{2}, 275 !shl(CD8_EltSize, CD8_Form{1-0}), 276 !if (hasEVEX_B, 277 CD8_EltSize, 278 !srl(VectSize, CD8_Form{1-0}))), 0); 279 280 ExplicitOpPrefix explicitOpPrefix = NoExplicitOpPrefix; 281 bits<2> explicitOpPrefixBits = explicitOpPrefix.Value; 282 // TSFlags layout should be kept in sync with X86BaseInfo.h. 283 let TSFlags{6-0} = FormBits; 284 let TSFlags{8-7} = OpSizeBits; 285 let TSFlags{10-9} = AdSizeBits; 286 // No need for 3rd bit, we don't need to distinguish NoPrfx from PS. 287 let TSFlags{12-11} = OpPrefixBits{1-0}; 288 let TSFlags{16-13} = OpMapBits; 289 let TSFlags{17} = hasREX_W; 290 let TSFlags{21-18} = ImmT.Value; 291 let TSFlags{24-22} = FPForm.Value; 292 let TSFlags{25} = hasLockPrefix; 293 let TSFlags{26} = hasREPPrefix; 294 let TSFlags{28-27} = ExeDomain.Value; 295 let TSFlags{30-29} = OpEncBits; 296 let TSFlags{38-31} = Opcode; 297 let TSFlags{39} = hasVEX_4V; 298 let TSFlags{40} = hasVEX_L; 299 let TSFlags{41} = hasEVEX_K; 300 let TSFlags{42} = hasEVEX_Z; 301 let TSFlags{43} = hasEVEX_L2; 302 let TSFlags{44} = hasEVEX_B; 303 let TSFlags{47-45} = !if(!eq(CD8_Scale, 0), 0, !add(!logtwo(CD8_Scale), 1)); 304 let TSFlags{48} = hasEVEX_RC; 305 let TSFlags{49} = hasNoTrackPrefix; 306 let TSFlags{51-50} = explicitOpPrefixBits; 307 let TSFlags{52} = hasEVEX_NF; 308} 309