1//===-- X86InstrMisc.td - Misc X86 Instruction Definition -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defining the misc X86 instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Instruction list. 15// 16 17// Nop 18let hasSideEffects = 0, SchedRW = [WriteNop] in { 19 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; 20 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 21 "nop{w}\t$zero", []>, TB, OpSize16; 22 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 23 "nop{l}\t$zero", []>, TB, OpSize32; 24 def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), 25 "nop{q}\t$zero", []>, TB, Requires<[In64BitMode]>; 26 // Also allow register so we can assemble/disassemble 27 def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), 28 "nop{w}\t$zero", []>, TB, OpSize16; 29 def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), 30 "nop{l}\t$zero", []>, TB, OpSize32; 31 def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), 32 "nop{q}\t$zero", []>, TB, Requires<[In64BitMode]>; 33} 34 35 36// Constructing a stack frame. 37def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 38 "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; 39 40let SchedRW = [WriteALU] in { 41let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 42def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 43 Requires<[Not64BitMode]>; 44 45let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 46def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 47 Requires<[In64BitMode]>; 48} // SchedRW 49 50//===----------------------------------------------------------------------===// 51// Miscellaneous Instructions. 52// 53 54let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, 55 SchedRW = [WriteSystem] in 56 def Int_eh_sjlj_setup_dispatch 57 : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; 58 59let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 60let mayLoad = 1, SchedRW = [WriteLoad] in { 61def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 62 OpSize16; 63def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 64 OpSize32, Requires<[Not64BitMode]>; 65// Long form for the disassembler. 66let isCodeGenOnly = 1, ForceDisassemble = 1 in { 67def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 68 OpSize16; 69def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 70 OpSize32, Requires<[Not64BitMode]>; 71} // isCodeGenOnly = 1, ForceDisassemble = 1 72} // mayLoad, SchedRW 73let mayStore = 1, mayLoad = 1, SchedRW = [WriteCopy] in { 74def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, 75 OpSize16; 76def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, 77 OpSize32, Requires<[Not64BitMode]>; 78} // mayStore, mayLoad, SchedRW 79 80let mayStore = 1, SchedRW = [WriteStore] in { 81def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 82 OpSize16; 83def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 84 OpSize32, Requires<[Not64BitMode]>; 85// Long form for the disassembler. 86let isCodeGenOnly = 1, ForceDisassemble = 1 in { 87def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 88 OpSize16; 89def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 90 OpSize32, Requires<[Not64BitMode]>; 91} // isCodeGenOnly = 1, ForceDisassemble = 1 92 93def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 94 "push{w}\t$imm", []>, OpSize16; 95def PUSH16i : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 96 "push{w}\t$imm", []>, OpSize16; 97 98def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 99 "push{l}\t$imm", []>, OpSize32, 100 Requires<[Not64BitMode]>; 101def PUSH32i : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 102 "push{l}\t$imm", []>, OpSize32, 103 Requires<[Not64BitMode]>; 104} // mayStore, SchedRW 105 106let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { 107def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, 108 OpSize16; 109def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, 110 OpSize32, Requires<[Not64BitMode]>; 111} // mayLoad, mayStore, SchedRW 112 113} 114 115let isPseudo = 1, mayLoad = 1, mayStore = 1, 116 SchedRW = [WriteRMW], Defs = [ESP] in { 117 let Uses = [ESP] in 118 def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), 119 [(set GR32:$dst, (int_x86_flags_read_u32))]>, 120 Requires<[Not64BitMode]>; 121 122 let Uses = [RSP] in 123 def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), 124 [(set GR64:$dst, (int_x86_flags_read_u64))]>, 125 Requires<[In64BitMode]>; 126} 127 128let isPseudo = 1, mayLoad = 1, mayStore = 1, 129 SchedRW = [WriteRMW] in { 130 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in 131 def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), 132 [(int_x86_flags_write_u32 GR32:$src)]>, 133 Requires<[Not64BitMode]>; 134 135 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in 136 def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), 137 [(int_x86_flags_write_u64 GR64:$src)]>, 138 Requires<[In64BitMode]>; 139} 140 141let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 142 SchedRW = [WriteLoad] in { 143def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; 144def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, 145 Requires<[Not64BitMode]>; 146} 147 148let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, 149 SchedRW = [WriteStore] in { 150def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; 151def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, 152 Requires<[Not64BitMode]>; 153} 154 155let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 156let mayLoad = 1, SchedRW = [WriteLoad] in { 157def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 158 OpSize32, Requires<[In64BitMode]>; 159// Long form for the disassembler. 160let isCodeGenOnly = 1, ForceDisassemble = 1 in { 161def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 162 OpSize32, Requires<[In64BitMode]>; 163} // isCodeGenOnly = 1, ForceDisassemble = 1 164} // mayLoad, SchedRW 165let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in 166def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, 167 OpSize32, Requires<[In64BitMode]>; 168let mayStore = 1, SchedRW = [WriteStore] in { 169def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 170 OpSize32, Requires<[In64BitMode]>; 171// Long form for the disassembler. 172let isCodeGenOnly = 1, ForceDisassemble = 1 in { 173def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 174 OpSize32, Requires<[In64BitMode]>; 175} // isCodeGenOnly = 1, ForceDisassemble = 1 176} // mayStore, SchedRW 177let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { 178def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, 179 OpSize32, Requires<[In64BitMode]>; 180} // mayLoad, mayStore, SchedRW 181} 182 183let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 184 SchedRW = [WriteStore] in { 185def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 186 "push{q}\t$imm", []>, OpSize32, 187 Requires<[In64BitMode]>; 188def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 189 "push{q}\t$imm", []>, OpSize32, 190 Requires<[In64BitMode]>; 191} 192 193let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 194def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, 195 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 196let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in 197def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, 198 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 199 200let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 201 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 202def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, 203 OpSize32, Requires<[Not64BitMode]>; 204def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, 205 OpSize16, Requires<[Not64BitMode]>; 206} 207let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 208 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 209def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, 210 OpSize32, Requires<[Not64BitMode]>; 211def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, 212 OpSize16, Requires<[Not64BitMode]>; 213} 214 215let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { 216// This instruction is a consequence of BSWAP32r observing operand size. The 217// encoding is valid, but the behavior is undefined. 218let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 219def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 220 "bswap{w}\t$dst", []>, OpSize16, TB; 221// GR32 = bswap GR32 222def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 223 "bswap{l}\t$dst", 224 [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; 225 226let SchedRW = [WriteBSWAP64] in 227def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 228 "bswap{q}\t$dst", 229 [(set GR64:$dst, (bswap GR64:$src))]>, TB; 230} // Constraints = "$src = $dst", SchedRW 231 232// Bit scan instructions. 233let Defs = [EFLAGS] in { 234def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 235 "bsf{w}\t{$src, $dst|$dst, $src}", 236 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, 237 PS, OpSize16, Sched<[WriteBSF]>; 238def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 239 "bsf{w}\t{$src, $dst|$dst, $src}", 240 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, 241 PS, OpSize16, Sched<[WriteBSFLd]>; 242def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 243 "bsf{l}\t{$src, $dst|$dst, $src}", 244 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, 245 PS, OpSize32, Sched<[WriteBSF]>; 246def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 247 "bsf{l}\t{$src, $dst|$dst, $src}", 248 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, 249 PS, OpSize32, Sched<[WriteBSFLd]>; 250def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 251 "bsf{q}\t{$src, $dst|$dst, $src}", 252 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, 253 PS, Sched<[WriteBSF]>; 254def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 255 "bsf{q}\t{$src, $dst|$dst, $src}", 256 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, 257 PS, Sched<[WriteBSFLd]>; 258 259def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 260 "bsr{w}\t{$src, $dst|$dst, $src}", 261 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, 262 PS, OpSize16, Sched<[WriteBSR]>; 263def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 264 "bsr{w}\t{$src, $dst|$dst, $src}", 265 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, 266 PS, OpSize16, Sched<[WriteBSRLd]>; 267def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 268 "bsr{l}\t{$src, $dst|$dst, $src}", 269 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, 270 PS, OpSize32, Sched<[WriteBSR]>; 271def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 272 "bsr{l}\t{$src, $dst|$dst, $src}", 273 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, 274 PS, OpSize32, Sched<[WriteBSRLd]>; 275def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 276 "bsr{q}\t{$src, $dst|$dst, $src}", 277 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, 278 PS, Sched<[WriteBSR]>; 279def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 280 "bsr{q}\t{$src, $dst|$dst, $src}", 281 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, 282 PS, Sched<[WriteBSRLd]>; 283} // Defs = [EFLAGS] 284 285let SchedRW = [WriteMicrocoded] in { 286let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { 287def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 288 "movsb\t{$src, $dst|$dst, $src}", []>; 289def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 290 "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; 291def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 292 "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; 293def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 294 "movsq\t{$src, $dst|$dst, $src}", []>, 295 Requires<[In64BitMode]>; 296} 297 298let Defs = [EDI], Uses = [AL,EDI,DF] in 299def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), 300 "stosb\t{%al, $dst|$dst, al}", []>; 301let Defs = [EDI], Uses = [AX,EDI,DF] in 302def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), 303 "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; 304let Defs = [EDI], Uses = [EAX,EDI,DF] in 305def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), 306 "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; 307let Defs = [RDI], Uses = [RAX,RDI,DF] in 308def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), 309 "stosq\t{%rax, $dst|$dst, rax}", []>, 310 Requires<[In64BitMode]>; 311 312let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in 313def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 314 "scasb\t{$dst, %al|al, $dst}", []>; 315let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in 316def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 317 "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; 318let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in 319def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 320 "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; 321let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in 322def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 323 "scasq\t{$dst, %rax|rax, $dst}", []>, 324 Requires<[In64BitMode]>; 325 326let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { 327def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 328 "cmpsb\t{$dst, $src|$src, $dst}", []>; 329def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 330 "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; 331def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 332 "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; 333def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 334 "cmpsq\t{$dst, $src|$src, $dst}", []>, 335 Requires<[In64BitMode]>; 336} 337} // SchedRW 338 339//===----------------------------------------------------------------------===// 340// Move Instructions. 341// 342let SchedRW = [WriteMove] in { 343let hasSideEffects = 0, isMoveReg = 1 in { 344def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 345 "mov{b}\t{$src, $dst|$dst, $src}", []>; 346def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 347 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 348def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 349 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 350def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 351 "mov{q}\t{$src, $dst|$dst, $src}", []>; 352} 353 354let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 355def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 356 "mov{b}\t{$src, $dst|$dst, $src}", 357 [(set GR8:$dst, imm:$src)]>; 358def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 359 "mov{w}\t{$src, $dst|$dst, $src}", 360 [(set GR16:$dst, imm:$src)]>, OpSize16; 361def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 362 "mov{l}\t{$src, $dst|$dst, $src}", 363 [(set GR32:$dst, imm:$src)]>, OpSize32; 364def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 365 "mov{q}\t{$src, $dst|$dst, $src}", 366 [(set GR64:$dst, i64immSExt32:$src)]>; 367} 368let isReMaterializable = 1, isMoveImm = 1 in { 369def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 370 "movabs{q}\t{$src, $dst|$dst, $src}", 371 [(set GR64:$dst, imm:$src)]>; 372} 373 374// Longer forms that use a ModR/M byte. Needed for disassembler 375let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 376def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 377 "mov{b}\t{$src, $dst|$dst, $src}", []>; 378def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 379 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 380def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 381 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 382} 383} // SchedRW 384 385let SchedRW = [WriteStore] in { 386def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 387 "mov{b}\t{$src, $dst|$dst, $src}", 388 [(store (i8 imm_su:$src), addr:$dst)]>; 389def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 390 "mov{w}\t{$src, $dst|$dst, $src}", 391 [(store (i16 imm_su:$src), addr:$dst)]>, OpSize16; 392def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 393 "mov{l}\t{$src, $dst|$dst, $src}", 394 [(store (i32 imm_su:$src), addr:$dst)]>, OpSize32; 395def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 396 "mov{q}\t{$src, $dst|$dst, $src}", 397 [(store i64immSExt32_su:$src, addr:$dst)]>, 398 Requires<[In64BitMode]>; 399} // SchedRW 400 401def : Pat<(i32 relocImm:$src), (MOV32ri relocImm:$src)>; 402def : Pat<(i64 relocImm:$src), (MOV64ri relocImm:$src)>; 403 404def : Pat<(store (i8 relocImm8_su:$src), addr:$dst), 405 (MOV8mi addr:$dst, relocImm8_su:$src)>; 406def : Pat<(store (i16 relocImm16_su:$src), addr:$dst), 407 (MOV16mi addr:$dst, relocImm16_su:$src)>; 408def : Pat<(store (i32 relocImm32_su:$src), addr:$dst), 409 (MOV32mi addr:$dst, relocImm32_su:$src)>; 410def : Pat<(store (i64 i64relocImmSExt32_su:$src), addr:$dst), 411 (MOV64mi32 addr:$dst, i64immSExt32_su:$src)>; 412 413let hasSideEffects = 0 in { 414 415/// Memory offset versions of moves. The immediate is an address mode sized 416/// offset from the segment base. 417let SchedRW = [WriteALU] in { 418let mayLoad = 1 in { 419let Defs = [AL] in 420def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 421 "mov{b}\t{$src, %al|al, $src}", []>, 422 AdSize32; 423let Defs = [AX] in 424def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 425 "mov{w}\t{$src, %ax|ax, $src}", []>, 426 OpSize16, AdSize32; 427let Defs = [EAX] in 428def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 429 "mov{l}\t{$src, %eax|eax, $src}", []>, 430 OpSize32, AdSize32; 431let Defs = [RAX] in 432def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 433 "mov{q}\t{$src, %rax|rax, $src}", []>, 434 AdSize32; 435 436let Defs = [AL] in 437def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 438 "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; 439let Defs = [AX] in 440def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 441 "mov{w}\t{$src, %ax|ax, $src}", []>, 442 OpSize16, AdSize16; 443let Defs = [EAX] in 444def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 445 "mov{l}\t{$src, %eax|eax, $src}", []>, 446 AdSize16, OpSize32; 447} // mayLoad 448let mayStore = 1 in { 449let Uses = [AL] in 450def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), 451 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; 452let Uses = [AX] in 453def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), 454 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 455 OpSize16, AdSize32; 456let Uses = [EAX] in 457def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), 458 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 459 OpSize32, AdSize32; 460let Uses = [RAX] in 461def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), 462 "mov{q}\t{%rax, $dst|$dst, rax}", []>, 463 AdSize32; 464 465let Uses = [AL] in 466def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), 467 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; 468let Uses = [AX] in 469def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), 470 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 471 OpSize16, AdSize16; 472let Uses = [EAX] in 473def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), 474 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 475 OpSize32, AdSize16; 476} // mayStore 477 478// These forms all have full 64-bit absolute addresses in their instructions 479// and use the movabs mnemonic to indicate this specific form. 480let mayLoad = 1 in { 481let Defs = [AL] in 482def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 483 "movabs{b}\t{$src, %al|al, $src}", []>, 484 AdSize64; 485let Defs = [AX] in 486def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 487 "movabs{w}\t{$src, %ax|ax, $src}", []>, 488 OpSize16, AdSize64; 489let Defs = [EAX] in 490def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 491 "movabs{l}\t{$src, %eax|eax, $src}", []>, 492 OpSize32, AdSize64; 493let Defs = [RAX] in 494def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 495 "movabs{q}\t{$src, %rax|rax, $src}", []>, 496 AdSize64; 497} // mayLoad 498 499let mayStore = 1 in { 500let Uses = [AL] in 501def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), 502 "movabs{b}\t{%al, $dst|$dst, al}", []>, 503 AdSize64; 504let Uses = [AX] in 505def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), 506 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, 507 OpSize16, AdSize64; 508let Uses = [EAX] in 509def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), 510 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, 511 OpSize32, AdSize64; 512let Uses = [RAX] in 513def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), 514 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 515 AdSize64; 516} // mayStore 517} // SchedRW 518} // hasSideEffects = 0 519 520let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 521 SchedRW = [WriteMove], isMoveReg = 1 in { 522def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 523 "mov{b}\t{$src, $dst|$dst, $src}", []>; 524def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 525 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 526def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 527 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 528def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 529 "mov{q}\t{$src, $dst|$dst, $src}", []>; 530} 531 532let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 533def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 534 "mov{b}\t{$src, $dst|$dst, $src}", 535 [(set GR8:$dst, (loadi8 addr:$src))]>; 536def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 537 "mov{w}\t{$src, $dst|$dst, $src}", 538 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; 539def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 540 "mov{l}\t{$src, $dst|$dst, $src}", 541 [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; 542def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 543 "mov{q}\t{$src, $dst|$dst, $src}", 544 [(set GR64:$dst, (load addr:$src))]>; 545} 546 547let SchedRW = [WriteStore] in { 548def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 549 "mov{b}\t{$src, $dst|$dst, $src}", 550 [(store GR8:$src, addr:$dst)]>; 551def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 552 "mov{w}\t{$src, $dst|$dst, $src}", 553 [(store GR16:$src, addr:$dst)]>, OpSize16; 554def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 555 "mov{l}\t{$src, $dst|$dst, $src}", 556 [(store GR32:$src, addr:$dst)]>, OpSize32; 557def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 558 "mov{q}\t{$src, $dst|$dst, $src}", 559 [(store GR64:$src, addr:$dst)]>; 560} // SchedRW 561 562// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 563// that they can be used for copying and storing h registers, which can't be 564// encoded when a REX prefix is present. 565let isCodeGenOnly = 1 in { 566let hasSideEffects = 0, isMoveReg = 1 in 567def MOV8rr_NOREX : I<0x88, MRMDestReg, 568 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 569 "mov{b}\t{$src, $dst|$dst, $src}", []>, 570 Sched<[WriteMove]>; 571let mayStore = 1, hasSideEffects = 0 in 572def MOV8mr_NOREX : I<0x88, MRMDestMem, 573 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 574 "mov{b}\t{$src, $dst|$dst, $src}", []>, 575 Sched<[WriteStore]>; 576let mayLoad = 1, hasSideEffects = 0, 577 canFoldAsLoad = 1, isReMaterializable = 1 in 578def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 579 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 580 "mov{b}\t{$src, $dst|$dst, $src}", []>, 581 Sched<[WriteLoad]>; 582} 583 584 585// Condition code ops, incl. set if equal/not equal/... 586let SchedRW = [WriteLAHFSAHF] in { 587let Defs = [EFLAGS], Uses = [AH], hasSideEffects = 0 in 588def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, // flags = AH 589 Requires<[HasLAHFSAHF]>; 590let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 591def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags 592 Requires<[HasLAHFSAHF]>; 593} // SchedRW 594 595//===----------------------------------------------------------------------===// 596// Bit tests instructions: BT, BTS, BTR, BTC. 597 598let Defs = [EFLAGS] in { 599let SchedRW = [WriteBitTest] in { 600def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 601 "bt{w}\t{$src2, $src1|$src1, $src2}", 602 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, 603 OpSize16, TB; 604def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 605 "bt{l}\t{$src2, $src1|$src1, $src2}", 606 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, 607 OpSize32, TB; 608def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 609 "bt{q}\t{$src2, $src1|$src1, $src2}", 610 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB; 611} // SchedRW 612 613// Unlike with the register+register form, the memory+register form of the 614// bt instruction does not ignore the high bits of the index. From ISel's 615// perspective, this is pretty bizarre. Make these instructions disassembly 616// only for now. These instructions are also slow on modern CPUs so that's 617// another reason to avoid generating them. 618 619let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteBitTestRegLd] in { 620 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 621 "bt{w}\t{$src2, $src1|$src1, $src2}", 622 []>, OpSize16, TB; 623 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 624 "bt{l}\t{$src2, $src1|$src1, $src2}", 625 []>, OpSize32, TB; 626 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 627 "bt{q}\t{$src2, $src1|$src1, $src2}", 628 []>, TB; 629} 630 631let SchedRW = [WriteBitTest] in { 632def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16u8imm:$src2), 633 "bt{w}\t{$src2, $src1|$src1, $src2}", 634 [(set EFLAGS, (X86bt GR16:$src1, imm:$src2))]>, 635 OpSize16, TB; 636def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32u8imm:$src2), 637 "bt{l}\t{$src2, $src1|$src1, $src2}", 638 [(set EFLAGS, (X86bt GR32:$src1, imm:$src2))]>, 639 OpSize32, TB; 640def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64u8imm:$src2), 641 "bt{q}\t{$src2, $src1|$src1, $src2}", 642 [(set EFLAGS, (X86bt GR64:$src1, imm:$src2))]>, TB; 643} // SchedRW 644 645// Note that these instructions aren't slow because that only applies when the 646// other operand is in a register. When it's an immediate, bt is still fast. 647let SchedRW = [WriteBitTestImmLd] in { 648def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 649 "bt{w}\t{$src2, $src1|$src1, $src2}", 650 [(set EFLAGS, (X86bt (loadi16 addr:$src1), 651 imm:$src2))]>, 652 OpSize16, TB; 653def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 654 "bt{l}\t{$src2, $src1|$src1, $src2}", 655 [(set EFLAGS, (X86bt (loadi32 addr:$src1), 656 imm:$src2))]>, 657 OpSize32, TB; 658def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 659 "bt{q}\t{$src2, $src1|$src1, $src2}", 660 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 661 imm:$src2))]>, TB, 662 Requires<[In64BitMode]>; 663} // SchedRW 664 665let hasSideEffects = 0 in { 666let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 667def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 668 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 669 OpSize16, TB; 670def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 671 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 672 OpSize32, TB; 673def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 674 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 675} // SchedRW 676 677let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 678def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 679 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 680 OpSize16, TB; 681def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 682 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 683 OpSize32, TB; 684def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 685 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 686} 687 688let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 689def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 690 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 691def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 692 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 693def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 694 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 695} // SchedRW 696 697let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 698def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 699 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 700def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 701 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 702def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 703 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 704 Requires<[In64BitMode]>; 705} 706 707let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 708def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 709 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 710 OpSize16, TB; 711def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 712 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 713 OpSize32, TB; 714def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 715 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 716} // SchedRW 717 718let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 719def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 720 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 721 OpSize16, TB; 722def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 723 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 724 OpSize32, TB; 725def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 726 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 727} 728 729let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 730def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 731 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 732 OpSize16, TB; 733def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 734 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 735 OpSize32, TB; 736def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 737 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 738} // SchedRW 739 740let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 741def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 742 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 743 OpSize16, TB; 744def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 745 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 746 OpSize32, TB; 747def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 748 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 749 Requires<[In64BitMode]>; 750} 751 752let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 753def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 754 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 755 OpSize16, TB; 756def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 757 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 758 OpSize32, TB; 759def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 760 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 761} // SchedRW 762 763let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 764def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 765 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 766 OpSize16, TB; 767def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 768 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 769 OpSize32, TB; 770def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 771 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 772} 773 774let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 775def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 776 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 777def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 778 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 779def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 780 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 781} // SchedRW 782 783let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 784def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 785 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 786def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 787 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 788def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 789 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 790 Requires<[In64BitMode]>; 791} 792} // hasSideEffects = 0 793} // Defs = [EFLAGS] 794 795 796//===----------------------------------------------------------------------===// 797// Atomic support 798// 799 800// Atomic swap. These are just normal xchg instructions. But since a memory 801// operand is referenced, the atomicity is ensured. 802multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag> { 803 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 804 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 805 (ins GR8:$val, i8mem:$ptr), 806 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 807 [(set 808 GR8:$dst, 809 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 810 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 811 (ins GR16:$val, i16mem:$ptr), 812 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 813 [(set 814 GR16:$dst, 815 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 816 OpSize16; 817 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 818 (ins GR32:$val, i32mem:$ptr), 819 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 820 [(set 821 GR32:$dst, 822 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 823 OpSize32; 824 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 825 (ins GR64:$val, i64mem:$ptr), 826 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 827 [(set 828 GR64:$dst, 829 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 830 } 831} 832 833defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">; 834 835// Swap between registers. 836let SchedRW = [WriteXCHG] in { 837let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { 838def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), 839 (ins GR8:$src1, GR8:$src2), 840 "xchg{b}\t{$src2, $src1|$src1, $src2}", []>; 841def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), 842 (ins GR16:$src1, GR16:$src2), 843 "xchg{w}\t{$src2, $src1|$src1, $src2}", []>, 844 OpSize16; 845def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), 846 (ins GR32:$src1, GR32:$src2), 847 "xchg{l}\t{$src2, $src1|$src1, $src2}", []>, 848 OpSize32; 849def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), 850 (ins GR64:$src1 ,GR64:$src2), 851 "xchg{q}\t{$src2, $src1|$src1, $src2}", []>; 852} 853 854// Swap between EAX and other registers. 855let Constraints = "$src = $dst", hasSideEffects = 0 in { 856let Uses = [AX], Defs = [AX] in 857def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 858 "xchg{w}\t{$src, %ax|ax, $src}", []>, OpSize16; 859let Uses = [EAX], Defs = [EAX] in 860def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 861 "xchg{l}\t{$src, %eax|eax, $src}", []>, OpSize32; 862let Uses = [RAX], Defs = [RAX] in 863def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 864 "xchg{q}\t{$src, %rax|rax, $src}", []>; 865} 866} // SchedRW 867 868let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", 869 Defs = [EFLAGS], SchedRW = [WriteXCHG] in { 870def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), 871 (ins GR8:$src1, GR8:$src2), 872 "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; 873def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), 874 (ins GR16:$src1, GR16:$src2), 875 "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; 876def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), 877 (ins GR32:$src1, GR32:$src2), 878 "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; 879def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), 880 (ins GR64:$src1, GR64:$src2), 881 "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 882} // SchedRW 883 884let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", 885 Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { 886def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), 887 (ins GR8:$val, i8mem:$ptr), 888 "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; 889def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), 890 (ins GR16:$val, i16mem:$ptr), 891 "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, 892 OpSize16; 893def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), 894 (ins GR32:$val, i32mem:$ptr), 895 "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, 896 OpSize32; 897def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), 898 (ins GR64:$val, i64mem:$ptr), 899 "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; 900 901} 902 903let SchedRW = [WriteCMPXCHG], hasSideEffects = 0 in { 904let Defs = [AL, EFLAGS], Uses = [AL] in 905def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 906 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; 907let Defs = [AX, EFLAGS], Uses = [AX] in 908def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 909 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 910let Defs = [EAX, EFLAGS], Uses = [EAX] in 911def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 912 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 913let Defs = [RAX, EFLAGS], Uses = [RAX] in 914def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 915 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; 916} // SchedRW, hasSideEffects 917 918let SchedRW = [WriteCMPXCHGRMW], mayLoad = 1, mayStore = 1, 919 hasSideEffects = 0 in { 920let Defs = [AL, EFLAGS], Uses = [AL] in 921def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 922 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; 923let Defs = [AX, EFLAGS], Uses = [AX] in 924def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 925 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 926let Defs = [EAX, EFLAGS], Uses = [EAX] in 927def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 928 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 929let Defs = [RAX, EFLAGS], Uses = [RAX] in 930def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 931 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; 932 933let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 934def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 935 "cmpxchg8b\t$dst", []>, TB, Requires<[HasCX8]>; 936 937let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 938// NOTE: In64BitMode check needed for the AssemblerPredicate. 939def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 940 "cmpxchg16b\t$dst", []>, 941 TB, Requires<[HasCX16,In64BitMode]>; 942} // SchedRW, mayLoad, mayStore, hasSideEffects 943 944 945// Lock instruction prefix 946let SchedRW = [WriteMicrocoded] in 947def LOCK_PREFIX : I<0xF0, PrefixByte, (outs), (ins), "lock", []>; 948 949let SchedRW = [WriteNop] in { 950 951// Rex64 instruction prefix 952def REX64_PREFIX : I<0x48, PrefixByte, (outs), (ins), "rex64", []>, 953 Requires<[In64BitMode]>; 954 955// Data16 instruction prefix 956def DATA16_PREFIX : I<0x66, PrefixByte, (outs), (ins), "data16", []>; 957} // SchedRW 958 959// Repeat string operation instruction prefixes 960let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { 961// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 962def REP_PREFIX : I<0xF3, PrefixByte, (outs), (ins), "rep", []>; 963// Repeat while not equal (used with CMPS and SCAS) 964def REPNE_PREFIX : I<0xF2, PrefixByte, (outs), (ins), "repne", []>; 965} 966 967// String manipulation instructions 968let SchedRW = [WriteMicrocoded] in { 969let Defs = [AL,ESI], Uses = [ESI,DF] in 970def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 971 "lodsb\t{$src, %al|al, $src}", []>; 972let Defs = [AX,ESI], Uses = [ESI,DF] in 973def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 974 "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; 975let Defs = [EAX,ESI], Uses = [ESI,DF] in 976def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 977 "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; 978let Defs = [RAX,ESI], Uses = [ESI,DF] in 979def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 980 "lodsq\t{$src, %rax|rax, $src}", []>, 981 Requires<[In64BitMode]>; 982} 983 984let SchedRW = [WriteSystem] in { 985let Defs = [ESI], Uses = [DX,ESI,DF] in { 986def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 987 "outsb\t{$src, %dx|dx, $src}", []>; 988def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 989 "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; 990def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 991 "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; 992} 993 994let Defs = [EDI], Uses = [DX,EDI,DF] in { 995def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), 996 "insb\t{%dx, $dst|$dst, dx}", []>; 997def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), 998 "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; 999def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), 1000 "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; 1001} 1002} 1003 1004// EFLAGS management instructions. 1005let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { 1006def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; 1007def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; 1008def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; 1009} 1010 1011// DF management instructions. 1012let SchedRW = [WriteALU], Defs = [DF] in { 1013def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; 1014def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; 1015} 1016 1017// Table lookup instructions 1018let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in 1019def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; 1020 1021let SchedRW = [WriteMicrocoded] in { 1022// ASCII Adjust After Addition 1023let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 1024def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, 1025 Requires<[Not64BitMode]>; 1026 1027// ASCII Adjust AX Before Division 1028let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in 1029def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1030 "aad\t$src", []>, Requires<[Not64BitMode]>; 1031 1032// ASCII Adjust AX After Multiply 1033let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in 1034def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1035 "aam\t$src", []>, Requires<[Not64BitMode]>; 1036 1037// ASCII Adjust AL After Subtraction - sets 1038let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 1039def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, 1040 Requires<[Not64BitMode]>; 1041 1042// Decimal Adjust AL after Addition 1043let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 1044def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, 1045 Requires<[Not64BitMode]>; 1046 1047// Decimal Adjust AL after Subtraction 1048let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 1049def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, 1050 Requires<[Not64BitMode]>; 1051} // SchedRW 1052 1053let SchedRW = [WriteSystem] in { 1054// Check Array Index Against Bounds 1055// Note: "bound" does not have reversed operands in at&t syntax. 1056def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1057 "bound\t$dst, $src", []>, OpSize16, 1058 Requires<[Not64BitMode]>; 1059def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1060 "bound\t$dst, $src", []>, OpSize32, 1061 Requires<[Not64BitMode]>; 1062 1063// Adjust RPL Field of Segment Selector 1064def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1065 "arpl\t{$src, $dst|$dst, $src}", []>, 1066 Requires<[Not64BitMode]>; 1067let mayStore = 1 in 1068def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1069 "arpl\t{$src, $dst|$dst, $src}", []>, 1070 Requires<[Not64BitMode]>; 1071} // SchedRW 1072 1073//===----------------------------------------------------------------------===// 1074// MOVBE Instructions 1075// 1076let Predicates = [HasMOVBE] in { 1077 let SchedRW = [WriteALULd] in { 1078 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1079 "movbe{w}\t{$src, $dst|$dst, $src}", 1080 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, 1081 OpSize16, T8PS; 1082 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1083 "movbe{l}\t{$src, $dst|$dst, $src}", 1084 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, 1085 OpSize32, T8PS; 1086 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1087 "movbe{q}\t{$src, $dst|$dst, $src}", 1088 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, 1089 T8PS; 1090 } 1091 let SchedRW = [WriteStore] in { 1092 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1093 "movbe{w}\t{$src, $dst|$dst, $src}", 1094 [(store (bswap GR16:$src), addr:$dst)]>, 1095 OpSize16, T8PS; 1096 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1097 "movbe{l}\t{$src, $dst|$dst, $src}", 1098 [(store (bswap GR32:$src), addr:$dst)]>, 1099 OpSize32, T8PS; 1100 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1101 "movbe{q}\t{$src, $dst|$dst, $src}", 1102 [(store (bswap GR64:$src), addr:$dst)]>, 1103 T8PS; 1104 } 1105} 1106 1107//===----------------------------------------------------------------------===// 1108// RDRAND Instruction 1109// 1110let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 1111 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1112 "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, 1113 OpSize16, PS; 1114 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1115 "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, 1116 OpSize32, PS; 1117 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1118 "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, 1119 PS; 1120} 1121 1122//===----------------------------------------------------------------------===// 1123// RDSEED Instruction 1124// 1125let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 1126 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", 1127 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; 1128 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", 1129 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; 1130 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", 1131 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; 1132} 1133 1134//===----------------------------------------------------------------------===// 1135// LZCNT Instruction 1136// 1137let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 1138 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1139 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1140 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, 1141 XS, OpSize16, Sched<[WriteLZCNT]>; 1142 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1143 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1144 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 1145 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; 1146 1147 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1148 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1149 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, 1150 XS, OpSize32, Sched<[WriteLZCNT]>; 1151 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1152 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1153 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 1154 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; 1155 1156 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1157 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1158 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 1159 XS, Sched<[WriteLZCNT]>; 1160 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1161 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1162 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 1163 (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; 1164} 1165 1166//===----------------------------------------------------------------------===// 1167// BMI Instructions 1168// 1169let Predicates = [HasBMI], Defs = [EFLAGS] in { 1170 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1171 "tzcnt{w}\t{$src, $dst|$dst, $src}", 1172 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, 1173 XS, OpSize16, Sched<[WriteTZCNT]>; 1174 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1175 "tzcnt{w}\t{$src, $dst|$dst, $src}", 1176 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 1177 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; 1178 1179 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1180 "tzcnt{l}\t{$src, $dst|$dst, $src}", 1181 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, 1182 XS, OpSize32, Sched<[WriteTZCNT]>; 1183 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1184 "tzcnt{l}\t{$src, $dst|$dst, $src}", 1185 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 1186 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; 1187 1188 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1189 "tzcnt{q}\t{$src, $dst|$dst, $src}", 1190 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 1191 XS, Sched<[WriteTZCNT]>; 1192 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1193 "tzcnt{q}\t{$src, $dst|$dst, $src}", 1194 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 1195 (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; 1196} 1197 1198multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 1199 RegisterClass RC, X86MemOperand x86memop, 1200 X86FoldableSchedWrite sched> { 1201let hasSideEffects = 0 in { 1202 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 1203 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 1204 T8PS, VEX_4V, Sched<[sched]>; 1205 let mayLoad = 1 in 1206 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 1207 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 1208 T8PS, VEX_4V, Sched<[sched.Folded]>; 1209} 1210} 1211 1212let Predicates = [HasBMI], Defs = [EFLAGS] in { 1213 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>; 1214 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, REX_W; 1215 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>; 1216 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, REX_W; 1217 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS>; 1218 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, REX_W; 1219} 1220 1221//===----------------------------------------------------------------------===// 1222// Pattern fragments to auto generate BMI instructions. 1223//===----------------------------------------------------------------------===// 1224 1225def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 1226 (X86or_flag node:$lhs, node:$rhs), [{ 1227 return hasNoCarryFlagUses(SDValue(N, 1)); 1228}]>; 1229 1230def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 1231 (X86xor_flag node:$lhs, node:$rhs), [{ 1232 return hasNoCarryFlagUses(SDValue(N, 1)); 1233}]>; 1234 1235def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 1236 (X86and_flag node:$lhs, node:$rhs), [{ 1237 return hasNoCarryFlagUses(SDValue(N, 1)); 1238}]>; 1239 1240 1241let Predicates = [HasBMI] in { 1242 // FIXME(1): patterns for the load versions are not implemented 1243 // FIXME(2): By only matching `add_su` and `ineg_su` we may emit 1244 // extra `mov` instructions if `src` has future uses. It may be better 1245 // to always match if `src` has more users. 1246 def : Pat<(and GR32:$src, (add_su GR32:$src, -1)), 1247 (BLSR32rr GR32:$src)>; 1248 def : Pat<(and GR64:$src, (add_su GR64:$src, -1)), 1249 (BLSR64rr GR64:$src)>; 1250 1251 def : Pat<(xor GR32:$src, (add_su GR32:$src, -1)), 1252 (BLSMSK32rr GR32:$src)>; 1253 def : Pat<(xor GR64:$src, (add_su GR64:$src, -1)), 1254 (BLSMSK64rr GR64:$src)>; 1255 1256 def : Pat<(and GR32:$src, (ineg_su GR32:$src)), 1257 (BLSI32rr GR32:$src)>; 1258 def : Pat<(and GR64:$src, (ineg_su GR64:$src)), 1259 (BLSI64rr GR64:$src)>; 1260 1261 // Versions to match flag producing ops. 1262 def : Pat<(and_flag_nocf GR32:$src, (add_su GR32:$src, -1)), 1263 (BLSR32rr GR32:$src)>; 1264 def : Pat<(and_flag_nocf GR64:$src, (add_su GR64:$src, -1)), 1265 (BLSR64rr GR64:$src)>; 1266 1267 def : Pat<(xor_flag_nocf GR32:$src, (add_su GR32:$src, -1)), 1268 (BLSMSK32rr GR32:$src)>; 1269 def : Pat<(xor_flag_nocf GR64:$src, (add_su GR64:$src, -1)), 1270 (BLSMSK64rr GR64:$src)>; 1271 1272 def : Pat<(and_flag_nocf GR32:$src, (ineg_su GR32:$src)), 1273 (BLSI32rr GR32:$src)>; 1274 def : Pat<(and_flag_nocf GR64:$src, (ineg_su GR64:$src)), 1275 (BLSI64rr GR64:$src)>; 1276} 1277 1278multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC, 1279 X86MemOperand x86memop, SDNode OpNode, 1280 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 1281 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1282 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1283 [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 1284 T8PS, VEX, Sched<[Sched]>; 1285 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 1286 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1287 [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)), 1288 (implicit EFLAGS)]>, T8PS, VEX, 1289 Sched<[Sched.Folded, 1290 // x86memop:$src1 1291 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 1292 ReadDefault, 1293 // RC:$src2 1294 Sched.ReadAfterFold]>; 1295} 1296 1297let Predicates = [HasBMI], Defs = [EFLAGS] in { 1298 defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, 1299 X86bextr, loadi32, WriteBEXTR>; 1300 defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, 1301 X86bextr, loadi64, WriteBEXTR>, REX_W; 1302} 1303 1304multiclass bmi_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 1305 X86MemOperand x86memop, SDNode Int, 1306 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 1307 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1308 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1309 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 1310 T8PS, VEX, Sched<[Sched]>; 1311 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 1312 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1313 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 1314 (implicit EFLAGS)]>, T8PS, VEX, 1315 Sched<[Sched.Folded, 1316 // x86memop:$src1 1317 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 1318 ReadDefault, 1319 // RC:$src2 1320 Sched.ReadAfterFold]>; 1321} 1322 1323let Predicates = [HasBMI2], Defs = [EFLAGS] in { 1324 defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 1325 X86bzhi, loadi32, WriteBZHI>; 1326 defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 1327 X86bzhi, loadi64, WriteBZHI>, REX_W; 1328} 1329 1330def CountTrailingOnes : SDNodeXForm<imm, [{ 1331 // Count the trailing ones in the immediate. 1332 return getI8Imm(llvm::countr_one(N->getZExtValue()), SDLoc(N)); 1333}]>; 1334 1335def BEXTRMaskXForm : SDNodeXForm<imm, [{ 1336 unsigned Length = llvm::countr_one(N->getZExtValue()); 1337 return getI32Imm(Length << 8, SDLoc(N)); 1338}]>; 1339 1340def AndMask64 : ImmLeaf<i64, [{ 1341 return isMask_64(Imm) && !isUInt<32>(Imm); 1342}]>; 1343 1344// Use BEXTR for 64-bit 'and' with large immediate 'mask'. 1345let Predicates = [HasBMI, NoBMI2, NoTBM] in { 1346 def : Pat<(and GR64:$src, AndMask64:$mask), 1347 (BEXTR64rr GR64:$src, 1348 (SUBREG_TO_REG (i64 0), 1349 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 1350 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 1351 (BEXTR64rm addr:$src, 1352 (SUBREG_TO_REG (i64 0), 1353 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 1354} 1355 1356// Use BZHI for 64-bit 'and' with large immediate 'mask'. 1357let Predicates = [HasBMI2, NoTBM] in { 1358 def : Pat<(and GR64:$src, AndMask64:$mask), 1359 (BZHI64rr GR64:$src, 1360 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1361 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 1362 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 1363 (BZHI64rm addr:$src, 1364 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1365 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 1366} 1367 1368multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 1369 X86MemOperand x86memop, SDNode OpNode, 1370 PatFrag ld_frag> { 1371 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1372 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1373 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>, 1374 VEX_4V, Sched<[WriteALU]>; 1375 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 1376 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1377 [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>, 1378 VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>; 1379} 1380 1381let Predicates = [HasBMI2] in { 1382 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 1383 X86pdep, loadi32>, T8XD; 1384 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 1385 X86pdep, loadi64>, T8XD, REX_W; 1386 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 1387 X86pext, loadi32>, T8XS; 1388 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 1389 X86pext, loadi64>, T8XS, REX_W; 1390} 1391 1392//===----------------------------------------------------------------------===// 1393// Lightweight Profiling Instructions 1394 1395let Predicates = [HasLWP], SchedRW = [WriteSystem] in { 1396 1397def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", 1398 [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; 1399def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", 1400 [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; 1401 1402def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", 1403 [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, REX_W; 1404def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", 1405 [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, REX_W; 1406 1407multiclass lwpins_intr<RegisterClass RC> { 1408 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 1409 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 1410 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>, 1411 XOP_4V, XOPA; 1412 let mayLoad = 1 in 1413 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 1414 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 1415 [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), timm:$cntl))]>, 1416 XOP_4V, XOPA; 1417} 1418 1419let Defs = [EFLAGS] in { 1420 defm LWPINS32 : lwpins_intr<GR32>; 1421 defm LWPINS64 : lwpins_intr<GR64>, REX_W; 1422} // EFLAGS 1423 1424multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> { 1425 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 1426 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 1427 [(Int RC:$src0, GR32:$src1, timm:$cntl)]>, XOP_4V, XOPA; 1428 let mayLoad = 1 in 1429 def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 1430 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 1431 [(Int RC:$src0, (loadi32 addr:$src1), timm:$cntl)]>, 1432 XOP_4V, XOPA; 1433} 1434 1435defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>; 1436defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, REX_W; 1437 1438} // HasLWP, SchedRW 1439 1440//===----------------------------------------------------------------------===// 1441// MONITORX/MWAITX Instructions 1442// 1443let SchedRW = [ WriteSystem ] in { 1444 let Uses = [ EAX, ECX, EDX ] in 1445 def MONITORX32rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 1446 TB, Requires<[ HasMWAITX, Not64BitMode ]>; 1447 let Uses = [ RAX, ECX, EDX ] in 1448 def MONITORX64rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 1449 TB, Requires<[ HasMWAITX, In64BitMode ]>; 1450 1451 let Uses = [ ECX, EAX, EBX ] in { 1452 def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", 1453 []>, TB, Requires<[ HasMWAITX ]>; 1454 } 1455} // SchedRW 1456 1457//===----------------------------------------------------------------------===// 1458// WAITPKG Instructions 1459// 1460let SchedRW = [WriteSystem] in { 1461 def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), 1462 "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, 1463 XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; 1464 def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), 1465 "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, 1466 XS, AdSize32, Requires<[HasWAITPKG]>; 1467 def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), 1468 "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, 1469 XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; 1470 let Uses = [EAX, EDX], Defs = [EFLAGS] in { 1471 def UMWAIT : I<0xAE, MRM6r, 1472 (outs), (ins GR32orGR64:$src), "umwait\t$src", 1473 [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, 1474 XD, Requires<[HasWAITPKG]>; 1475 def TPAUSE : I<0xAE, MRM6r, 1476 (outs), (ins GR32orGR64:$src), "tpause\t$src", 1477 [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, 1478 PD, Requires<[HasWAITPKG]>; 1479 } 1480} // SchedRW 1481 1482//===----------------------------------------------------------------------===// 1483// MOVDIRI - Move doubleword/quadword as direct store 1484// 1485let SchedRW = [WriteStore] in { 1486def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1487 "movdiri\t{$src, $dst|$dst, $src}", 1488 [(int_x86_directstore32 addr:$dst, GR32:$src)]>, 1489 T8PS, Requires<[HasMOVDIRI]>; 1490def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1491 "movdiri\t{$src, $dst|$dst, $src}", 1492 [(int_x86_directstore64 addr:$dst, GR64:$src)]>, 1493 T8PS, Requires<[In64BitMode, HasMOVDIRI]>; 1494} // SchedRW 1495 1496//===----------------------------------------------------------------------===// 1497// MOVDIR64B - Move 64 bytes as direct store 1498// 1499let SchedRW = [WriteStore] in { 1500def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src), 1501 "movdir64b\t{$src, $dst|$dst, $src}", []>, 1502 T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; 1503def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src), 1504 "movdir64b\t{$src, $dst|$dst, $src}", 1505 [(int_x86_movdir64b GR32:$dst, addr:$src)]>, 1506 T8PD, AdSize32, Requires<[HasMOVDIR64B]>; 1507def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src), 1508 "movdir64b\t{$src, $dst|$dst, $src}", 1509 [(int_x86_movdir64b GR64:$dst, addr:$src)]>, 1510 T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; 1511} // SchedRW 1512 1513//===----------------------------------------------------------------------===// 1514// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity 1515// 1516let SchedRW = [WriteStore], Defs = [EFLAGS] in { 1517 def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 1518 "enqcmd\t{$src, $dst|$dst, $src}", 1519 [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>, 1520 T8XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; 1521 def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 1522 "enqcmd\t{$src, $dst|$dst, $src}", 1523 [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>, 1524 T8XD, AdSize32, Requires<[HasENQCMD]>; 1525 def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 1526 "enqcmd\t{$src, $dst|$dst, $src}", 1527 [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>, 1528 T8XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>; 1529 1530 def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 1531 "enqcmds\t{$src, $dst|$dst, $src}", 1532 [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>, 1533 T8XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; 1534 def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 1535 "enqcmds\t{$src, $dst|$dst, $src}", 1536 [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>, 1537 T8XS, AdSize32, Requires<[HasENQCMD]>; 1538 def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 1539 "enqcmds\t{$src, $dst|$dst, $src}", 1540 [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>, 1541 T8XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>; 1542} 1543 1544//===----------------------------------------------------------------------===// 1545// CLZERO Instruction 1546// 1547let SchedRW = [WriteLoad] in { 1548 let Uses = [EAX] in 1549 def CLZERO32r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 1550 TB, Requires<[HasCLZERO, Not64BitMode]>; 1551 let Uses = [RAX] in 1552 def CLZERO64r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 1553 TB, Requires<[HasCLZERO, In64BitMode]>; 1554} // SchedRW 1555 1556//===----------------------------------------------------------------------===// 1557// INVLPGB Instruction 1558// OPCODE 0F 01 FE 1559// 1560let SchedRW = [WriteSystem] in { 1561 let Uses = [EAX, EDX] in 1562 def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins), 1563 "invlpgb", []>, 1564 PS, Requires<[Not64BitMode]>; 1565 let Uses = [RAX, EDX] in 1566 def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins), 1567 "invlpgb", []>, 1568 PS, Requires<[In64BitMode]>; 1569} // SchedRW 1570 1571//===----------------------------------------------------------------------===// 1572// TLBSYNC Instruction 1573// OPCODE 0F 01 FF 1574// 1575let SchedRW = [WriteSystem] in { 1576 def TLBSYNC : I<0x01, MRM_FF, (outs), (ins), 1577 "tlbsync", []>, 1578 PS, Requires<[]>; 1579} // SchedRW 1580 1581//===----------------------------------------------------------------------===// 1582// HRESET Instruction 1583// 1584let Uses = [EAX], SchedRW = [WriteSystem] in 1585 def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>, 1586 Requires<[HasHRESET]>, TAXS; 1587 1588//===----------------------------------------------------------------------===// 1589// SERIALIZE Instruction 1590// 1591let SchedRW = [WriteSystem] in 1592 def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize", 1593 [(int_x86_serialize)]>, PS, 1594 Requires<[HasSERIALIZE]>; 1595 1596//===----------------------------------------------------------------------===// 1597// TSXLDTRK - TSX Suspend Load Address Tracking 1598// 1599let Predicates = [HasTSXLDTRK], SchedRW = [WriteSystem] in { 1600 def XSUSLDTRK : I<0x01, MRM_E8, (outs), (ins), "xsusldtrk", 1601 [(int_x86_xsusldtrk)]>, XD; 1602 def XRESLDTRK : I<0x01, MRM_E9, (outs), (ins), "xresldtrk", 1603 [(int_x86_xresldtrk)]>, XD; 1604} 1605 1606//===----------------------------------------------------------------------===// 1607// UINTR Instructions 1608// 1609let Predicates = [HasUINTR, In64BitMode], SchedRW = [WriteSystem] in { 1610 def UIRET : I<0x01, MRM_EC, (outs), (ins), "uiret", 1611 []>, XS; 1612 def CLUI : I<0x01, MRM_EE, (outs), (ins), "clui", 1613 [(int_x86_clui)]>, XS; 1614 def STUI : I<0x01, MRM_EF, (outs), (ins), "stui", 1615 [(int_x86_stui)]>, XS; 1616 1617 def SENDUIPI : I<0xC7, MRM6r, (outs), (ins GR64:$arg), "senduipi\t$arg", 1618 [(int_x86_senduipi GR64:$arg)]>, XS; 1619 1620 let Defs = [EFLAGS] in 1621 def TESTUI : I<0x01, MRM_ED, (outs), (ins), "testui", 1622 [(set EFLAGS, (X86testui))]>, XS; 1623} 1624 1625//===----------------------------------------------------------------------===// 1626// PREFETCHIT0 and PREFETCHIT1 Instructions 1627// prefetch ADDR, RW, Locality, Data 1628let Predicates = [HasPREFETCHI, In64BitMode], SchedRW = [WriteLoad] in { 1629 def PREFETCHIT0 : I<0x18, MRM7m, (outs), (ins i8mem:$src), 1630 "prefetchit0\t$src", [(prefetch addr:$src, (i32 0), (i32 3), (i32 0))]>, TB; 1631 def PREFETCHIT1 : I<0x18, MRM6m, (outs), (ins i8mem:$src), 1632 "prefetchit1\t$src", [(prefetch addr:$src, (i32 0), (i32 2), (i32 0))]>, TB; 1633} 1634 1635//===----------------------------------------------------------------------===// 1636// CMPCCXADD Instructions 1637// 1638let isCodeGenOnly = 1, ForceDisassemble = 1, mayLoad = 1, mayStore = 1, 1639 Predicates = [HasCMPCCXADD, In64BitMode], Defs = [EFLAGS], 1640 Constraints = "$dstsrc1 = $dst" in { 1641def CMPCCXADDmr32 : I<0xe0, MRMDestMem4VOp3CC, (outs GR32:$dst), 1642 (ins GR32:$dstsrc1, i32mem:$dstsrc2, GR32:$src3, ccode:$cond), 1643 "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 1644 [(set GR32:$dst, (X86cmpccxadd addr:$dstsrc2, 1645 GR32:$dstsrc1, GR32:$src3, timm:$cond))]>, 1646 VEX_4V, T8PD, Sched<[WriteXCHG]>; 1647 1648def CMPCCXADDmr64 : I<0xe0, MRMDestMem4VOp3CC, (outs GR64:$dst), 1649 (ins GR64:$dstsrc1, i64mem:$dstsrc2, GR64:$src3, ccode:$cond), 1650 "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 1651 [(set GR64:$dst, (X86cmpccxadd addr:$dstsrc2, 1652 GR64:$dstsrc1, GR64:$src3, timm:$cond))]>, 1653 VEX_4V, REX_W, T8PD, Sched<[WriteXCHG]>; 1654} 1655 1656//===----------------------------------------------------------------------===// 1657// Memory Instructions 1658// 1659 1660let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in 1661def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 1662 "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; 1663 1664let Predicates = [HasCLWB], SchedRW = [WriteLoad] in 1665def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", 1666 [(int_x86_clwb addr:$src)]>, PD; 1667 1668let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in 1669def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", 1670 [(int_x86_cldemote addr:$src)]>, PS; 1671